1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "accessories/link_fpga.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 50 #include "dm_helpers.h" 51 #include "link_enc_cfg.h" 52 #include "resource.h" 53 #include "dsc.h" 54 #include "dccg.h" 55 #include "clk_mgr.h" 56 #include "atomfirmware.h" 57 #define DC_LOGGER_INIT(logger) 58 59 #define LINK_INFO(...) \ 60 DC_LOG_HW_HOTPLUG( \ 61 __VA_ARGS__) 62 63 #define RETIMER_REDRIVER_INFO(...) \ 64 DC_LOG_RETIMER_REDRIVER( \ 65 __VA_ARGS__) 66 #include "dc/dcn30/dcn30_vpg.h" 67 68 #define MAX_MTP_SLOT_COUNT 64 69 #define LINK_TRAINING_ATTEMPTS 4 70 #define PEAK_FACTOR_X1000 1006 71 72 void link_blank_all_dp_displays(struct dc *dc) 73 { 74 unsigned int i; 75 uint8_t dpcd_power_state = '\0'; 76 enum dc_status status = DC_ERROR_UNEXPECTED; 77 78 for (i = 0; i < dc->link_count; i++) { 79 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 80 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 81 continue; 82 83 /* DP 2.0 spec requires that we read LTTPR caps first */ 84 dp_retrieve_lttpr_cap(dc->links[i]); 85 /* if any of the displays are lit up turn them off */ 86 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 87 &dpcd_power_state, sizeof(dpcd_power_state)); 88 89 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 90 link_blank_dp_stream(dc->links[i], true); 91 } 92 93 } 94 95 void link_blank_all_edp_displays(struct dc *dc) 96 { 97 unsigned int i; 98 uint8_t dpcd_power_state = '\0'; 99 enum dc_status status = DC_ERROR_UNEXPECTED; 100 101 for (i = 0; i < dc->link_count; i++) { 102 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 103 (!dc->links[i]->edp_sink_present)) 104 continue; 105 106 /* if any of the displays are lit up turn them off */ 107 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 108 &dpcd_power_state, sizeof(dpcd_power_state)); 109 110 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 111 link_blank_dp_stream(dc->links[i], true); 112 } 113 } 114 115 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 116 { 117 unsigned int j; 118 struct dc *dc = link->ctx->dc; 119 enum signal_type signal = link->connector_signal; 120 121 if ((signal == SIGNAL_TYPE_EDP) || 122 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 123 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 124 link->link_enc->funcs->get_dig_frontend && 125 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 126 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 127 128 if (fe != ENGINE_ID_UNKNOWN) 129 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 130 if (fe == dc->res_pool->stream_enc[j]->id) { 131 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 132 dc->res_pool->stream_enc[j]); 133 break; 134 } 135 } 136 } 137 138 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 139 dc_link_dp_receiver_power_ctrl(link, false); 140 } 141 } 142 143 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 144 { 145 struct pipe_ctx *pipes[MAX_PIPES]; 146 struct dc_state *state = link->dc->current_state; 147 uint8_t count; 148 int i; 149 struct dc_stream_update stream_update; 150 bool dpms_off = true; 151 struct link_resource link_res = {0}; 152 153 memset(&stream_update, 0, sizeof(stream_update)); 154 stream_update.dpms_off = &dpms_off; 155 156 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 157 158 for (i = 0; i < count; i++) { 159 stream_update.stream = pipes[i]->stream; 160 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 161 pipes[i]->stream, &stream_update, 162 state); 163 } 164 165 /* link can be also enabled by vbios. In this case it is not recorded 166 * in pipe_ctx. Disable link phy here to make sure it is completely off 167 */ 168 dp_disable_link_phy(link, &link_res, link->connector_signal); 169 } 170 171 void link_resume(struct dc_link *link) 172 { 173 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 174 program_hpd_filter(link); 175 } 176 177 /* This function returns true if the pipe is used to feed video signal directly 178 * to the link. 179 */ 180 static bool is_master_pipe_for_link(const struct dc_link *link, 181 const struct pipe_ctx *pipe) 182 { 183 return (pipe->stream && 184 pipe->stream->link && 185 pipe->stream->link == link && 186 pipe->top_pipe == NULL && 187 pipe->prev_odm_pipe == NULL); 188 } 189 190 /* 191 * This function finds all master pipes feeding to a given link with dpms set to 192 * on in given dc state. 193 */ 194 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 195 struct dc_state *state, 196 uint8_t *count, 197 struct pipe_ctx *pipes[MAX_PIPES]) 198 { 199 int i; 200 struct pipe_ctx *pipe = NULL; 201 202 *count = 0; 203 for (i = 0; i < MAX_PIPES; i++) { 204 pipe = &state->res_ctx.pipe_ctx[i]; 205 206 if (is_master_pipe_for_link(link, pipe) && 207 pipe->stream->dpms_off == false) { 208 pipes[(*count)++] = pipe; 209 } 210 } 211 } 212 213 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 214 enum engine_id eng_id, 215 struct ext_hdmi_settings *settings) 216 { 217 bool result = false; 218 int i = 0; 219 struct integrated_info *integrated_info = 220 pipe_ctx->stream->ctx->dc_bios->integrated_info; 221 222 if (integrated_info == NULL) 223 return false; 224 225 /* 226 * Get retimer settings from sbios for passing SI eye test for DCE11 227 * The setting values are varied based on board revision and port id 228 * Therefore the setting values of each ports is passed by sbios. 229 */ 230 231 // Check if current bios contains ext Hdmi settings 232 if (integrated_info->gpu_cap_info & 0x20) { 233 switch (eng_id) { 234 case ENGINE_ID_DIGA: 235 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 236 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 237 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 238 memmove(settings->reg_settings, 239 integrated_info->dp0_ext_hdmi_reg_settings, 240 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 241 memmove(settings->reg_settings_6g, 242 integrated_info->dp0_ext_hdmi_6g_reg_settings, 243 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 244 result = true; 245 break; 246 case ENGINE_ID_DIGB: 247 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 248 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 249 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 250 memmove(settings->reg_settings, 251 integrated_info->dp1_ext_hdmi_reg_settings, 252 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 253 memmove(settings->reg_settings_6g, 254 integrated_info->dp1_ext_hdmi_6g_reg_settings, 255 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 256 result = true; 257 break; 258 case ENGINE_ID_DIGC: 259 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 260 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 261 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 262 memmove(settings->reg_settings, 263 integrated_info->dp2_ext_hdmi_reg_settings, 264 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 265 memmove(settings->reg_settings_6g, 266 integrated_info->dp2_ext_hdmi_6g_reg_settings, 267 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 268 result = true; 269 break; 270 case ENGINE_ID_DIGD: 271 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 272 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 273 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 274 memmove(settings->reg_settings, 275 integrated_info->dp3_ext_hdmi_reg_settings, 276 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 277 memmove(settings->reg_settings_6g, 278 integrated_info->dp3_ext_hdmi_6g_reg_settings, 279 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 280 result = true; 281 break; 282 default: 283 break; 284 } 285 286 if (result == true) { 287 // Validate settings from bios integrated info table 288 if (settings->slv_addr == 0) 289 return false; 290 if (settings->reg_num > 9) 291 return false; 292 if (settings->reg_num_6g > 3) 293 return false; 294 295 for (i = 0; i < settings->reg_num; i++) { 296 if (settings->reg_settings[i].i2c_reg_index > 0x20) 297 return false; 298 } 299 300 for (i = 0; i < settings->reg_num_6g; i++) { 301 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 302 return false; 303 } 304 } 305 } 306 307 return result; 308 } 309 310 static bool write_i2c(struct pipe_ctx *pipe_ctx, 311 uint8_t address, uint8_t *buffer, uint32_t length) 312 { 313 struct i2c_command cmd = {0}; 314 struct i2c_payload payload = {0}; 315 316 memset(&payload, 0, sizeof(payload)); 317 memset(&cmd, 0, sizeof(cmd)); 318 319 cmd.number_of_payloads = 1; 320 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 321 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 322 323 payload.address = address; 324 payload.data = buffer; 325 payload.length = length; 326 payload.write = true; 327 cmd.payloads = &payload; 328 329 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 330 pipe_ctx->stream->link, &cmd)) 331 return true; 332 333 return false; 334 } 335 336 static void write_i2c_retimer_setting( 337 struct pipe_ctx *pipe_ctx, 338 bool is_vga_mode, 339 bool is_over_340mhz, 340 struct ext_hdmi_settings *settings) 341 { 342 uint8_t slave_address = (settings->slv_addr >> 1); 343 uint8_t buffer[2]; 344 const uint8_t apply_rx_tx_change = 0x4; 345 uint8_t offset = 0xA; 346 uint8_t value = 0; 347 int i = 0; 348 bool i2c_success = false; 349 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 350 351 memset(&buffer, 0, sizeof(buffer)); 352 353 /* Start Ext-Hdmi programming*/ 354 355 for (i = 0; i < settings->reg_num; i++) { 356 /* Apply 3G settings */ 357 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 358 359 buffer[0] = settings->reg_settings[i].i2c_reg_index; 360 buffer[1] = settings->reg_settings[i].i2c_reg_val; 361 i2c_success = write_i2c(pipe_ctx, slave_address, 362 buffer, sizeof(buffer)); 363 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 364 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 365 slave_address, buffer[0], buffer[1], i2c_success?1:0); 366 367 if (!i2c_success) 368 goto i2c_write_fail; 369 370 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 371 * needs to be set to 1 on every 0xA-0xC write. 372 */ 373 if (settings->reg_settings[i].i2c_reg_index == 0xA || 374 settings->reg_settings[i].i2c_reg_index == 0xB || 375 settings->reg_settings[i].i2c_reg_index == 0xC) { 376 377 /* Query current value from offset 0xA */ 378 if (settings->reg_settings[i].i2c_reg_index == 0xA) 379 value = settings->reg_settings[i].i2c_reg_val; 380 else { 381 i2c_success = 382 link_query_ddc_data( 383 pipe_ctx->stream->link->ddc, 384 slave_address, &offset, 1, &value, 1); 385 if (!i2c_success) 386 goto i2c_write_fail; 387 } 388 389 buffer[0] = offset; 390 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 391 buffer[1] = value | apply_rx_tx_change; 392 i2c_success = write_i2c(pipe_ctx, slave_address, 393 buffer, sizeof(buffer)); 394 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 395 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 396 slave_address, buffer[0], buffer[1], i2c_success?1:0); 397 if (!i2c_success) 398 goto i2c_write_fail; 399 } 400 } 401 } 402 403 /* Apply 3G settings */ 404 if (is_over_340mhz) { 405 for (i = 0; i < settings->reg_num_6g; i++) { 406 /* Apply 3G settings */ 407 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 408 409 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 410 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 411 i2c_success = write_i2c(pipe_ctx, slave_address, 412 buffer, sizeof(buffer)); 413 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 414 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 415 slave_address, buffer[0], buffer[1], i2c_success?1:0); 416 417 if (!i2c_success) 418 goto i2c_write_fail; 419 420 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 421 * needs to be set to 1 on every 0xA-0xC write. 422 */ 423 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 424 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 425 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 426 427 /* Query current value from offset 0xA */ 428 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 429 value = settings->reg_settings_6g[i].i2c_reg_val; 430 else { 431 i2c_success = 432 link_query_ddc_data( 433 pipe_ctx->stream->link->ddc, 434 slave_address, &offset, 1, &value, 1); 435 if (!i2c_success) 436 goto i2c_write_fail; 437 } 438 439 buffer[0] = offset; 440 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 441 buffer[1] = value | apply_rx_tx_change; 442 i2c_success = write_i2c(pipe_ctx, slave_address, 443 buffer, sizeof(buffer)); 444 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 445 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 446 slave_address, buffer[0], buffer[1], i2c_success?1:0); 447 if (!i2c_success) 448 goto i2c_write_fail; 449 } 450 } 451 } 452 } 453 454 if (is_vga_mode) { 455 /* Program additional settings if using 640x480 resolution */ 456 457 /* Write offset 0xFF to 0x01 */ 458 buffer[0] = 0xff; 459 buffer[1] = 0x01; 460 i2c_success = write_i2c(pipe_ctx, slave_address, 461 buffer, sizeof(buffer)); 462 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 463 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 464 slave_address, buffer[0], buffer[1], i2c_success?1:0); 465 if (!i2c_success) 466 goto i2c_write_fail; 467 468 /* Write offset 0x00 to 0x23 */ 469 buffer[0] = 0x00; 470 buffer[1] = 0x23; 471 i2c_success = write_i2c(pipe_ctx, slave_address, 472 buffer, sizeof(buffer)); 473 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 474 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 475 slave_address, buffer[0], buffer[1], i2c_success?1:0); 476 if (!i2c_success) 477 goto i2c_write_fail; 478 479 /* Write offset 0xff to 0x00 */ 480 buffer[0] = 0xff; 481 buffer[1] = 0x00; 482 i2c_success = write_i2c(pipe_ctx, slave_address, 483 buffer, sizeof(buffer)); 484 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 485 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 486 slave_address, buffer[0], buffer[1], i2c_success?1:0); 487 if (!i2c_success) 488 goto i2c_write_fail; 489 490 } 491 492 return; 493 494 i2c_write_fail: 495 DC_LOG_DEBUG("Set retimer failed"); 496 } 497 498 static void write_i2c_default_retimer_setting( 499 struct pipe_ctx *pipe_ctx, 500 bool is_vga_mode, 501 bool is_over_340mhz) 502 { 503 uint8_t slave_address = (0xBA >> 1); 504 uint8_t buffer[2]; 505 bool i2c_success = false; 506 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 507 508 memset(&buffer, 0, sizeof(buffer)); 509 510 /* Program Slave Address for tuning single integrity */ 511 /* Write offset 0x0A to 0x13 */ 512 buffer[0] = 0x0A; 513 buffer[1] = 0x13; 514 i2c_success = write_i2c(pipe_ctx, slave_address, 515 buffer, sizeof(buffer)); 516 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 517 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 518 slave_address, buffer[0], buffer[1], i2c_success?1:0); 519 if (!i2c_success) 520 goto i2c_write_fail; 521 522 /* Write offset 0x0A to 0x17 */ 523 buffer[0] = 0x0A; 524 buffer[1] = 0x17; 525 i2c_success = write_i2c(pipe_ctx, slave_address, 526 buffer, sizeof(buffer)); 527 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 528 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 529 slave_address, buffer[0], buffer[1], i2c_success?1:0); 530 if (!i2c_success) 531 goto i2c_write_fail; 532 533 /* Write offset 0x0B to 0xDA or 0xD8 */ 534 buffer[0] = 0x0B; 535 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 536 i2c_success = write_i2c(pipe_ctx, slave_address, 537 buffer, sizeof(buffer)); 538 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 539 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 540 slave_address, buffer[0], buffer[1], i2c_success?1:0); 541 if (!i2c_success) 542 goto i2c_write_fail; 543 544 /* Write offset 0x0A to 0x17 */ 545 buffer[0] = 0x0A; 546 buffer[1] = 0x17; 547 i2c_success = write_i2c(pipe_ctx, slave_address, 548 buffer, sizeof(buffer)); 549 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 550 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 551 slave_address, buffer[0], buffer[1], i2c_success?1:0); 552 if (!i2c_success) 553 goto i2c_write_fail; 554 555 /* Write offset 0x0C to 0x1D or 0x91 */ 556 buffer[0] = 0x0C; 557 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 558 i2c_success = write_i2c(pipe_ctx, slave_address, 559 buffer, sizeof(buffer)); 560 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 561 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 562 slave_address, buffer[0], buffer[1], i2c_success?1:0); 563 if (!i2c_success) 564 goto i2c_write_fail; 565 566 /* Write offset 0x0A to 0x17 */ 567 buffer[0] = 0x0A; 568 buffer[1] = 0x17; 569 i2c_success = write_i2c(pipe_ctx, slave_address, 570 buffer, sizeof(buffer)); 571 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 572 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 573 slave_address, buffer[0], buffer[1], i2c_success?1:0); 574 if (!i2c_success) 575 goto i2c_write_fail; 576 577 578 if (is_vga_mode) { 579 /* Program additional settings if using 640x480 resolution */ 580 581 /* Write offset 0xFF to 0x01 */ 582 buffer[0] = 0xff; 583 buffer[1] = 0x01; 584 i2c_success = write_i2c(pipe_ctx, slave_address, 585 buffer, sizeof(buffer)); 586 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 587 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 588 slave_address, buffer[0], buffer[1], i2c_success?1:0); 589 if (!i2c_success) 590 goto i2c_write_fail; 591 592 /* Write offset 0x00 to 0x23 */ 593 buffer[0] = 0x00; 594 buffer[1] = 0x23; 595 i2c_success = write_i2c(pipe_ctx, slave_address, 596 buffer, sizeof(buffer)); 597 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 598 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 599 slave_address, buffer[0], buffer[1], i2c_success?1:0); 600 if (!i2c_success) 601 goto i2c_write_fail; 602 603 /* Write offset 0xff to 0x00 */ 604 buffer[0] = 0xff; 605 buffer[1] = 0x00; 606 i2c_success = write_i2c(pipe_ctx, slave_address, 607 buffer, sizeof(buffer)); 608 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 609 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 610 slave_address, buffer[0], buffer[1], i2c_success?1:0); 611 if (!i2c_success) 612 goto i2c_write_fail; 613 } 614 615 return; 616 617 i2c_write_fail: 618 DC_LOG_DEBUG("Set default retimer failed"); 619 } 620 621 static void write_i2c_redriver_setting( 622 struct pipe_ctx *pipe_ctx, 623 bool is_over_340mhz) 624 { 625 uint8_t slave_address = (0xF0 >> 1); 626 uint8_t buffer[16]; 627 bool i2c_success = false; 628 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 629 630 memset(&buffer, 0, sizeof(buffer)); 631 632 // Program Slave Address for tuning single integrity 633 buffer[3] = 0x4E; 634 buffer[4] = 0x4E; 635 buffer[5] = 0x4E; 636 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 637 638 i2c_success = write_i2c(pipe_ctx, slave_address, 639 buffer, sizeof(buffer)); 640 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 641 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 642 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 643 i2c_success = %d\n", 644 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 645 646 if (!i2c_success) 647 DC_LOG_DEBUG("Set redriver failed"); 648 } 649 #if defined(CONFIG_DRM_AMD_DC_HDCP) 650 651 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 652 { 653 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 654 struct link_encoder *link_enc = NULL; 655 struct cp_psp_stream_config config = {0}; 656 enum dp_panel_mode panel_mode = 657 dp_get_panel_mode(pipe_ctx->stream->link); 658 659 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 660 return; 661 662 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 663 ASSERT(link_enc); 664 if (link_enc == NULL) 665 return; 666 667 /* otg instance */ 668 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 669 670 /* dig front end */ 671 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 672 673 /* stream encoder index */ 674 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 675 if (link_is_dp_128b_132b_signal(pipe_ctx)) 676 config.stream_enc_idx = 677 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 678 679 /* dig back end */ 680 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 681 682 /* link encoder index */ 683 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 684 if (link_is_dp_128b_132b_signal(pipe_ctx)) 685 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 686 687 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 688 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 689 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 690 else 691 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 692 693 694 /* phy index */ 695 config.phy_idx = resource_transmitter_to_phy_idx( 696 pipe_ctx->stream->link->dc, link_enc->transmitter); 697 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 698 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 699 config.phy_idx = 0; 700 701 /* stream properties */ 702 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 703 config.mst_enabled = (pipe_ctx->stream->signal == 704 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 705 config.dp2_enabled = link_is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0; 706 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 707 1 : 0; 708 config.dpms_off = dpms_off; 709 710 /* dm stream context */ 711 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 712 713 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 714 } 715 #endif 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 781 struct dc *dc = pipe_ctx->stream->ctx->dc; 782 struct dc_stream_state *stream = pipe_ctx->stream; 783 struct pipe_ctx *odm_pipe; 784 int opp_cnt = 1; 785 DC_LOGGER_INIT(dsc->ctx->logger); 786 787 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 788 opp_cnt++; 789 790 if (enable) { 791 struct dsc_config dsc_cfg; 792 struct dsc_optc_config dsc_optc_cfg; 793 enum optc_dsc_mode optc_dsc_mode; 794 795 /* Enable DSC hw block */ 796 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 797 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 798 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 799 dsc_cfg.color_depth = stream->timing.display_color_depth; 800 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 801 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 802 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 803 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 804 805 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 806 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 807 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 808 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 809 810 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 811 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 812 } 813 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 814 dsc_cfg.pic_width *= opp_cnt; 815 816 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 817 818 /* Enable DSC in encoder */ 819 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) 820 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 821 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 822 dsc_optc_config_log(dsc, &dsc_optc_cfg); 823 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 824 optc_dsc_mode, 825 dsc_optc_cfg.bytes_per_pixel, 826 dsc_optc_cfg.slice_width); 827 828 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 829 } 830 831 /* Enable DSC in OPTC */ 832 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 833 dsc_optc_config_log(dsc, &dsc_optc_cfg); 834 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 835 optc_dsc_mode, 836 dsc_optc_cfg.bytes_per_pixel, 837 dsc_optc_cfg.slice_width); 838 } else { 839 /* disable DSC in OPTC */ 840 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 841 pipe_ctx->stream_res.tg, 842 OPTC_DSC_DISABLED, 0, 0); 843 844 /* disable DSC in stream encoder */ 845 if (dc_is_dp_signal(stream->signal)) { 846 if (link_is_dp_128b_132b_signal(pipe_ctx)) 847 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 848 pipe_ctx->stream_res.hpo_dp_stream_enc, 849 false, 850 NULL, 851 true); 852 else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 853 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 854 pipe_ctx->stream_res.stream_enc, 855 OPTC_DSC_DISABLED, 0, 0); 856 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 857 pipe_ctx->stream_res.stream_enc, false, NULL, true); 858 } 859 } 860 861 /* disable DSC block */ 862 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 863 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 864 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 865 } 866 } 867 868 /* 869 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 870 * hence PPS info packet update need to use frame update instead of immediate update. 871 * Added parameter immediate_update for this purpose. 872 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 873 * which is the only place where a "false" would be passed in for param immediate_update. 874 * 875 * immediate_update is only applicable when DSC is enabled. 876 */ 877 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 878 { 879 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 880 struct dc_stream_state *stream = pipe_ctx->stream; 881 DC_LOGGER_INIT(dsc->ctx->logger); 882 883 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 884 return false; 885 886 if (enable) { 887 struct dsc_config dsc_cfg; 888 uint8_t dsc_packed_pps[128]; 889 890 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 891 memset(dsc_packed_pps, 0, 128); 892 893 /* Enable DSC hw block */ 894 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 895 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 896 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 897 dsc_cfg.color_depth = stream->timing.display_color_depth; 898 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 899 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 900 901 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 902 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 903 if (dc_is_dp_signal(stream->signal)) { 904 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 905 if (link_is_dp_128b_132b_signal(pipe_ctx)) 906 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 907 pipe_ctx->stream_res.hpo_dp_stream_enc, 908 true, 909 &dsc_packed_pps[0], 910 immediate_update); 911 else 912 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 913 pipe_ctx->stream_res.stream_enc, 914 true, 915 &dsc_packed_pps[0], 916 immediate_update); 917 } 918 } else { 919 /* disable DSC PPS in stream encoder */ 920 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 921 if (dc_is_dp_signal(stream->signal)) { 922 if (link_is_dp_128b_132b_signal(pipe_ctx)) 923 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 924 pipe_ctx->stream_res.hpo_dp_stream_enc, 925 false, 926 NULL, 927 true); 928 else 929 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 930 pipe_ctx->stream_res.stream_enc, false, NULL, true); 931 } 932 } 933 934 return true; 935 } 936 937 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 938 { 939 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 940 bool result = false; 941 942 if (!pipe_ctx->stream->timing.flags.DSC) 943 goto out; 944 if (!dsc) 945 goto out; 946 947 if (enable) { 948 { 949 link_set_dsc_on_stream(pipe_ctx, true); 950 result = true; 951 } 952 } else { 953 dp_set_dsc_on_rx(pipe_ctx, false); 954 link_set_dsc_on_stream(pipe_ctx, false); 955 result = true; 956 } 957 out: 958 return result; 959 } 960 961 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) 962 { 963 return link_update_dsc_config(pipe_ctx); 964 } 965 966 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 967 { 968 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 969 970 if (!pipe_ctx->stream->timing.flags.DSC) 971 return false; 972 if (!dsc) 973 return false; 974 975 link_set_dsc_on_stream(pipe_ctx, true); 976 link_set_dsc_pps_packet(pipe_ctx, true, false); 977 return true; 978 } 979 980 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 981 { 982 struct dc_stream_state *stream = pipe_ctx->stream; 983 984 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 985 struct dc_link *link = stream->link; 986 union down_spread_ctrl old_downspread; 987 union down_spread_ctrl new_downspread; 988 989 memset(&old_downspread, 0, sizeof(old_downspread)); 990 991 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 992 &old_downspread.raw, sizeof(old_downspread)); 993 994 new_downspread.raw = old_downspread.raw; 995 996 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 997 (stream->ignore_msa_timing_param) ? 1 : 0; 998 999 if (new_downspread.raw != old_downspread.raw) { 1000 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1001 &new_downspread.raw, sizeof(new_downspread)); 1002 } 1003 1004 } else { 1005 dm_helpers_mst_enable_stream_features(stream); 1006 } 1007 } 1008 1009 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1010 { 1011 const uint32_t VCP_Y_PRECISION = 1000; 1012 uint64_t vcp_x, vcp_y; 1013 DC_LOGGER_INIT(link->ctx->logger); 1014 1015 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1016 avg_time_slots_per_mtp = dc_fixpt_add( 1017 avg_time_slots_per_mtp, 1018 dc_fixpt_from_fraction( 1019 1, 1020 2*VCP_Y_PRECISION)); 1021 1022 vcp_x = dc_fixpt_floor( 1023 avg_time_slots_per_mtp); 1024 vcp_y = dc_fixpt_floor( 1025 dc_fixpt_mul_int( 1026 dc_fixpt_sub_int( 1027 avg_time_slots_per_mtp, 1028 dc_fixpt_floor( 1029 avg_time_slots_per_mtp)), 1030 VCP_Y_PRECISION)); 1031 1032 1033 if (link->type == dc_connection_mst_branch) 1034 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1035 "X: %llu " 1036 "Y: %llu/%d", 1037 vcp_x, 1038 vcp_y, 1039 VCP_Y_PRECISION); 1040 else 1041 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1042 "X: %llu " 1043 "Y: %llu/%d", 1044 vcp_x, 1045 vcp_y, 1046 VCP_Y_PRECISION); 1047 } 1048 1049 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1050 { 1051 struct fixed31_32 mbytes_per_sec; 1052 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, 1053 &stream->link->cur_link_settings); 1054 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1055 1056 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1057 1058 return dc_fixpt_div_int(mbytes_per_sec, 54); 1059 } 1060 1061 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1062 { 1063 struct fixed31_32 peak_kbps; 1064 uint32_t numerator = 0; 1065 uint32_t denominator = 1; 1066 1067 /* 1068 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1069 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1070 * common multiplier to render an integer PBN for all link rate/lane 1071 * counts combinations 1072 * calculate 1073 * peak_kbps *= (1006/1000) 1074 * peak_kbps *= (64/54) 1075 * peak_kbps *= 8 convert to bytes 1076 */ 1077 1078 numerator = 64 * PEAK_FACTOR_X1000; 1079 denominator = 54 * 8 * 1000 * 1000; 1080 kbps *= numerator; 1081 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1082 1083 return peak_kbps; 1084 } 1085 1086 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1087 { 1088 uint64_t kbps; 1089 1090 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1091 return get_pbn_from_bw_in_kbps(kbps); 1092 } 1093 1094 1095 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1096 static void get_lane_status( 1097 struct dc_link *link, 1098 uint32_t lane_count, 1099 union lane_status *status, 1100 union lane_align_status_updated *status_updated) 1101 { 1102 unsigned int lane; 1103 uint8_t dpcd_buf[3] = {0}; 1104 1105 if (status == NULL || status_updated == NULL) { 1106 return; 1107 } 1108 1109 core_link_read_dpcd( 1110 link, 1111 DP_LANE0_1_STATUS, 1112 dpcd_buf, 1113 sizeof(dpcd_buf)); 1114 1115 for (lane = 0; lane < lane_count; lane++) { 1116 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1117 } 1118 1119 status_updated->raw = dpcd_buf[2]; 1120 } 1121 1122 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1123 { 1124 /* 1125 * wait for ACT handled 1126 */ 1127 int i; 1128 const int act_retries = 30; 1129 enum act_return_status result = ACT_FAILED; 1130 union payload_table_update_status update_status = {0}; 1131 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1132 union lane_align_status_updated lane_status_updated; 1133 DC_LOGGER_INIT(link->ctx->logger); 1134 1135 if (link->aux_access_disabled) 1136 return true; 1137 for (i = 0; i < act_retries; i++) { 1138 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1139 1140 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1141 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1142 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1143 !dp_is_interlane_aligned(lane_status_updated)) { 1144 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1145 "polling for ACT handled."); 1146 result = ACT_LINK_LOST; 1147 break; 1148 } 1149 core_link_read_dpcd( 1150 link, 1151 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1152 &update_status.raw, 1153 1); 1154 1155 if (update_status.bits.ACT_HANDLED == 1) { 1156 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1157 result = ACT_SUCCESS; 1158 break; 1159 } 1160 1161 msleep(5); 1162 } 1163 1164 if (result == ACT_FAILED) { 1165 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1166 "continue on. Something is wrong with the branch."); 1167 } 1168 1169 return (result == ACT_SUCCESS); 1170 } 1171 1172 static void update_mst_stream_alloc_table( 1173 struct dc_link *link, 1174 struct stream_encoder *stream_enc, 1175 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1176 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1177 { 1178 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1179 struct link_mst_stream_allocation *dc_alloc; 1180 1181 int i; 1182 int j; 1183 1184 /* if DRM proposed_table has more than one new payload */ 1185 ASSERT(proposed_table->stream_count - 1186 link->mst_stream_alloc_table.stream_count < 2); 1187 1188 /* copy proposed_table to link, add stream encoder */ 1189 for (i = 0; i < proposed_table->stream_count; i++) { 1190 1191 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1192 dc_alloc = 1193 &link->mst_stream_alloc_table.stream_allocations[j]; 1194 1195 if (dc_alloc->vcp_id == 1196 proposed_table->stream_allocations[i].vcp_id) { 1197 1198 work_table[i] = *dc_alloc; 1199 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1200 break; /* exit j loop */ 1201 } 1202 } 1203 1204 /* new vcp_id */ 1205 if (j == link->mst_stream_alloc_table.stream_count) { 1206 work_table[i].vcp_id = 1207 proposed_table->stream_allocations[i].vcp_id; 1208 work_table[i].slot_count = 1209 proposed_table->stream_allocations[i].slot_count; 1210 work_table[i].stream_enc = stream_enc; 1211 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1212 } 1213 } 1214 1215 /* update link->mst_stream_alloc_table with work_table */ 1216 link->mst_stream_alloc_table.stream_count = 1217 proposed_table->stream_count; 1218 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1219 link->mst_stream_alloc_table.stream_allocations[i] = 1220 work_table[i]; 1221 } 1222 1223 static void remove_stream_from_alloc_table( 1224 struct dc_link *link, 1225 struct stream_encoder *dio_stream_enc, 1226 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1227 { 1228 int i = 0; 1229 struct link_mst_stream_allocation_table *table = 1230 &link->mst_stream_alloc_table; 1231 1232 if (hpo_dp_stream_enc) { 1233 for (; i < table->stream_count; i++) 1234 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1235 break; 1236 } else { 1237 for (; i < table->stream_count; i++) 1238 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1239 break; 1240 } 1241 1242 if (i < table->stream_count) { 1243 i++; 1244 for (; i < table->stream_count; i++) 1245 table->stream_allocations[i-1] = table->stream_allocations[i]; 1246 memset(&table->stream_allocations[table->stream_count-1], 0, 1247 sizeof(struct link_mst_stream_allocation)); 1248 table->stream_count--; 1249 } 1250 } 1251 1252 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1253 struct pipe_ctx *pipe_ctx) 1254 { 1255 struct dc_stream_state *stream = pipe_ctx->stream; 1256 struct dc_link *link = stream->link; 1257 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1258 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1259 int i; 1260 bool mst_mode = (link->type == dc_connection_mst_branch); 1261 /* adjust for drm changes*/ 1262 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1263 const struct dc_link_settings empty_link_settings = {0}; 1264 DC_LOGGER_INIT(link->ctx->logger); 1265 1266 if (link_hwss->ext.set_throttled_vcp_size) 1267 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1268 if (link_hwss->ext.set_hblank_min_symbol_width) 1269 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1270 &empty_link_settings, 1271 avg_time_slots_per_mtp); 1272 1273 if (dm_helpers_dp_mst_write_payload_allocation_table( 1274 stream->ctx, 1275 stream, 1276 &proposed_table, 1277 false)) 1278 update_mst_stream_alloc_table( 1279 link, 1280 pipe_ctx->stream_res.stream_enc, 1281 pipe_ctx->stream_res.hpo_dp_stream_enc, 1282 &proposed_table); 1283 else 1284 DC_LOG_WARNING("Failed to update" 1285 "MST allocation table for" 1286 "pipe idx:%d\n", 1287 pipe_ctx->pipe_idx); 1288 1289 DC_LOG_MST("%s" 1290 "stream_count: %d: ", 1291 __func__, 1292 link->mst_stream_alloc_table.stream_count); 1293 1294 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1295 DC_LOG_MST("stream_enc[%d]: %p " 1296 "stream[%d].hpo_dp_stream_enc: %p " 1297 "stream[%d].vcp_id: %d " 1298 "stream[%d].slot_count: %d\n", 1299 i, 1300 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1301 i, 1302 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1303 i, 1304 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1305 i, 1306 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1307 } 1308 1309 if (link_hwss->ext.update_stream_allocation_table == NULL || 1310 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1311 DC_LOG_DEBUG("Unknown encoding format\n"); 1312 return DC_ERROR_UNEXPECTED; 1313 } 1314 1315 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1316 &link->mst_stream_alloc_table); 1317 1318 if (mst_mode) { 1319 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1320 stream->ctx, 1321 stream); 1322 } 1323 1324 dm_helpers_dp_mst_send_payload_allocation( 1325 stream->ctx, 1326 stream, 1327 false); 1328 1329 return DC_OK; 1330 } 1331 1332 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1333 { 1334 struct dc_stream_state *stream = pipe_ctx->stream; 1335 struct dc_link *link = stream->link; 1336 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1337 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1338 int i; 1339 bool mst_mode = (link->type == dc_connection_mst_branch); 1340 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1341 const struct dc_link_settings empty_link_settings = {0}; 1342 DC_LOGGER_INIT(link->ctx->logger); 1343 1344 if (link->dc->debug.temp_mst_deallocation_sequence) 1345 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1346 1347 /* deallocate_mst_payload is called before disable link. When mode or 1348 * disable/enable monitor, new stream is created which is not in link 1349 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1350 * should not done. For new mode set, map_resources will get engine 1351 * for new stream, so stream_enc->id should be validated until here. 1352 */ 1353 1354 /* slot X.Y */ 1355 if (link_hwss->ext.set_throttled_vcp_size) 1356 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1357 if (link_hwss->ext.set_hblank_min_symbol_width) 1358 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1359 &empty_link_settings, 1360 avg_time_slots_per_mtp); 1361 1362 if (mst_mode) { 1363 /* when link is in mst mode, reply on mst manager to remove 1364 * payload 1365 */ 1366 if (dm_helpers_dp_mst_write_payload_allocation_table( 1367 stream->ctx, 1368 stream, 1369 &proposed_table, 1370 false)) 1371 update_mst_stream_alloc_table( 1372 link, 1373 pipe_ctx->stream_res.stream_enc, 1374 pipe_ctx->stream_res.hpo_dp_stream_enc, 1375 &proposed_table); 1376 else 1377 DC_LOG_WARNING("Failed to update" 1378 "MST allocation table for" 1379 "pipe idx:%d\n", 1380 pipe_ctx->pipe_idx); 1381 } else { 1382 /* when link is no longer in mst mode (mst hub unplugged), 1383 * remove payload with default dc logic 1384 */ 1385 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1386 pipe_ctx->stream_res.hpo_dp_stream_enc); 1387 } 1388 1389 DC_LOG_MST("%s" 1390 "stream_count: %d: ", 1391 __func__, 1392 link->mst_stream_alloc_table.stream_count); 1393 1394 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1395 DC_LOG_MST("stream_enc[%d]: %p " 1396 "stream[%d].hpo_dp_stream_enc: %p " 1397 "stream[%d].vcp_id: %d " 1398 "stream[%d].slot_count: %d\n", 1399 i, 1400 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1401 i, 1402 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1403 i, 1404 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1405 i, 1406 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1407 } 1408 1409 /* update mst stream allocation table hardware state */ 1410 if (link_hwss->ext.update_stream_allocation_table == NULL || 1411 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1412 DC_LOG_DEBUG("Unknown encoding format\n"); 1413 return DC_ERROR_UNEXPECTED; 1414 } 1415 1416 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1417 &link->mst_stream_alloc_table); 1418 1419 if (mst_mode) { 1420 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1421 stream->ctx, 1422 stream); 1423 1424 dm_helpers_dp_mst_send_payload_allocation( 1425 stream->ctx, 1426 stream, 1427 false); 1428 } 1429 1430 return DC_OK; 1431 } 1432 1433 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1434 * because stream_encoder is not exposed to dm 1435 */ 1436 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1437 { 1438 struct dc_stream_state *stream = pipe_ctx->stream; 1439 struct dc_link *link = stream->link; 1440 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1441 struct fixed31_32 avg_time_slots_per_mtp; 1442 struct fixed31_32 pbn; 1443 struct fixed31_32 pbn_per_slot; 1444 int i; 1445 enum act_return_status ret; 1446 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1447 DC_LOGGER_INIT(link->ctx->logger); 1448 1449 /* enable_link_dp_mst already check link->enabled_stream_count 1450 * and stream is in link->stream[]. This is called during set mode, 1451 * stream_enc is available. 1452 */ 1453 1454 /* get calculate VC payload for stream: stream_alloc */ 1455 if (dm_helpers_dp_mst_write_payload_allocation_table( 1456 stream->ctx, 1457 stream, 1458 &proposed_table, 1459 true)) 1460 update_mst_stream_alloc_table( 1461 link, 1462 pipe_ctx->stream_res.stream_enc, 1463 pipe_ctx->stream_res.hpo_dp_stream_enc, 1464 &proposed_table); 1465 else 1466 DC_LOG_WARNING("Failed to update" 1467 "MST allocation table for" 1468 "pipe idx:%d\n", 1469 pipe_ctx->pipe_idx); 1470 1471 DC_LOG_MST("%s " 1472 "stream_count: %d: \n ", 1473 __func__, 1474 link->mst_stream_alloc_table.stream_count); 1475 1476 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1477 DC_LOG_MST("stream_enc[%d]: %p " 1478 "stream[%d].hpo_dp_stream_enc: %p " 1479 "stream[%d].vcp_id: %d " 1480 "stream[%d].slot_count: %d\n", 1481 i, 1482 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1483 i, 1484 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1485 i, 1486 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1487 i, 1488 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1489 } 1490 1491 ASSERT(proposed_table.stream_count > 0); 1492 1493 /* program DP source TX for payload */ 1494 if (link_hwss->ext.update_stream_allocation_table == NULL || 1495 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1496 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1497 return DC_ERROR_UNEXPECTED; 1498 } 1499 1500 link_hwss->ext.update_stream_allocation_table(link, 1501 &pipe_ctx->link_res, 1502 &link->mst_stream_alloc_table); 1503 1504 /* send down message */ 1505 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1506 stream->ctx, 1507 stream); 1508 1509 if (ret != ACT_LINK_LOST) { 1510 dm_helpers_dp_mst_send_payload_allocation( 1511 stream->ctx, 1512 stream, 1513 true); 1514 } 1515 1516 /* slot X.Y for only current stream */ 1517 pbn_per_slot = get_pbn_per_slot(stream); 1518 if (pbn_per_slot.value == 0) { 1519 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1520 return DC_UNSUPPORTED_VALUE; 1521 } 1522 pbn = get_pbn_from_timing(pipe_ctx); 1523 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1524 1525 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1526 1527 if (link_hwss->ext.set_throttled_vcp_size) 1528 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1529 if (link_hwss->ext.set_hblank_min_symbol_width) 1530 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1531 &link->cur_link_settings, 1532 avg_time_slots_per_mtp); 1533 1534 return DC_OK; 1535 } 1536 1537 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1538 const struct dc_stream_state *stream, 1539 const struct dc_link *link) 1540 { 1541 struct fixed31_32 link_bw_effective = 1542 dc_fixpt_from_int( 1543 dc_link_bandwidth_kbps(link, &link->cur_link_settings)); 1544 struct fixed31_32 timeslot_bw_effective = 1545 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1546 struct fixed31_32 timing_bw = 1547 dc_fixpt_from_int( 1548 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1549 struct fixed31_32 avg_time_slots_per_mtp = 1550 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1551 1552 return avg_time_slots_per_mtp; 1553 } 1554 1555 1556 static bool write_128b_132b_sst_payload_allocation_table( 1557 const struct dc_stream_state *stream, 1558 struct dc_link *link, 1559 struct link_mst_stream_allocation_table *proposed_table, 1560 bool allocate) 1561 { 1562 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1563 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1564 bool result = false; 1565 uint8_t req_slot_count = 0; 1566 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1567 union payload_table_update_status update_status = { 0 }; 1568 const uint32_t max_retries = 30; 1569 uint32_t retries = 0; 1570 DC_LOGGER_INIT(link->ctx->logger); 1571 1572 if (allocate) { 1573 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1574 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1575 /// Validation should filter out modes that exceed link BW 1576 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1577 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1578 return false; 1579 } else { 1580 /// Leave req_slot_count = 0 if allocate is false. 1581 } 1582 1583 proposed_table->stream_count = 1; /// Always 1 stream for SST 1584 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1585 proposed_table->stream_allocations[0].vcp_id = vc_id; 1586 1587 if (link->aux_access_disabled) 1588 return true; 1589 1590 /// Write DPCD 2C0 = 1 to start updating 1591 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1592 core_link_write_dpcd( 1593 link, 1594 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1595 &update_status.raw, 1596 1); 1597 1598 /// Program the changes in DPCD 1C0 - 1C2 1599 ASSERT(vc_id == 1); 1600 core_link_write_dpcd( 1601 link, 1602 DP_PAYLOAD_ALLOCATE_SET, 1603 &vc_id, 1604 1); 1605 1606 ASSERT(start_time_slot == 0); 1607 core_link_write_dpcd( 1608 link, 1609 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1610 &start_time_slot, 1611 1); 1612 1613 core_link_write_dpcd( 1614 link, 1615 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1616 &req_slot_count, 1617 1); 1618 1619 /// Poll till DPCD 2C0 read 1 1620 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1621 1622 while (retries < max_retries) { 1623 if (core_link_read_dpcd( 1624 link, 1625 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1626 &update_status.raw, 1627 1) == DC_OK) { 1628 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1629 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1630 result = true; 1631 break; 1632 } 1633 } else { 1634 union dpcd_rev dpcdRev; 1635 1636 if (core_link_read_dpcd( 1637 link, 1638 DP_DPCD_REV, 1639 &dpcdRev.raw, 1640 1) != DC_OK) { 1641 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1642 "of sink while polling payload table " 1643 "updated status bit."); 1644 break; 1645 } 1646 } 1647 retries++; 1648 msleep(5); 1649 } 1650 1651 if (!result && retries == max_retries) { 1652 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1653 "continue on. Something is wrong with the branch."); 1654 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1655 } 1656 1657 return result; 1658 } 1659 1660 /* 1661 * Payload allocation/deallocation for SST introduced in DP2.0 1662 */ 1663 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1664 bool allocate) 1665 { 1666 struct dc_stream_state *stream = pipe_ctx->stream; 1667 struct dc_link *link = stream->link; 1668 struct link_mst_stream_allocation_table proposed_table = {0}; 1669 struct fixed31_32 avg_time_slots_per_mtp; 1670 const struct dc_link_settings empty_link_settings = {0}; 1671 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1672 DC_LOGGER_INIT(link->ctx->logger); 1673 1674 /* slot X.Y for SST payload deallocate */ 1675 if (!allocate) { 1676 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1677 1678 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1679 1680 if (link_hwss->ext.set_throttled_vcp_size) 1681 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1682 avg_time_slots_per_mtp); 1683 if (link_hwss->ext.set_hblank_min_symbol_width) 1684 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1685 &empty_link_settings, 1686 avg_time_slots_per_mtp); 1687 } 1688 1689 /* calculate VC payload and update branch with new payload allocation table*/ 1690 if (!write_128b_132b_sst_payload_allocation_table( 1691 stream, 1692 link, 1693 &proposed_table, 1694 allocate)) { 1695 DC_LOG_ERROR("SST Update Payload: Failed to update " 1696 "allocation table for " 1697 "pipe idx: %d\n", 1698 pipe_ctx->pipe_idx); 1699 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1700 } 1701 1702 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1703 1704 ASSERT(proposed_table.stream_count == 1); 1705 1706 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1707 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1708 "vcp_id: %d " 1709 "slot_count: %d\n", 1710 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1711 proposed_table.stream_allocations[0].vcp_id, 1712 proposed_table.stream_allocations[0].slot_count); 1713 1714 /* program DP source TX for payload */ 1715 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1716 &proposed_table); 1717 1718 /* poll for ACT handled */ 1719 if (!poll_for_allocation_change_trigger(link)) { 1720 // Failures will result in blackscreen and errors logged 1721 BREAK_TO_DEBUGGER(); 1722 } 1723 1724 /* slot X.Y for SST payload allocate */ 1725 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1726 DP_128b_132b_ENCODING) { 1727 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1728 1729 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1730 1731 if (link_hwss->ext.set_throttled_vcp_size) 1732 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1733 avg_time_slots_per_mtp); 1734 if (link_hwss->ext.set_hblank_min_symbol_width) 1735 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1736 &link->cur_link_settings, 1737 avg_time_slots_per_mtp); 1738 } 1739 1740 /* Always return DC_OK. 1741 * If part of sequence fails, log failure(s) and show blackscreen 1742 */ 1743 return DC_OK; 1744 } 1745 1746 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1747 { 1748 struct dc_stream_state *stream = pipe_ctx->stream; 1749 struct dc_link *link = stream->link; 1750 struct fixed31_32 avg_time_slots_per_mtp; 1751 struct fixed31_32 pbn; 1752 struct fixed31_32 pbn_per_slot; 1753 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1754 uint8_t i; 1755 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1756 DC_LOGGER_INIT(link->ctx->logger); 1757 1758 /* decrease throttled vcp size */ 1759 pbn_per_slot = get_pbn_per_slot(stream); 1760 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1761 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1762 1763 if (link_hwss->ext.set_throttled_vcp_size) 1764 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1765 if (link_hwss->ext.set_hblank_min_symbol_width) 1766 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1767 &link->cur_link_settings, 1768 avg_time_slots_per_mtp); 1769 1770 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1771 dm_helpers_dp_mst_send_payload_allocation( 1772 stream->ctx, 1773 stream, 1774 true); 1775 1776 /* notify immediate branch device table update */ 1777 if (dm_helpers_dp_mst_write_payload_allocation_table( 1778 stream->ctx, 1779 stream, 1780 &proposed_table, 1781 true)) { 1782 /* update mst stream allocation table software state */ 1783 update_mst_stream_alloc_table( 1784 link, 1785 pipe_ctx->stream_res.stream_enc, 1786 pipe_ctx->stream_res.hpo_dp_stream_enc, 1787 &proposed_table); 1788 } else { 1789 DC_LOG_WARNING("Failed to update" 1790 "MST allocation table for" 1791 "pipe idx:%d\n", 1792 pipe_ctx->pipe_idx); 1793 } 1794 1795 DC_LOG_MST("%s " 1796 "stream_count: %d: \n ", 1797 __func__, 1798 link->mst_stream_alloc_table.stream_count); 1799 1800 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1801 DC_LOG_MST("stream_enc[%d]: %p " 1802 "stream[%d].hpo_dp_stream_enc: %p " 1803 "stream[%d].vcp_id: %d " 1804 "stream[%d].slot_count: %d\n", 1805 i, 1806 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1807 i, 1808 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1809 i, 1810 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1811 i, 1812 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1813 } 1814 1815 ASSERT(proposed_table.stream_count > 0); 1816 1817 /* update mst stream allocation table hardware state */ 1818 if (link_hwss->ext.update_stream_allocation_table == NULL || 1819 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1820 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1821 return DC_ERROR_UNEXPECTED; 1822 } 1823 1824 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1825 &link->mst_stream_alloc_table); 1826 1827 /* poll for immediate branch device ACT handled */ 1828 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1829 stream->ctx, 1830 stream); 1831 1832 return DC_OK; 1833 } 1834 1835 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1836 { 1837 struct dc_stream_state *stream = pipe_ctx->stream; 1838 struct dc_link *link = stream->link; 1839 struct fixed31_32 avg_time_slots_per_mtp; 1840 struct fixed31_32 pbn; 1841 struct fixed31_32 pbn_per_slot; 1842 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1843 uint8_t i; 1844 enum act_return_status ret; 1845 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1846 DC_LOGGER_INIT(link->ctx->logger); 1847 1848 /* notify immediate branch device table update */ 1849 if (dm_helpers_dp_mst_write_payload_allocation_table( 1850 stream->ctx, 1851 stream, 1852 &proposed_table, 1853 true)) { 1854 /* update mst stream allocation table software state */ 1855 update_mst_stream_alloc_table( 1856 link, 1857 pipe_ctx->stream_res.stream_enc, 1858 pipe_ctx->stream_res.hpo_dp_stream_enc, 1859 &proposed_table); 1860 } 1861 1862 DC_LOG_MST("%s " 1863 "stream_count: %d: \n ", 1864 __func__, 1865 link->mst_stream_alloc_table.stream_count); 1866 1867 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1868 DC_LOG_MST("stream_enc[%d]: %p " 1869 "stream[%d].hpo_dp_stream_enc: %p " 1870 "stream[%d].vcp_id: %d " 1871 "stream[%d].slot_count: %d\n", 1872 i, 1873 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1874 i, 1875 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1876 i, 1877 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1878 i, 1879 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1880 } 1881 1882 ASSERT(proposed_table.stream_count > 0); 1883 1884 /* update mst stream allocation table hardware state */ 1885 if (link_hwss->ext.update_stream_allocation_table == NULL || 1886 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1887 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1888 return DC_ERROR_UNEXPECTED; 1889 } 1890 1891 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1892 &link->mst_stream_alloc_table); 1893 1894 /* poll for immediate branch device ACT handled */ 1895 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1896 stream->ctx, 1897 stream); 1898 1899 if (ret != ACT_LINK_LOST) { 1900 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1901 dm_helpers_dp_mst_send_payload_allocation( 1902 stream->ctx, 1903 stream, 1904 true); 1905 } 1906 1907 /* increase throttled vcp size */ 1908 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1909 pbn_per_slot = get_pbn_per_slot(stream); 1910 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1911 1912 if (link_hwss->ext.set_throttled_vcp_size) 1913 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1914 if (link_hwss->ext.set_hblank_min_symbol_width) 1915 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1916 &link->cur_link_settings, 1917 avg_time_slots_per_mtp); 1918 1919 return DC_OK; 1920 } 1921 1922 static void disable_link_dp(struct dc_link *link, 1923 const struct link_resource *link_res, 1924 enum signal_type signal) 1925 { 1926 struct dc_link_settings link_settings = link->cur_link_settings; 1927 1928 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1929 link->mst_stream_alloc_table.stream_count > 0) 1930 /* disable MST link only when last vc payload is deallocated */ 1931 return; 1932 1933 dp_disable_link_phy(link, link_res, signal); 1934 1935 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1936 /* set the sink to SST mode after disabling the link */ 1937 enable_mst_on_sink(link, false); 1938 1939 if (link_dp_get_encoding_format(&link_settings) == 1940 DP_8b_10b_ENCODING) { 1941 dp_set_fec_enable(link, false); 1942 dp_set_fec_ready(link, link_res, false); 1943 } 1944 } 1945 1946 static void disable_link(struct dc_link *link, 1947 const struct link_resource *link_res, 1948 enum signal_type signal) 1949 { 1950 if (dc_is_dp_signal(signal)) { 1951 disable_link_dp(link, link_res, signal); 1952 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1953 link->dc->hwss.disable_link_output(link, link_res, signal); 1954 } 1955 1956 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1957 /* MST disable link only when no stream use the link */ 1958 if (link->mst_stream_alloc_table.stream_count <= 0) 1959 link->link_status.link_active = false; 1960 } else { 1961 link->link_status.link_active = false; 1962 } 1963 } 1964 1965 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1966 { 1967 struct dc_stream_state *stream = pipe_ctx->stream; 1968 struct dc_link *link = stream->link; 1969 enum dc_color_depth display_color_depth; 1970 enum engine_id eng_id; 1971 struct ext_hdmi_settings settings = {0}; 1972 bool is_over_340mhz = false; 1973 bool is_vga_mode = (stream->timing.h_addressable == 640) 1974 && (stream->timing.v_addressable == 480); 1975 struct dc *dc = pipe_ctx->stream->ctx->dc; 1976 1977 if (stream->phy_pix_clk == 0) 1978 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1979 if (stream->phy_pix_clk > 340000) 1980 is_over_340mhz = true; 1981 1982 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1983 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1984 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1985 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1986 /* DP159, Retimer settings */ 1987 eng_id = pipe_ctx->stream_res.stream_enc->id; 1988 1989 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1990 write_i2c_retimer_setting(pipe_ctx, 1991 is_vga_mode, is_over_340mhz, &settings); 1992 } else { 1993 write_i2c_default_retimer_setting(pipe_ctx, 1994 is_vga_mode, is_over_340mhz); 1995 } 1996 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1997 /* PI3EQX1204, Redriver settings */ 1998 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1999 } 2000 } 2001 2002 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2003 write_scdc_data( 2004 stream->link->ddc, 2005 stream->phy_pix_clk, 2006 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2007 2008 memset(&stream->link->cur_link_settings, 0, 2009 sizeof(struct dc_link_settings)); 2010 2011 display_color_depth = stream->timing.display_color_depth; 2012 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2013 display_color_depth = COLOR_DEPTH_888; 2014 2015 dc->hwss.enable_tmds_link_output( 2016 link, 2017 &pipe_ctx->link_res, 2018 pipe_ctx->stream->signal, 2019 pipe_ctx->clock_source->id, 2020 display_color_depth, 2021 stream->phy_pix_clk); 2022 2023 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2024 read_scdc_data(link->ddc); 2025 } 2026 2027 static enum dc_status enable_link_dp(struct dc_state *state, 2028 struct pipe_ctx *pipe_ctx) 2029 { 2030 struct dc_stream_state *stream = pipe_ctx->stream; 2031 enum dc_status status; 2032 bool skip_video_pattern; 2033 struct dc_link *link = stream->link; 2034 const struct dc_link_settings *link_settings = 2035 &pipe_ctx->link_config.dp_link_settings; 2036 bool fec_enable; 2037 int i; 2038 bool apply_seamless_boot_optimization = false; 2039 uint32_t bl_oled_enable_delay = 50; // in ms 2040 uint32_t post_oui_delay = 30; // 30ms 2041 /* Reduce link bandwidth between failed link training attempts. */ 2042 bool do_fallback = false; 2043 2044 // check for seamless boot 2045 for (i = 0; i < state->stream_count; i++) { 2046 if (state->streams[i]->apply_seamless_boot_optimization) { 2047 apply_seamless_boot_optimization = true; 2048 break; 2049 } 2050 } 2051 2052 /* Train with fallback when enabling DPIA link. Conventional links are 2053 * trained with fallback during sink detection. 2054 */ 2055 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2056 do_fallback = true; 2057 2058 /* 2059 * Temporary w/a to get DP2.0 link rates to work with SST. 2060 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2061 */ 2062 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2063 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2064 link->dc->debug.set_mst_en_for_sst) { 2065 enable_mst_on_sink(link, true); 2066 } 2067 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2068 /*in case it is not on*/ 2069 if (!link->dc->config.edp_no_power_sequencing) 2070 link->dc->hwss.edp_power_control(link, true); 2071 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2072 } 2073 2074 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2075 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2076 } else { 2077 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2078 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2079 if (state->clk_mgr && !apply_seamless_boot_optimization) 2080 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2081 state, false); 2082 } 2083 2084 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2085 dpcd_set_source_specific_data(link); 2086 if (link->dpcd_sink_ext_caps.raw != 0) { 2087 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2088 msleep(post_oui_delay); 2089 } 2090 2091 // similarly, mode switch can cause loss of cable ID 2092 dpcd_write_cable_id_to_dprx(link); 2093 2094 skip_video_pattern = true; 2095 2096 if (link_settings->link_rate == LINK_RATE_LOW) 2097 skip_video_pattern = false; 2098 2099 if (perform_link_training_with_retries(link_settings, 2100 skip_video_pattern, 2101 LINK_TRAINING_ATTEMPTS, 2102 pipe_ctx, 2103 pipe_ctx->stream->signal, 2104 do_fallback)) { 2105 status = DC_OK; 2106 } else { 2107 status = DC_FAIL_DP_LINK_TRAINING; 2108 } 2109 2110 if (link->preferred_training_settings.fec_enable) 2111 fec_enable = *link->preferred_training_settings.fec_enable; 2112 else 2113 fec_enable = true; 2114 2115 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2116 dp_set_fec_enable(link, fec_enable); 2117 2118 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2119 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2120 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2121 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2122 set_default_brightness_aux(link); // TODO: use cached if known 2123 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2124 msleep(bl_oled_enable_delay); 2125 link_backlight_enable_aux(link, true); 2126 } 2127 2128 return status; 2129 } 2130 2131 static enum dc_status enable_link_edp( 2132 struct dc_state *state, 2133 struct pipe_ctx *pipe_ctx) 2134 { 2135 return enable_link_dp(state, pipe_ctx); 2136 } 2137 2138 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2139 { 2140 struct dc_stream_state *stream = pipe_ctx->stream; 2141 struct dc_link *link = stream->link; 2142 struct dc *dc = stream->ctx->dc; 2143 2144 if (stream->phy_pix_clk == 0) 2145 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2146 2147 memset(&stream->link->cur_link_settings, 0, 2148 sizeof(struct dc_link_settings)); 2149 dc->hwss.enable_lvds_link_output( 2150 link, 2151 &pipe_ctx->link_res, 2152 pipe_ctx->clock_source->id, 2153 stream->phy_pix_clk); 2154 2155 } 2156 2157 static enum dc_status enable_link_dp_mst( 2158 struct dc_state *state, 2159 struct pipe_ctx *pipe_ctx) 2160 { 2161 struct dc_link *link = pipe_ctx->stream->link; 2162 2163 /* sink signal type after MST branch is MST. Multiple MST sinks 2164 * share one link. Link DP PHY is enable or training only once. 2165 */ 2166 if (link->link_status.link_active) 2167 return DC_OK; 2168 2169 /* clear payload table */ 2170 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2171 2172 /* to make sure the pending down rep can be processed 2173 * before enabling the link 2174 */ 2175 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2176 2177 /* set the sink to MST mode before enabling the link */ 2178 enable_mst_on_sink(link, true); 2179 2180 return enable_link_dp(state, pipe_ctx); 2181 } 2182 2183 static enum dc_status enable_link( 2184 struct dc_state *state, 2185 struct pipe_ctx *pipe_ctx) 2186 { 2187 enum dc_status status = DC_ERROR_UNEXPECTED; 2188 struct dc_stream_state *stream = pipe_ctx->stream; 2189 struct dc_link *link = stream->link; 2190 2191 /* There's some scenarios where driver is unloaded with display 2192 * still enabled. When driver is reloaded, it may cause a display 2193 * to not light up if there is a mismatch between old and new 2194 * link settings. Need to call disable first before enabling at 2195 * new link settings. 2196 */ 2197 if (link->link_status.link_active) { 2198 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2199 } 2200 2201 switch (pipe_ctx->stream->signal) { 2202 case SIGNAL_TYPE_DISPLAY_PORT: 2203 status = enable_link_dp(state, pipe_ctx); 2204 break; 2205 case SIGNAL_TYPE_EDP: 2206 status = enable_link_edp(state, pipe_ctx); 2207 break; 2208 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2209 status = enable_link_dp_mst(state, pipe_ctx); 2210 msleep(200); 2211 break; 2212 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2213 case SIGNAL_TYPE_DVI_DUAL_LINK: 2214 case SIGNAL_TYPE_HDMI_TYPE_A: 2215 enable_link_hdmi(pipe_ctx); 2216 status = DC_OK; 2217 break; 2218 case SIGNAL_TYPE_LVDS: 2219 enable_link_lvds(pipe_ctx); 2220 status = DC_OK; 2221 break; 2222 case SIGNAL_TYPE_VIRTUAL: 2223 status = DC_OK; 2224 break; 2225 default: 2226 break; 2227 } 2228 2229 if (status == DC_OK) { 2230 pipe_ctx->stream->link->link_status.link_active = true; 2231 } 2232 2233 return status; 2234 } 2235 2236 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2237 { 2238 struct dc *dc = pipe_ctx->stream->ctx->dc; 2239 struct dc_stream_state *stream = pipe_ctx->stream; 2240 struct dc_link *link = stream->sink->link; 2241 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2242 2243 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2244 2245 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2246 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2247 2248 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2249 2250 if (pipe_ctx->stream->sink) { 2251 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2252 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2253 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2254 pipe_ctx->stream->sink->edid_caps.display_name, 2255 pipe_ctx->stream->signal); 2256 } 2257 } 2258 2259 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2260 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2261 return; 2262 2263 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2264 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2265 set_avmute(pipe_ctx, true); 2266 } 2267 2268 dc->hwss.disable_audio_stream(pipe_ctx); 2269 2270 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2271 update_psp_stream_config(pipe_ctx, true); 2272 #endif 2273 dc->hwss.blank_stream(pipe_ctx); 2274 2275 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2276 deallocate_mst_payload(pipe_ctx); 2277 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2278 link_is_dp_128b_132b_signal(pipe_ctx)) 2279 update_sst_payload(pipe_ctx, false); 2280 2281 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2282 struct ext_hdmi_settings settings = {0}; 2283 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2284 2285 unsigned short masked_chip_caps = link->chip_caps & 2286 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2287 //Need to inform that sink is going to use legacy HDMI mode. 2288 write_scdc_data( 2289 link->ddc, 2290 165000,//vbios only handles 165Mhz. 2291 false); 2292 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2293 /* DP159, Retimer settings */ 2294 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2295 write_i2c_retimer_setting(pipe_ctx, 2296 false, false, &settings); 2297 else 2298 write_i2c_default_retimer_setting(pipe_ctx, 2299 false, false); 2300 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2301 /* PI3EQX1204, Redriver settings */ 2302 write_i2c_redriver_setting(pipe_ctx, false); 2303 } 2304 } 2305 2306 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2307 !link_is_dp_128b_132b_signal(pipe_ctx)) { 2308 2309 /* In DP1.x SST mode, our encoder will go to TPS1 2310 * when link is on but stream is off. 2311 * Disabling link before stream will avoid exposing TPS1 pattern 2312 * during the disable sequence as it will confuse some receivers 2313 * state machine. 2314 * In DP2 or MST mode, our encoder will stay video active 2315 */ 2316 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2317 dc->hwss.disable_stream(pipe_ctx); 2318 } else { 2319 dc->hwss.disable_stream(pipe_ctx); 2320 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2321 } 2322 2323 if (pipe_ctx->stream->timing.flags.DSC) { 2324 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2325 link_set_dsc_enable(pipe_ctx, false); 2326 } 2327 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2328 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2329 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2330 } 2331 2332 if (vpg && vpg->funcs->vpg_powerdown) 2333 vpg->funcs->vpg_powerdown(vpg); 2334 } 2335 2336 void link_set_dpms_on( 2337 struct dc_state *state, 2338 struct pipe_ctx *pipe_ctx) 2339 { 2340 struct dc *dc = pipe_ctx->stream->ctx->dc; 2341 struct dc_stream_state *stream = pipe_ctx->stream; 2342 struct dc_link *link = stream->sink->link; 2343 enum dc_status status; 2344 struct link_encoder *link_enc; 2345 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2346 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2347 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2348 2349 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2350 2351 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2352 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2353 2354 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2355 2356 if (pipe_ctx->stream->sink) { 2357 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2358 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2359 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2360 pipe_ctx->stream->sink->edid_caps.display_name, 2361 pipe_ctx->stream->signal); 2362 } 2363 } 2364 2365 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2366 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2367 return; 2368 2369 link_enc = link_enc_cfg_get_link_enc(link); 2370 ASSERT(link_enc); 2371 2372 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2373 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 2374 if (link_enc) 2375 link_enc->funcs->setup( 2376 link_enc, 2377 pipe_ctx->stream->signal); 2378 } 2379 2380 pipe_ctx->stream->link->link_state_valid = true; 2381 2382 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2383 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2384 otg_out_dest = OUT_MUX_HPO_DP; 2385 else 2386 otg_out_dest = OUT_MUX_DIO; 2387 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2388 } 2389 2390 link_hwss->setup_stream_attribute(pipe_ctx); 2391 2392 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2393 bool apply_edp_fast_boot_optimization = 2394 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2395 2396 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2397 2398 // Enable VPG before building infoframe 2399 if (vpg && vpg->funcs->vpg_poweron) 2400 vpg->funcs->vpg_poweron(vpg); 2401 2402 resource_build_info_frame(pipe_ctx); 2403 dc->hwss.update_info_frame(pipe_ctx); 2404 2405 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2406 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2407 2408 /* Do not touch link on seamless boot optimization. */ 2409 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2410 pipe_ctx->stream->dpms_off = false; 2411 2412 /* Still enable stream features & audio on seamless boot for DP external displays */ 2413 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2414 enable_stream_features(pipe_ctx); 2415 dc->hwss.enable_audio_stream(pipe_ctx); 2416 } 2417 2418 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2419 update_psp_stream_config(pipe_ctx, false); 2420 #endif 2421 return; 2422 } 2423 2424 /* eDP lit up by bios already, no need to enable again. */ 2425 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2426 apply_edp_fast_boot_optimization && 2427 !pipe_ctx->stream->timing.flags.DSC && 2428 !pipe_ctx->next_odm_pipe) { 2429 pipe_ctx->stream->dpms_off = false; 2430 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2431 update_psp_stream_config(pipe_ctx, false); 2432 #endif 2433 return; 2434 } 2435 2436 if (pipe_ctx->stream->dpms_off) 2437 return; 2438 2439 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2440 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2441 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2442 * will be automatically set at a later time when the video is enabled 2443 * (DP_VID_STREAM_EN = 1). 2444 */ 2445 if (pipe_ctx->stream->timing.flags.DSC) { 2446 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2447 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2448 link_set_dsc_enable(pipe_ctx, true); 2449 2450 } 2451 2452 status = enable_link(state, pipe_ctx); 2453 2454 if (status != DC_OK) { 2455 DC_LOG_WARNING("enabling link %u failed: %d\n", 2456 pipe_ctx->stream->link->link_index, 2457 status); 2458 2459 /* Abort stream enable *unless* the failure was due to 2460 * DP link training - some DP monitors will recover and 2461 * show the stream anyway. But MST displays can't proceed 2462 * without link training. 2463 */ 2464 if (status != DC_FAIL_DP_LINK_TRAINING || 2465 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2466 if (false == stream->link->link_status.link_active) 2467 disable_link(stream->link, &pipe_ctx->link_res, 2468 pipe_ctx->stream->signal); 2469 BREAK_TO_DEBUGGER(); 2470 return; 2471 } 2472 } 2473 2474 /* turn off otg test pattern if enable */ 2475 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2476 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2477 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2478 COLOR_DEPTH_UNDEFINED); 2479 2480 /* This second call is needed to reconfigure the DIG 2481 * as a workaround for the incorrect value being applied 2482 * from transmitter control. 2483 */ 2484 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2485 link_is_dp_128b_132b_signal(pipe_ctx))) 2486 if (link_enc) 2487 link_enc->funcs->setup( 2488 link_enc, 2489 pipe_ctx->stream->signal); 2490 2491 dc->hwss.enable_stream(pipe_ctx); 2492 2493 /* Set DPS PPS SDP (AKA "info frames") */ 2494 if (pipe_ctx->stream->timing.flags.DSC) { 2495 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2496 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2497 dp_set_dsc_on_rx(pipe_ctx, true); 2498 link_set_dsc_pps_packet(pipe_ctx, true, true); 2499 } 2500 } 2501 2502 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2503 allocate_mst_payload(pipe_ctx); 2504 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2505 link_is_dp_128b_132b_signal(pipe_ctx)) 2506 update_sst_payload(pipe_ctx, true); 2507 2508 dc->hwss.unblank_stream(pipe_ctx, 2509 &pipe_ctx->stream->link->cur_link_settings); 2510 2511 if (stream->sink_patches.delay_ignore_msa > 0) 2512 msleep(stream->sink_patches.delay_ignore_msa); 2513 2514 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2515 enable_stream_features(pipe_ctx); 2516 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2517 update_psp_stream_config(pipe_ctx, false); 2518 #endif 2519 2520 dc->hwss.enable_audio_stream(pipe_ctx); 2521 2522 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2523 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2524 dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx); 2525 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2526 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2527 link_set_dsc_enable(pipe_ctx, true); 2528 } 2529 2530 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2531 set_avmute(pipe_ctx, false); 2532 } 2533 } 2534