1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "accessories/link_fpga.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #define DC_LOGGER_INIT(logger) 59 60 #define LINK_INFO(...) \ 61 DC_LOG_HW_HOTPLUG( \ 62 __VA_ARGS__) 63 64 #define RETIMER_REDRIVER_INFO(...) \ 65 DC_LOG_RETIMER_REDRIVER( \ 66 __VA_ARGS__) 67 #include "dc/dcn30/dcn30_vpg.h" 68 69 #define MAX_MTP_SLOT_COUNT 64 70 #define LINK_TRAINING_ATTEMPTS 4 71 #define PEAK_FACTOR_X1000 1006 72 73 void link_blank_all_dp_displays(struct dc *dc) 74 { 75 unsigned int i; 76 uint8_t dpcd_power_state = '\0'; 77 enum dc_status status = DC_ERROR_UNEXPECTED; 78 79 for (i = 0; i < dc->link_count; i++) { 80 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 81 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 82 continue; 83 84 /* DP 2.0 spec requires that we read LTTPR caps first */ 85 dp_retrieve_lttpr_cap(dc->links[i]); 86 /* if any of the displays are lit up turn them off */ 87 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 88 &dpcd_power_state, sizeof(dpcd_power_state)); 89 90 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 91 link_blank_dp_stream(dc->links[i], true); 92 } 93 94 } 95 96 void link_blank_all_edp_displays(struct dc *dc) 97 { 98 unsigned int i; 99 uint8_t dpcd_power_state = '\0'; 100 enum dc_status status = DC_ERROR_UNEXPECTED; 101 102 for (i = 0; i < dc->link_count; i++) { 103 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 104 (!dc->links[i]->edp_sink_present)) 105 continue; 106 107 /* if any of the displays are lit up turn them off */ 108 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 109 &dpcd_power_state, sizeof(dpcd_power_state)); 110 111 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 112 link_blank_dp_stream(dc->links[i], true); 113 } 114 } 115 116 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 117 { 118 unsigned int j; 119 struct dc *dc = link->ctx->dc; 120 enum signal_type signal = link->connector_signal; 121 122 if ((signal == SIGNAL_TYPE_EDP) || 123 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 124 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 125 link->link_enc->funcs->get_dig_frontend && 126 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 127 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 128 129 if (fe != ENGINE_ID_UNKNOWN) 130 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 131 if (fe == dc->res_pool->stream_enc[j]->id) { 132 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 133 dc->res_pool->stream_enc[j]); 134 break; 135 } 136 } 137 } 138 139 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 140 dc_link_dp_receiver_power_ctrl(link, false); 141 } 142 } 143 144 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 145 { 146 struct pipe_ctx *pipes[MAX_PIPES]; 147 struct dc_state *state = link->dc->current_state; 148 uint8_t count; 149 int i; 150 struct dc_stream_update stream_update; 151 bool dpms_off = true; 152 struct link_resource link_res = {0}; 153 154 memset(&stream_update, 0, sizeof(stream_update)); 155 stream_update.dpms_off = &dpms_off; 156 157 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 158 159 for (i = 0; i < count; i++) { 160 stream_update.stream = pipes[i]->stream; 161 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 162 pipes[i]->stream, &stream_update, 163 state); 164 } 165 166 /* link can be also enabled by vbios. In this case it is not recorded 167 * in pipe_ctx. Disable link phy here to make sure it is completely off 168 */ 169 dp_disable_link_phy(link, &link_res, link->connector_signal); 170 } 171 172 void link_resume(struct dc_link *link) 173 { 174 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 175 program_hpd_filter(link); 176 } 177 178 /* This function returns true if the pipe is used to feed video signal directly 179 * to the link. 180 */ 181 static bool is_master_pipe_for_link(const struct dc_link *link, 182 const struct pipe_ctx *pipe) 183 { 184 return (pipe->stream && 185 pipe->stream->link && 186 pipe->stream->link == link && 187 pipe->top_pipe == NULL && 188 pipe->prev_odm_pipe == NULL); 189 } 190 191 /* 192 * This function finds all master pipes feeding to a given link with dpms set to 193 * on in given dc state. 194 */ 195 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 196 struct dc_state *state, 197 uint8_t *count, 198 struct pipe_ctx *pipes[MAX_PIPES]) 199 { 200 int i; 201 struct pipe_ctx *pipe = NULL; 202 203 *count = 0; 204 for (i = 0; i < MAX_PIPES; i++) { 205 pipe = &state->res_ctx.pipe_ctx[i]; 206 207 if (is_master_pipe_for_link(link, pipe) && 208 pipe->stream->dpms_off == false) { 209 pipes[(*count)++] = pipe; 210 } 211 } 212 } 213 214 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 215 enum engine_id eng_id, 216 struct ext_hdmi_settings *settings) 217 { 218 bool result = false; 219 int i = 0; 220 struct integrated_info *integrated_info = 221 pipe_ctx->stream->ctx->dc_bios->integrated_info; 222 223 if (integrated_info == NULL) 224 return false; 225 226 /* 227 * Get retimer settings from sbios for passing SI eye test for DCE11 228 * The setting values are varied based on board revision and port id 229 * Therefore the setting values of each ports is passed by sbios. 230 */ 231 232 // Check if current bios contains ext Hdmi settings 233 if (integrated_info->gpu_cap_info & 0x20) { 234 switch (eng_id) { 235 case ENGINE_ID_DIGA: 236 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 237 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 238 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 memmove(settings->reg_settings, 240 integrated_info->dp0_ext_hdmi_reg_settings, 241 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 242 memmove(settings->reg_settings_6g, 243 integrated_info->dp0_ext_hdmi_6g_reg_settings, 244 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 245 result = true; 246 break; 247 case ENGINE_ID_DIGB: 248 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 249 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 250 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 memmove(settings->reg_settings, 252 integrated_info->dp1_ext_hdmi_reg_settings, 253 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 254 memmove(settings->reg_settings_6g, 255 integrated_info->dp1_ext_hdmi_6g_reg_settings, 256 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 257 result = true; 258 break; 259 case ENGINE_ID_DIGC: 260 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 261 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 262 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 memmove(settings->reg_settings, 264 integrated_info->dp2_ext_hdmi_reg_settings, 265 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 266 memmove(settings->reg_settings_6g, 267 integrated_info->dp2_ext_hdmi_6g_reg_settings, 268 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 269 result = true; 270 break; 271 case ENGINE_ID_DIGD: 272 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 273 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 274 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 memmove(settings->reg_settings, 276 integrated_info->dp3_ext_hdmi_reg_settings, 277 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 278 memmove(settings->reg_settings_6g, 279 integrated_info->dp3_ext_hdmi_6g_reg_settings, 280 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 281 result = true; 282 break; 283 default: 284 break; 285 } 286 287 if (result == true) { 288 // Validate settings from bios integrated info table 289 if (settings->slv_addr == 0) 290 return false; 291 if (settings->reg_num > 9) 292 return false; 293 if (settings->reg_num_6g > 3) 294 return false; 295 296 for (i = 0; i < settings->reg_num; i++) { 297 if (settings->reg_settings[i].i2c_reg_index > 0x20) 298 return false; 299 } 300 301 for (i = 0; i < settings->reg_num_6g; i++) { 302 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 303 return false; 304 } 305 } 306 } 307 308 return result; 309 } 310 311 static bool write_i2c(struct pipe_ctx *pipe_ctx, 312 uint8_t address, uint8_t *buffer, uint32_t length) 313 { 314 struct i2c_command cmd = {0}; 315 struct i2c_payload payload = {0}; 316 317 memset(&payload, 0, sizeof(payload)); 318 memset(&cmd, 0, sizeof(cmd)); 319 320 cmd.number_of_payloads = 1; 321 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 322 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 323 324 payload.address = address; 325 payload.data = buffer; 326 payload.length = length; 327 payload.write = true; 328 cmd.payloads = &payload; 329 330 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 331 pipe_ctx->stream->link, &cmd)) 332 return true; 333 334 return false; 335 } 336 337 static void write_i2c_retimer_setting( 338 struct pipe_ctx *pipe_ctx, 339 bool is_vga_mode, 340 bool is_over_340mhz, 341 struct ext_hdmi_settings *settings) 342 { 343 uint8_t slave_address = (settings->slv_addr >> 1); 344 uint8_t buffer[2]; 345 const uint8_t apply_rx_tx_change = 0x4; 346 uint8_t offset = 0xA; 347 uint8_t value = 0; 348 int i = 0; 349 bool i2c_success = false; 350 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 351 352 memset(&buffer, 0, sizeof(buffer)); 353 354 /* Start Ext-Hdmi programming*/ 355 356 for (i = 0; i < settings->reg_num; i++) { 357 /* Apply 3G settings */ 358 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 359 360 buffer[0] = settings->reg_settings[i].i2c_reg_index; 361 buffer[1] = settings->reg_settings[i].i2c_reg_val; 362 i2c_success = write_i2c(pipe_ctx, slave_address, 363 buffer, sizeof(buffer)); 364 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 365 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 366 slave_address, buffer[0], buffer[1], i2c_success?1:0); 367 368 if (!i2c_success) 369 goto i2c_write_fail; 370 371 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 372 * needs to be set to 1 on every 0xA-0xC write. 373 */ 374 if (settings->reg_settings[i].i2c_reg_index == 0xA || 375 settings->reg_settings[i].i2c_reg_index == 0xB || 376 settings->reg_settings[i].i2c_reg_index == 0xC) { 377 378 /* Query current value from offset 0xA */ 379 if (settings->reg_settings[i].i2c_reg_index == 0xA) 380 value = settings->reg_settings[i].i2c_reg_val; 381 else { 382 i2c_success = 383 link_query_ddc_data( 384 pipe_ctx->stream->link->ddc, 385 slave_address, &offset, 1, &value, 1); 386 if (!i2c_success) 387 goto i2c_write_fail; 388 } 389 390 buffer[0] = offset; 391 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 392 buffer[1] = value | apply_rx_tx_change; 393 i2c_success = write_i2c(pipe_ctx, slave_address, 394 buffer, sizeof(buffer)); 395 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 396 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 397 slave_address, buffer[0], buffer[1], i2c_success?1:0); 398 if (!i2c_success) 399 goto i2c_write_fail; 400 } 401 } 402 } 403 404 /* Apply 3G settings */ 405 if (is_over_340mhz) { 406 for (i = 0; i < settings->reg_num_6g; i++) { 407 /* Apply 3G settings */ 408 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 409 410 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 411 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 412 i2c_success = write_i2c(pipe_ctx, slave_address, 413 buffer, sizeof(buffer)); 414 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 415 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 416 slave_address, buffer[0], buffer[1], i2c_success?1:0); 417 418 if (!i2c_success) 419 goto i2c_write_fail; 420 421 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 422 * needs to be set to 1 on every 0xA-0xC write. 423 */ 424 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 425 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 427 428 /* Query current value from offset 0xA */ 429 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 430 value = settings->reg_settings_6g[i].i2c_reg_val; 431 else { 432 i2c_success = 433 link_query_ddc_data( 434 pipe_ctx->stream->link->ddc, 435 slave_address, &offset, 1, &value, 1); 436 if (!i2c_success) 437 goto i2c_write_fail; 438 } 439 440 buffer[0] = offset; 441 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 442 buffer[1] = value | apply_rx_tx_change; 443 i2c_success = write_i2c(pipe_ctx, slave_address, 444 buffer, sizeof(buffer)); 445 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 446 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 447 slave_address, buffer[0], buffer[1], i2c_success?1:0); 448 if (!i2c_success) 449 goto i2c_write_fail; 450 } 451 } 452 } 453 } 454 455 if (is_vga_mode) { 456 /* Program additional settings if using 640x480 resolution */ 457 458 /* Write offset 0xFF to 0x01 */ 459 buffer[0] = 0xff; 460 buffer[1] = 0x01; 461 i2c_success = write_i2c(pipe_ctx, slave_address, 462 buffer, sizeof(buffer)); 463 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 464 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 465 slave_address, buffer[0], buffer[1], i2c_success?1:0); 466 if (!i2c_success) 467 goto i2c_write_fail; 468 469 /* Write offset 0x00 to 0x23 */ 470 buffer[0] = 0x00; 471 buffer[1] = 0x23; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0xff to 0x00 */ 481 buffer[0] = 0xff; 482 buffer[1] = 0x00; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 } 492 493 return; 494 495 i2c_write_fail: 496 DC_LOG_DEBUG("Set retimer failed"); 497 } 498 499 static void write_i2c_default_retimer_setting( 500 struct pipe_ctx *pipe_ctx, 501 bool is_vga_mode, 502 bool is_over_340mhz) 503 { 504 uint8_t slave_address = (0xBA >> 1); 505 uint8_t buffer[2]; 506 bool i2c_success = false; 507 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 508 509 memset(&buffer, 0, sizeof(buffer)); 510 511 /* Program Slave Address for tuning single integrity */ 512 /* Write offset 0x0A to 0x13 */ 513 buffer[0] = 0x0A; 514 buffer[1] = 0x13; 515 i2c_success = write_i2c(pipe_ctx, slave_address, 516 buffer, sizeof(buffer)); 517 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 518 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 519 slave_address, buffer[0], buffer[1], i2c_success?1:0); 520 if (!i2c_success) 521 goto i2c_write_fail; 522 523 /* Write offset 0x0A to 0x17 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x17; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0B to 0xDA or 0xD8 */ 535 buffer[0] = 0x0B; 536 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0A to 0x17 */ 546 buffer[0] = 0x0A; 547 buffer[1] = 0x17; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0C to 0x1D or 0x91 */ 557 buffer[0] = 0x0C; 558 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0A to 0x17 */ 568 buffer[0] = 0x0A; 569 buffer[1] = 0x17; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 579 if (is_vga_mode) { 580 /* Program additional settings if using 640x480 resolution */ 581 582 /* Write offset 0xFF to 0x01 */ 583 buffer[0] = 0xff; 584 buffer[1] = 0x01; 585 i2c_success = write_i2c(pipe_ctx, slave_address, 586 buffer, sizeof(buffer)); 587 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 588 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 589 slave_address, buffer[0], buffer[1], i2c_success?1:0); 590 if (!i2c_success) 591 goto i2c_write_fail; 592 593 /* Write offset 0x00 to 0x23 */ 594 buffer[0] = 0x00; 595 buffer[1] = 0x23; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0xff to 0x00 */ 605 buffer[0] = 0xff; 606 buffer[1] = 0x00; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 } 615 616 return; 617 618 i2c_write_fail: 619 DC_LOG_DEBUG("Set default retimer failed"); 620 } 621 622 static void write_i2c_redriver_setting( 623 struct pipe_ctx *pipe_ctx, 624 bool is_over_340mhz) 625 { 626 uint8_t slave_address = (0xF0 >> 1); 627 uint8_t buffer[16]; 628 bool i2c_success = false; 629 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 630 631 memset(&buffer, 0, sizeof(buffer)); 632 633 // Program Slave Address for tuning single integrity 634 buffer[3] = 0x4E; 635 buffer[4] = 0x4E; 636 buffer[5] = 0x4E; 637 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 638 639 i2c_success = write_i2c(pipe_ctx, slave_address, 640 buffer, sizeof(buffer)); 641 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 642 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 643 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 644 i2c_success = %d\n", 645 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 646 647 if (!i2c_success) 648 DC_LOG_DEBUG("Set redriver failed"); 649 } 650 #if defined(CONFIG_DRM_AMD_DC_HDCP) 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (link_is_dp_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (link_is_dp_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = link_is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 #endif 717 718 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 719 { 720 struct dc *dc = pipe_ctx->stream->ctx->dc; 721 722 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 723 return; 724 725 dc->hwss.set_avmute(pipe_ctx, enable); 726 } 727 728 static void enable_mst_on_sink(struct dc_link *link, bool enable) 729 { 730 unsigned char mstmCntl; 731 732 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 733 if (enable) 734 mstmCntl |= DP_MST_EN; 735 else 736 mstmCntl &= (~DP_MST_EN); 737 738 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 739 } 740 741 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 742 struct dsc_optc_config *config) 743 { 744 uint32_t precision = 1 << 28; 745 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 746 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 747 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 748 DC_LOGGER_INIT(dsc->ctx->logger); 749 750 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 751 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 752 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 753 */ 754 ll_bytes_per_pix_fraq *= 10000000; 755 ll_bytes_per_pix_fraq /= precision; 756 757 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 758 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 759 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 760 DC_LOG_DSC("\tslice_width %d", config->slice_width); 761 } 762 763 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 764 { 765 struct dc *dc = pipe_ctx->stream->ctx->dc; 766 struct dc_stream_state *stream = pipe_ctx->stream; 767 bool result = false; 768 769 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 770 result = true; 771 else 772 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 773 return result; 774 } 775 776 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 777 * i.e. after dp_enable_dsc_on_rx() had been called 778 */ 779 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 780 { 781 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 782 struct dc *dc = pipe_ctx->stream->ctx->dc; 783 struct dc_stream_state *stream = pipe_ctx->stream; 784 struct pipe_ctx *odm_pipe; 785 int opp_cnt = 1; 786 DC_LOGGER_INIT(dsc->ctx->logger); 787 788 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 789 opp_cnt++; 790 791 if (enable) { 792 struct dsc_config dsc_cfg; 793 struct dsc_optc_config dsc_optc_cfg; 794 enum optc_dsc_mode optc_dsc_mode; 795 796 /* Enable DSC hw block */ 797 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 798 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 799 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 800 dsc_cfg.color_depth = stream->timing.display_color_depth; 801 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 802 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 803 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 804 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 805 806 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 807 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 808 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 809 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 810 811 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 812 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 813 } 814 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 815 dsc_cfg.pic_width *= opp_cnt; 816 817 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 818 819 /* Enable DSC in encoder */ 820 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) 821 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 822 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 823 dsc_optc_config_log(dsc, &dsc_optc_cfg); 824 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 825 optc_dsc_mode, 826 dsc_optc_cfg.bytes_per_pixel, 827 dsc_optc_cfg.slice_width); 828 829 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 830 } 831 832 /* Enable DSC in OPTC */ 833 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 834 dsc_optc_config_log(dsc, &dsc_optc_cfg); 835 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 836 optc_dsc_mode, 837 dsc_optc_cfg.bytes_per_pixel, 838 dsc_optc_cfg.slice_width); 839 } else { 840 /* disable DSC in OPTC */ 841 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 842 pipe_ctx->stream_res.tg, 843 OPTC_DSC_DISABLED, 0, 0); 844 845 /* disable DSC in stream encoder */ 846 if (dc_is_dp_signal(stream->signal)) { 847 if (link_is_dp_128b_132b_signal(pipe_ctx)) 848 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 849 pipe_ctx->stream_res.hpo_dp_stream_enc, 850 false, 851 NULL, 852 true); 853 else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 854 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 855 pipe_ctx->stream_res.stream_enc, 856 OPTC_DSC_DISABLED, 0, 0); 857 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 858 pipe_ctx->stream_res.stream_enc, false, NULL, true); 859 } 860 } 861 862 /* disable DSC block */ 863 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 864 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 865 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 866 } 867 } 868 869 /* 870 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 871 * hence PPS info packet update need to use frame update instead of immediate update. 872 * Added parameter immediate_update for this purpose. 873 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 874 * which is the only place where a "false" would be passed in for param immediate_update. 875 * 876 * immediate_update is only applicable when DSC is enabled. 877 */ 878 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 879 { 880 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 881 struct dc_stream_state *stream = pipe_ctx->stream; 882 DC_LOGGER_INIT(dsc->ctx->logger); 883 884 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 885 return false; 886 887 if (enable) { 888 struct dsc_config dsc_cfg; 889 uint8_t dsc_packed_pps[128]; 890 891 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 892 memset(dsc_packed_pps, 0, 128); 893 894 /* Enable DSC hw block */ 895 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 896 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 897 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 898 dsc_cfg.color_depth = stream->timing.display_color_depth; 899 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 900 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 901 902 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 903 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 904 if (dc_is_dp_signal(stream->signal)) { 905 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 906 if (link_is_dp_128b_132b_signal(pipe_ctx)) 907 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 908 pipe_ctx->stream_res.hpo_dp_stream_enc, 909 true, 910 &dsc_packed_pps[0], 911 immediate_update); 912 else 913 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 914 pipe_ctx->stream_res.stream_enc, 915 true, 916 &dsc_packed_pps[0], 917 immediate_update); 918 } 919 } else { 920 /* disable DSC PPS in stream encoder */ 921 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 922 if (dc_is_dp_signal(stream->signal)) { 923 if (link_is_dp_128b_132b_signal(pipe_ctx)) 924 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 925 pipe_ctx->stream_res.hpo_dp_stream_enc, 926 false, 927 NULL, 928 true); 929 else 930 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 931 pipe_ctx->stream_res.stream_enc, false, NULL, true); 932 } 933 } 934 935 return true; 936 } 937 938 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 939 { 940 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 941 bool result = false; 942 943 if (!pipe_ctx->stream->timing.flags.DSC) 944 goto out; 945 if (!dsc) 946 goto out; 947 948 if (enable) { 949 { 950 link_set_dsc_on_stream(pipe_ctx, true); 951 result = true; 952 } 953 } else { 954 dp_set_dsc_on_rx(pipe_ctx, false); 955 link_set_dsc_on_stream(pipe_ctx, false); 956 result = true; 957 } 958 out: 959 return result; 960 } 961 962 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 963 { 964 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 965 966 if (!pipe_ctx->stream->timing.flags.DSC) 967 return false; 968 if (!dsc) 969 return false; 970 971 link_set_dsc_on_stream(pipe_ctx, true); 972 link_set_dsc_pps_packet(pipe_ctx, true, false); 973 return true; 974 } 975 976 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 977 { 978 struct dc_stream_state *stream = pipe_ctx->stream; 979 980 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 981 struct dc_link *link = stream->link; 982 union down_spread_ctrl old_downspread; 983 union down_spread_ctrl new_downspread; 984 985 memset(&old_downspread, 0, sizeof(old_downspread)); 986 987 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 988 &old_downspread.raw, sizeof(old_downspread)); 989 990 new_downspread.raw = old_downspread.raw; 991 992 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 993 (stream->ignore_msa_timing_param) ? 1 : 0; 994 995 if (new_downspread.raw != old_downspread.raw) { 996 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 997 &new_downspread.raw, sizeof(new_downspread)); 998 } 999 1000 } else { 1001 dm_helpers_mst_enable_stream_features(stream); 1002 } 1003 } 1004 1005 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1006 { 1007 const uint32_t VCP_Y_PRECISION = 1000; 1008 uint64_t vcp_x, vcp_y; 1009 DC_LOGGER_INIT(link->ctx->logger); 1010 1011 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1012 avg_time_slots_per_mtp = dc_fixpt_add( 1013 avg_time_slots_per_mtp, 1014 dc_fixpt_from_fraction( 1015 1, 1016 2*VCP_Y_PRECISION)); 1017 1018 vcp_x = dc_fixpt_floor( 1019 avg_time_slots_per_mtp); 1020 vcp_y = dc_fixpt_floor( 1021 dc_fixpt_mul_int( 1022 dc_fixpt_sub_int( 1023 avg_time_slots_per_mtp, 1024 dc_fixpt_floor( 1025 avg_time_slots_per_mtp)), 1026 VCP_Y_PRECISION)); 1027 1028 1029 if (link->type == dc_connection_mst_branch) 1030 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1031 "X: %llu " 1032 "Y: %llu/%d", 1033 vcp_x, 1034 vcp_y, 1035 VCP_Y_PRECISION); 1036 else 1037 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1038 "X: %llu " 1039 "Y: %llu/%d", 1040 vcp_x, 1041 vcp_y, 1042 VCP_Y_PRECISION); 1043 } 1044 1045 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1046 { 1047 struct fixed31_32 mbytes_per_sec; 1048 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, 1049 &stream->link->cur_link_settings); 1050 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1051 1052 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1053 1054 return dc_fixpt_div_int(mbytes_per_sec, 54); 1055 } 1056 1057 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1058 { 1059 struct fixed31_32 peak_kbps; 1060 uint32_t numerator = 0; 1061 uint32_t denominator = 1; 1062 1063 /* 1064 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1065 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1066 * common multiplier to render an integer PBN for all link rate/lane 1067 * counts combinations 1068 * calculate 1069 * peak_kbps *= (1006/1000) 1070 * peak_kbps *= (64/54) 1071 * peak_kbps *= 8 convert to bytes 1072 */ 1073 1074 numerator = 64 * PEAK_FACTOR_X1000; 1075 denominator = 54 * 8 * 1000 * 1000; 1076 kbps *= numerator; 1077 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1078 1079 return peak_kbps; 1080 } 1081 1082 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1083 { 1084 uint64_t kbps; 1085 1086 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1087 return get_pbn_from_bw_in_kbps(kbps); 1088 } 1089 1090 1091 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1092 static void get_lane_status( 1093 struct dc_link *link, 1094 uint32_t lane_count, 1095 union lane_status *status, 1096 union lane_align_status_updated *status_updated) 1097 { 1098 unsigned int lane; 1099 uint8_t dpcd_buf[3] = {0}; 1100 1101 if (status == NULL || status_updated == NULL) { 1102 return; 1103 } 1104 1105 core_link_read_dpcd( 1106 link, 1107 DP_LANE0_1_STATUS, 1108 dpcd_buf, 1109 sizeof(dpcd_buf)); 1110 1111 for (lane = 0; lane < lane_count; lane++) { 1112 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1113 } 1114 1115 status_updated->raw = dpcd_buf[2]; 1116 } 1117 1118 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1119 { 1120 /* 1121 * wait for ACT handled 1122 */ 1123 int i; 1124 const int act_retries = 30; 1125 enum act_return_status result = ACT_FAILED; 1126 union payload_table_update_status update_status = {0}; 1127 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1128 union lane_align_status_updated lane_status_updated; 1129 DC_LOGGER_INIT(link->ctx->logger); 1130 1131 if (link->aux_access_disabled) 1132 return true; 1133 for (i = 0; i < act_retries; i++) { 1134 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1135 1136 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1137 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1138 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1139 !dp_is_interlane_aligned(lane_status_updated)) { 1140 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1141 "polling for ACT handled."); 1142 result = ACT_LINK_LOST; 1143 break; 1144 } 1145 core_link_read_dpcd( 1146 link, 1147 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1148 &update_status.raw, 1149 1); 1150 1151 if (update_status.bits.ACT_HANDLED == 1) { 1152 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1153 result = ACT_SUCCESS; 1154 break; 1155 } 1156 1157 fsleep(5000); 1158 } 1159 1160 if (result == ACT_FAILED) { 1161 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1162 "continue on. Something is wrong with the branch."); 1163 } 1164 1165 return (result == ACT_SUCCESS); 1166 } 1167 1168 static void update_mst_stream_alloc_table( 1169 struct dc_link *link, 1170 struct stream_encoder *stream_enc, 1171 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1172 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1173 { 1174 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1175 struct link_mst_stream_allocation *dc_alloc; 1176 1177 int i; 1178 int j; 1179 1180 /* if DRM proposed_table has more than one new payload */ 1181 ASSERT(proposed_table->stream_count - 1182 link->mst_stream_alloc_table.stream_count < 2); 1183 1184 /* copy proposed_table to link, add stream encoder */ 1185 for (i = 0; i < proposed_table->stream_count; i++) { 1186 1187 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1188 dc_alloc = 1189 &link->mst_stream_alloc_table.stream_allocations[j]; 1190 1191 if (dc_alloc->vcp_id == 1192 proposed_table->stream_allocations[i].vcp_id) { 1193 1194 work_table[i] = *dc_alloc; 1195 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1196 break; /* exit j loop */ 1197 } 1198 } 1199 1200 /* new vcp_id */ 1201 if (j == link->mst_stream_alloc_table.stream_count) { 1202 work_table[i].vcp_id = 1203 proposed_table->stream_allocations[i].vcp_id; 1204 work_table[i].slot_count = 1205 proposed_table->stream_allocations[i].slot_count; 1206 work_table[i].stream_enc = stream_enc; 1207 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1208 } 1209 } 1210 1211 /* update link->mst_stream_alloc_table with work_table */ 1212 link->mst_stream_alloc_table.stream_count = 1213 proposed_table->stream_count; 1214 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1215 link->mst_stream_alloc_table.stream_allocations[i] = 1216 work_table[i]; 1217 } 1218 1219 static void remove_stream_from_alloc_table( 1220 struct dc_link *link, 1221 struct stream_encoder *dio_stream_enc, 1222 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1223 { 1224 int i = 0; 1225 struct link_mst_stream_allocation_table *table = 1226 &link->mst_stream_alloc_table; 1227 1228 if (hpo_dp_stream_enc) { 1229 for (; i < table->stream_count; i++) 1230 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1231 break; 1232 } else { 1233 for (; i < table->stream_count; i++) 1234 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1235 break; 1236 } 1237 1238 if (i < table->stream_count) { 1239 i++; 1240 for (; i < table->stream_count; i++) 1241 table->stream_allocations[i-1] = table->stream_allocations[i]; 1242 memset(&table->stream_allocations[table->stream_count-1], 0, 1243 sizeof(struct link_mst_stream_allocation)); 1244 table->stream_count--; 1245 } 1246 } 1247 1248 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1249 struct pipe_ctx *pipe_ctx) 1250 { 1251 struct dc_stream_state *stream = pipe_ctx->stream; 1252 struct dc_link *link = stream->link; 1253 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1254 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1255 int i; 1256 bool mst_mode = (link->type == dc_connection_mst_branch); 1257 /* adjust for drm changes*/ 1258 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1259 const struct dc_link_settings empty_link_settings = {0}; 1260 DC_LOGGER_INIT(link->ctx->logger); 1261 1262 if (link_hwss->ext.set_throttled_vcp_size) 1263 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1264 if (link_hwss->ext.set_hblank_min_symbol_width) 1265 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1266 &empty_link_settings, 1267 avg_time_slots_per_mtp); 1268 1269 if (dm_helpers_dp_mst_write_payload_allocation_table( 1270 stream->ctx, 1271 stream, 1272 &proposed_table, 1273 false)) 1274 update_mst_stream_alloc_table( 1275 link, 1276 pipe_ctx->stream_res.stream_enc, 1277 pipe_ctx->stream_res.hpo_dp_stream_enc, 1278 &proposed_table); 1279 else 1280 DC_LOG_WARNING("Failed to update" 1281 "MST allocation table for" 1282 "pipe idx:%d\n", 1283 pipe_ctx->pipe_idx); 1284 1285 DC_LOG_MST("%s" 1286 "stream_count: %d: ", 1287 __func__, 1288 link->mst_stream_alloc_table.stream_count); 1289 1290 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1291 DC_LOG_MST("stream_enc[%d]: %p " 1292 "stream[%d].hpo_dp_stream_enc: %p " 1293 "stream[%d].vcp_id: %d " 1294 "stream[%d].slot_count: %d\n", 1295 i, 1296 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1297 i, 1298 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1299 i, 1300 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1301 i, 1302 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1303 } 1304 1305 if (link_hwss->ext.update_stream_allocation_table == NULL || 1306 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1307 DC_LOG_DEBUG("Unknown encoding format\n"); 1308 return DC_ERROR_UNEXPECTED; 1309 } 1310 1311 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1312 &link->mst_stream_alloc_table); 1313 1314 if (mst_mode) { 1315 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1316 stream->ctx, 1317 stream); 1318 } 1319 1320 dm_helpers_dp_mst_send_payload_allocation( 1321 stream->ctx, 1322 stream, 1323 false); 1324 1325 return DC_OK; 1326 } 1327 1328 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1329 { 1330 struct dc_stream_state *stream = pipe_ctx->stream; 1331 struct dc_link *link = stream->link; 1332 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1333 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1334 int i; 1335 bool mst_mode = (link->type == dc_connection_mst_branch); 1336 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1337 const struct dc_link_settings empty_link_settings = {0}; 1338 DC_LOGGER_INIT(link->ctx->logger); 1339 1340 if (link->dc->debug.temp_mst_deallocation_sequence) 1341 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1342 1343 /* deallocate_mst_payload is called before disable link. When mode or 1344 * disable/enable monitor, new stream is created which is not in link 1345 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1346 * should not done. For new mode set, map_resources will get engine 1347 * for new stream, so stream_enc->id should be validated until here. 1348 */ 1349 1350 /* slot X.Y */ 1351 if (link_hwss->ext.set_throttled_vcp_size) 1352 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1353 if (link_hwss->ext.set_hblank_min_symbol_width) 1354 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1355 &empty_link_settings, 1356 avg_time_slots_per_mtp); 1357 1358 if (mst_mode) { 1359 /* when link is in mst mode, reply on mst manager to remove 1360 * payload 1361 */ 1362 if (dm_helpers_dp_mst_write_payload_allocation_table( 1363 stream->ctx, 1364 stream, 1365 &proposed_table, 1366 false)) 1367 update_mst_stream_alloc_table( 1368 link, 1369 pipe_ctx->stream_res.stream_enc, 1370 pipe_ctx->stream_res.hpo_dp_stream_enc, 1371 &proposed_table); 1372 else 1373 DC_LOG_WARNING("Failed to update" 1374 "MST allocation table for" 1375 "pipe idx:%d\n", 1376 pipe_ctx->pipe_idx); 1377 } else { 1378 /* when link is no longer in mst mode (mst hub unplugged), 1379 * remove payload with default dc logic 1380 */ 1381 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1382 pipe_ctx->stream_res.hpo_dp_stream_enc); 1383 } 1384 1385 DC_LOG_MST("%s" 1386 "stream_count: %d: ", 1387 __func__, 1388 link->mst_stream_alloc_table.stream_count); 1389 1390 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1391 DC_LOG_MST("stream_enc[%d]: %p " 1392 "stream[%d].hpo_dp_stream_enc: %p " 1393 "stream[%d].vcp_id: %d " 1394 "stream[%d].slot_count: %d\n", 1395 i, 1396 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1397 i, 1398 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1399 i, 1400 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1401 i, 1402 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1403 } 1404 1405 /* update mst stream allocation table hardware state */ 1406 if (link_hwss->ext.update_stream_allocation_table == NULL || 1407 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1408 DC_LOG_DEBUG("Unknown encoding format\n"); 1409 return DC_ERROR_UNEXPECTED; 1410 } 1411 1412 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1413 &link->mst_stream_alloc_table); 1414 1415 if (mst_mode) { 1416 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1417 stream->ctx, 1418 stream); 1419 1420 dm_helpers_dp_mst_send_payload_allocation( 1421 stream->ctx, 1422 stream, 1423 false); 1424 } 1425 1426 return DC_OK; 1427 } 1428 1429 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1430 * because stream_encoder is not exposed to dm 1431 */ 1432 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1433 { 1434 struct dc_stream_state *stream = pipe_ctx->stream; 1435 struct dc_link *link = stream->link; 1436 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1437 struct fixed31_32 avg_time_slots_per_mtp; 1438 struct fixed31_32 pbn; 1439 struct fixed31_32 pbn_per_slot; 1440 int i; 1441 enum act_return_status ret; 1442 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1443 DC_LOGGER_INIT(link->ctx->logger); 1444 1445 /* enable_link_dp_mst already check link->enabled_stream_count 1446 * and stream is in link->stream[]. This is called during set mode, 1447 * stream_enc is available. 1448 */ 1449 1450 /* get calculate VC payload for stream: stream_alloc */ 1451 if (dm_helpers_dp_mst_write_payload_allocation_table( 1452 stream->ctx, 1453 stream, 1454 &proposed_table, 1455 true)) 1456 update_mst_stream_alloc_table( 1457 link, 1458 pipe_ctx->stream_res.stream_enc, 1459 pipe_ctx->stream_res.hpo_dp_stream_enc, 1460 &proposed_table); 1461 else 1462 DC_LOG_WARNING("Failed to update" 1463 "MST allocation table for" 1464 "pipe idx:%d\n", 1465 pipe_ctx->pipe_idx); 1466 1467 DC_LOG_MST("%s " 1468 "stream_count: %d: \n ", 1469 __func__, 1470 link->mst_stream_alloc_table.stream_count); 1471 1472 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1473 DC_LOG_MST("stream_enc[%d]: %p " 1474 "stream[%d].hpo_dp_stream_enc: %p " 1475 "stream[%d].vcp_id: %d " 1476 "stream[%d].slot_count: %d\n", 1477 i, 1478 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1479 i, 1480 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1481 i, 1482 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1483 i, 1484 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1485 } 1486 1487 ASSERT(proposed_table.stream_count > 0); 1488 1489 /* program DP source TX for payload */ 1490 if (link_hwss->ext.update_stream_allocation_table == NULL || 1491 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1492 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1493 return DC_ERROR_UNEXPECTED; 1494 } 1495 1496 link_hwss->ext.update_stream_allocation_table(link, 1497 &pipe_ctx->link_res, 1498 &link->mst_stream_alloc_table); 1499 1500 /* send down message */ 1501 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1502 stream->ctx, 1503 stream); 1504 1505 if (ret != ACT_LINK_LOST) { 1506 dm_helpers_dp_mst_send_payload_allocation( 1507 stream->ctx, 1508 stream, 1509 true); 1510 } 1511 1512 /* slot X.Y for only current stream */ 1513 pbn_per_slot = get_pbn_per_slot(stream); 1514 if (pbn_per_slot.value == 0) { 1515 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1516 return DC_UNSUPPORTED_VALUE; 1517 } 1518 pbn = get_pbn_from_timing(pipe_ctx); 1519 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1520 1521 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1522 1523 if (link_hwss->ext.set_throttled_vcp_size) 1524 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1525 if (link_hwss->ext.set_hblank_min_symbol_width) 1526 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1527 &link->cur_link_settings, 1528 avg_time_slots_per_mtp); 1529 1530 return DC_OK; 1531 } 1532 1533 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1534 const struct dc_stream_state *stream, 1535 const struct dc_link *link) 1536 { 1537 struct fixed31_32 link_bw_effective = 1538 dc_fixpt_from_int( 1539 dc_link_bandwidth_kbps(link, &link->cur_link_settings)); 1540 struct fixed31_32 timeslot_bw_effective = 1541 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1542 struct fixed31_32 timing_bw = 1543 dc_fixpt_from_int( 1544 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1545 struct fixed31_32 avg_time_slots_per_mtp = 1546 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1547 1548 return avg_time_slots_per_mtp; 1549 } 1550 1551 1552 static bool write_128b_132b_sst_payload_allocation_table( 1553 const struct dc_stream_state *stream, 1554 struct dc_link *link, 1555 struct link_mst_stream_allocation_table *proposed_table, 1556 bool allocate) 1557 { 1558 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1559 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1560 bool result = false; 1561 uint8_t req_slot_count = 0; 1562 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1563 union payload_table_update_status update_status = { 0 }; 1564 const uint32_t max_retries = 30; 1565 uint32_t retries = 0; 1566 DC_LOGGER_INIT(link->ctx->logger); 1567 1568 if (allocate) { 1569 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1570 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1571 /// Validation should filter out modes that exceed link BW 1572 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1573 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1574 return false; 1575 } else { 1576 /// Leave req_slot_count = 0 if allocate is false. 1577 } 1578 1579 proposed_table->stream_count = 1; /// Always 1 stream for SST 1580 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1581 proposed_table->stream_allocations[0].vcp_id = vc_id; 1582 1583 if (link->aux_access_disabled) 1584 return true; 1585 1586 /// Write DPCD 2C0 = 1 to start updating 1587 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1588 core_link_write_dpcd( 1589 link, 1590 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1591 &update_status.raw, 1592 1); 1593 1594 /// Program the changes in DPCD 1C0 - 1C2 1595 ASSERT(vc_id == 1); 1596 core_link_write_dpcd( 1597 link, 1598 DP_PAYLOAD_ALLOCATE_SET, 1599 &vc_id, 1600 1); 1601 1602 ASSERT(start_time_slot == 0); 1603 core_link_write_dpcd( 1604 link, 1605 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1606 &start_time_slot, 1607 1); 1608 1609 core_link_write_dpcd( 1610 link, 1611 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1612 &req_slot_count, 1613 1); 1614 1615 /// Poll till DPCD 2C0 read 1 1616 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1617 1618 while (retries < max_retries) { 1619 if (core_link_read_dpcd( 1620 link, 1621 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1622 &update_status.raw, 1623 1) == DC_OK) { 1624 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1625 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1626 result = true; 1627 break; 1628 } 1629 } else { 1630 union dpcd_rev dpcdRev; 1631 1632 if (core_link_read_dpcd( 1633 link, 1634 DP_DPCD_REV, 1635 &dpcdRev.raw, 1636 1) != DC_OK) { 1637 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1638 "of sink while polling payload table " 1639 "updated status bit."); 1640 break; 1641 } 1642 } 1643 retries++; 1644 fsleep(5000); 1645 } 1646 1647 if (!result && retries == max_retries) { 1648 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1649 "continue on. Something is wrong with the branch."); 1650 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1651 } 1652 1653 return result; 1654 } 1655 1656 /* 1657 * Payload allocation/deallocation for SST introduced in DP2.0 1658 */ 1659 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1660 bool allocate) 1661 { 1662 struct dc_stream_state *stream = pipe_ctx->stream; 1663 struct dc_link *link = stream->link; 1664 struct link_mst_stream_allocation_table proposed_table = {0}; 1665 struct fixed31_32 avg_time_slots_per_mtp; 1666 const struct dc_link_settings empty_link_settings = {0}; 1667 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1668 DC_LOGGER_INIT(link->ctx->logger); 1669 1670 /* slot X.Y for SST payload deallocate */ 1671 if (!allocate) { 1672 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1673 1674 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1675 1676 if (link_hwss->ext.set_throttled_vcp_size) 1677 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1678 avg_time_slots_per_mtp); 1679 if (link_hwss->ext.set_hblank_min_symbol_width) 1680 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1681 &empty_link_settings, 1682 avg_time_slots_per_mtp); 1683 } 1684 1685 /* calculate VC payload and update branch with new payload allocation table*/ 1686 if (!write_128b_132b_sst_payload_allocation_table( 1687 stream, 1688 link, 1689 &proposed_table, 1690 allocate)) { 1691 DC_LOG_ERROR("SST Update Payload: Failed to update " 1692 "allocation table for " 1693 "pipe idx: %d\n", 1694 pipe_ctx->pipe_idx); 1695 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1696 } 1697 1698 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1699 1700 ASSERT(proposed_table.stream_count == 1); 1701 1702 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1703 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1704 "vcp_id: %d " 1705 "slot_count: %d\n", 1706 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1707 proposed_table.stream_allocations[0].vcp_id, 1708 proposed_table.stream_allocations[0].slot_count); 1709 1710 /* program DP source TX for payload */ 1711 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1712 &proposed_table); 1713 1714 /* poll for ACT handled */ 1715 if (!poll_for_allocation_change_trigger(link)) { 1716 // Failures will result in blackscreen and errors logged 1717 BREAK_TO_DEBUGGER(); 1718 } 1719 1720 /* slot X.Y for SST payload allocate */ 1721 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1722 DP_128b_132b_ENCODING) { 1723 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1724 1725 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1726 1727 if (link_hwss->ext.set_throttled_vcp_size) 1728 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1729 avg_time_slots_per_mtp); 1730 if (link_hwss->ext.set_hblank_min_symbol_width) 1731 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1732 &link->cur_link_settings, 1733 avg_time_slots_per_mtp); 1734 } 1735 1736 /* Always return DC_OK. 1737 * If part of sequence fails, log failure(s) and show blackscreen 1738 */ 1739 return DC_OK; 1740 } 1741 1742 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1743 { 1744 struct dc_stream_state *stream = pipe_ctx->stream; 1745 struct dc_link *link = stream->link; 1746 struct fixed31_32 avg_time_slots_per_mtp; 1747 struct fixed31_32 pbn; 1748 struct fixed31_32 pbn_per_slot; 1749 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1750 uint8_t i; 1751 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1752 DC_LOGGER_INIT(link->ctx->logger); 1753 1754 /* decrease throttled vcp size */ 1755 pbn_per_slot = get_pbn_per_slot(stream); 1756 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1757 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1758 1759 if (link_hwss->ext.set_throttled_vcp_size) 1760 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1761 if (link_hwss->ext.set_hblank_min_symbol_width) 1762 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1763 &link->cur_link_settings, 1764 avg_time_slots_per_mtp); 1765 1766 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1767 dm_helpers_dp_mst_send_payload_allocation( 1768 stream->ctx, 1769 stream, 1770 true); 1771 1772 /* notify immediate branch device table update */ 1773 if (dm_helpers_dp_mst_write_payload_allocation_table( 1774 stream->ctx, 1775 stream, 1776 &proposed_table, 1777 true)) { 1778 /* update mst stream allocation table software state */ 1779 update_mst_stream_alloc_table( 1780 link, 1781 pipe_ctx->stream_res.stream_enc, 1782 pipe_ctx->stream_res.hpo_dp_stream_enc, 1783 &proposed_table); 1784 } else { 1785 DC_LOG_WARNING("Failed to update" 1786 "MST allocation table for" 1787 "pipe idx:%d\n", 1788 pipe_ctx->pipe_idx); 1789 } 1790 1791 DC_LOG_MST("%s " 1792 "stream_count: %d: \n ", 1793 __func__, 1794 link->mst_stream_alloc_table.stream_count); 1795 1796 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1797 DC_LOG_MST("stream_enc[%d]: %p " 1798 "stream[%d].hpo_dp_stream_enc: %p " 1799 "stream[%d].vcp_id: %d " 1800 "stream[%d].slot_count: %d\n", 1801 i, 1802 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1803 i, 1804 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1805 i, 1806 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1807 i, 1808 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1809 } 1810 1811 ASSERT(proposed_table.stream_count > 0); 1812 1813 /* update mst stream allocation table hardware state */ 1814 if (link_hwss->ext.update_stream_allocation_table == NULL || 1815 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1816 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1817 return DC_ERROR_UNEXPECTED; 1818 } 1819 1820 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1821 &link->mst_stream_alloc_table); 1822 1823 /* poll for immediate branch device ACT handled */ 1824 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1825 stream->ctx, 1826 stream); 1827 1828 return DC_OK; 1829 } 1830 1831 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1832 { 1833 struct dc_stream_state *stream = pipe_ctx->stream; 1834 struct dc_link *link = stream->link; 1835 struct fixed31_32 avg_time_slots_per_mtp; 1836 struct fixed31_32 pbn; 1837 struct fixed31_32 pbn_per_slot; 1838 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1839 uint8_t i; 1840 enum act_return_status ret; 1841 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1842 DC_LOGGER_INIT(link->ctx->logger); 1843 1844 /* notify immediate branch device table update */ 1845 if (dm_helpers_dp_mst_write_payload_allocation_table( 1846 stream->ctx, 1847 stream, 1848 &proposed_table, 1849 true)) { 1850 /* update mst stream allocation table software state */ 1851 update_mst_stream_alloc_table( 1852 link, 1853 pipe_ctx->stream_res.stream_enc, 1854 pipe_ctx->stream_res.hpo_dp_stream_enc, 1855 &proposed_table); 1856 } 1857 1858 DC_LOG_MST("%s " 1859 "stream_count: %d: \n ", 1860 __func__, 1861 link->mst_stream_alloc_table.stream_count); 1862 1863 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1864 DC_LOG_MST("stream_enc[%d]: %p " 1865 "stream[%d].hpo_dp_stream_enc: %p " 1866 "stream[%d].vcp_id: %d " 1867 "stream[%d].slot_count: %d\n", 1868 i, 1869 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1870 i, 1871 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1872 i, 1873 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1874 i, 1875 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1876 } 1877 1878 ASSERT(proposed_table.stream_count > 0); 1879 1880 /* update mst stream allocation table hardware state */ 1881 if (link_hwss->ext.update_stream_allocation_table == NULL || 1882 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1883 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1884 return DC_ERROR_UNEXPECTED; 1885 } 1886 1887 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1888 &link->mst_stream_alloc_table); 1889 1890 /* poll for immediate branch device ACT handled */ 1891 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1892 stream->ctx, 1893 stream); 1894 1895 if (ret != ACT_LINK_LOST) { 1896 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1897 dm_helpers_dp_mst_send_payload_allocation( 1898 stream->ctx, 1899 stream, 1900 true); 1901 } 1902 1903 /* increase throttled vcp size */ 1904 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1905 pbn_per_slot = get_pbn_per_slot(stream); 1906 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1907 1908 if (link_hwss->ext.set_throttled_vcp_size) 1909 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1910 if (link_hwss->ext.set_hblank_min_symbol_width) 1911 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1912 &link->cur_link_settings, 1913 avg_time_slots_per_mtp); 1914 1915 return DC_OK; 1916 } 1917 1918 static void disable_link_dp(struct dc_link *link, 1919 const struct link_resource *link_res, 1920 enum signal_type signal) 1921 { 1922 struct dc_link_settings link_settings = link->cur_link_settings; 1923 1924 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1925 link->mst_stream_alloc_table.stream_count > 0) 1926 /* disable MST link only when last vc payload is deallocated */ 1927 return; 1928 1929 dp_disable_link_phy(link, link_res, signal); 1930 1931 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1932 /* set the sink to SST mode after disabling the link */ 1933 enable_mst_on_sink(link, false); 1934 1935 if (link_dp_get_encoding_format(&link_settings) == 1936 DP_8b_10b_ENCODING) { 1937 dp_set_fec_enable(link, false); 1938 dp_set_fec_ready(link, link_res, false); 1939 } 1940 } 1941 1942 static void disable_link(struct dc_link *link, 1943 const struct link_resource *link_res, 1944 enum signal_type signal) 1945 { 1946 if (dc_is_dp_signal(signal)) { 1947 disable_link_dp(link, link_res, signal); 1948 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1949 link->dc->hwss.disable_link_output(link, link_res, signal); 1950 } 1951 1952 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1953 /* MST disable link only when no stream use the link */ 1954 if (link->mst_stream_alloc_table.stream_count <= 0) 1955 link->link_status.link_active = false; 1956 } else { 1957 link->link_status.link_active = false; 1958 } 1959 } 1960 1961 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1962 { 1963 struct dc_stream_state *stream = pipe_ctx->stream; 1964 struct dc_link *link = stream->link; 1965 enum dc_color_depth display_color_depth; 1966 enum engine_id eng_id; 1967 struct ext_hdmi_settings settings = {0}; 1968 bool is_over_340mhz = false; 1969 bool is_vga_mode = (stream->timing.h_addressable == 640) 1970 && (stream->timing.v_addressable == 480); 1971 struct dc *dc = pipe_ctx->stream->ctx->dc; 1972 1973 if (stream->phy_pix_clk == 0) 1974 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1975 if (stream->phy_pix_clk > 340000) 1976 is_over_340mhz = true; 1977 1978 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1979 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1980 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1981 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1982 /* DP159, Retimer settings */ 1983 eng_id = pipe_ctx->stream_res.stream_enc->id; 1984 1985 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1986 write_i2c_retimer_setting(pipe_ctx, 1987 is_vga_mode, is_over_340mhz, &settings); 1988 } else { 1989 write_i2c_default_retimer_setting(pipe_ctx, 1990 is_vga_mode, is_over_340mhz); 1991 } 1992 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1993 /* PI3EQX1204, Redriver settings */ 1994 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1995 } 1996 } 1997 1998 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1999 write_scdc_data( 2000 stream->link->ddc, 2001 stream->phy_pix_clk, 2002 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2003 2004 memset(&stream->link->cur_link_settings, 0, 2005 sizeof(struct dc_link_settings)); 2006 2007 display_color_depth = stream->timing.display_color_depth; 2008 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2009 display_color_depth = COLOR_DEPTH_888; 2010 2011 dc->hwss.enable_tmds_link_output( 2012 link, 2013 &pipe_ctx->link_res, 2014 pipe_ctx->stream->signal, 2015 pipe_ctx->clock_source->id, 2016 display_color_depth, 2017 stream->phy_pix_clk); 2018 2019 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2020 read_scdc_data(link->ddc); 2021 } 2022 2023 static enum dc_status enable_link_dp(struct dc_state *state, 2024 struct pipe_ctx *pipe_ctx) 2025 { 2026 struct dc_stream_state *stream = pipe_ctx->stream; 2027 enum dc_status status; 2028 bool skip_video_pattern; 2029 struct dc_link *link = stream->link; 2030 const struct dc_link_settings *link_settings = 2031 &pipe_ctx->link_config.dp_link_settings; 2032 bool fec_enable; 2033 int i; 2034 bool apply_seamless_boot_optimization = false; 2035 uint32_t bl_oled_enable_delay = 50; // in ms 2036 uint32_t post_oui_delay = 30; // 30ms 2037 /* Reduce link bandwidth between failed link training attempts. */ 2038 bool do_fallback = false; 2039 2040 // check for seamless boot 2041 for (i = 0; i < state->stream_count; i++) { 2042 if (state->streams[i]->apply_seamless_boot_optimization) { 2043 apply_seamless_boot_optimization = true; 2044 break; 2045 } 2046 } 2047 2048 /* 2049 * If the link is DP-over-USB4 do the following: 2050 * - Train with fallback when enabling DPIA link. Conventional links are 2051 * trained with fallback during sink detection. 2052 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2053 * in case stream needs more or less bw from what has been allocated 2054 * earlier at plug time. 2055 */ 2056 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2057 do_fallback = true; 2058 } 2059 2060 /* 2061 * Temporary w/a to get DP2.0 link rates to work with SST. 2062 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2063 */ 2064 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2065 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2066 link->dc->debug.set_mst_en_for_sst) { 2067 enable_mst_on_sink(link, true); 2068 } 2069 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2070 /*in case it is not on*/ 2071 if (!link->dc->config.edp_no_power_sequencing) 2072 link->dc->hwss.edp_power_control(link, true); 2073 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2074 } 2075 2076 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2077 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2078 } else { 2079 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2080 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2081 if (state->clk_mgr && !apply_seamless_boot_optimization) 2082 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2083 state, false); 2084 } 2085 2086 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2087 dpcd_set_source_specific_data(link); 2088 if (link->dpcd_sink_ext_caps.raw != 0) { 2089 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2090 msleep(post_oui_delay); 2091 } 2092 2093 // similarly, mode switch can cause loss of cable ID 2094 dpcd_write_cable_id_to_dprx(link); 2095 2096 skip_video_pattern = true; 2097 2098 if (link_settings->link_rate == LINK_RATE_LOW) 2099 skip_video_pattern = false; 2100 2101 if (perform_link_training_with_retries(link_settings, 2102 skip_video_pattern, 2103 LINK_TRAINING_ATTEMPTS, 2104 pipe_ctx, 2105 pipe_ctx->stream->signal, 2106 do_fallback)) { 2107 status = DC_OK; 2108 } else { 2109 status = DC_FAIL_DP_LINK_TRAINING; 2110 } 2111 2112 if (link->preferred_training_settings.fec_enable) 2113 fec_enable = *link->preferred_training_settings.fec_enable; 2114 else 2115 fec_enable = true; 2116 2117 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2118 dp_set_fec_enable(link, fec_enable); 2119 2120 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2121 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2122 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2123 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2124 set_default_brightness_aux(link); // TODO: use cached if known 2125 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2126 msleep(bl_oled_enable_delay); 2127 link_backlight_enable_aux(link, true); 2128 } 2129 2130 return status; 2131 } 2132 2133 static enum dc_status enable_link_edp( 2134 struct dc_state *state, 2135 struct pipe_ctx *pipe_ctx) 2136 { 2137 return enable_link_dp(state, pipe_ctx); 2138 } 2139 2140 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2141 { 2142 struct dc_stream_state *stream = pipe_ctx->stream; 2143 struct dc_link *link = stream->link; 2144 struct dc *dc = stream->ctx->dc; 2145 2146 if (stream->phy_pix_clk == 0) 2147 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2148 2149 memset(&stream->link->cur_link_settings, 0, 2150 sizeof(struct dc_link_settings)); 2151 dc->hwss.enable_lvds_link_output( 2152 link, 2153 &pipe_ctx->link_res, 2154 pipe_ctx->clock_source->id, 2155 stream->phy_pix_clk); 2156 2157 } 2158 2159 static enum dc_status enable_link_dp_mst( 2160 struct dc_state *state, 2161 struct pipe_ctx *pipe_ctx) 2162 { 2163 struct dc_link *link = pipe_ctx->stream->link; 2164 2165 /* sink signal type after MST branch is MST. Multiple MST sinks 2166 * share one link. Link DP PHY is enable or training only once. 2167 */ 2168 if (link->link_status.link_active) 2169 return DC_OK; 2170 2171 /* clear payload table */ 2172 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2173 2174 /* to make sure the pending down rep can be processed 2175 * before enabling the link 2176 */ 2177 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2178 2179 /* set the sink to MST mode before enabling the link */ 2180 enable_mst_on_sink(link, true); 2181 2182 return enable_link_dp(state, pipe_ctx); 2183 } 2184 2185 static enum dc_status enable_link( 2186 struct dc_state *state, 2187 struct pipe_ctx *pipe_ctx) 2188 { 2189 enum dc_status status = DC_ERROR_UNEXPECTED; 2190 struct dc_stream_state *stream = pipe_ctx->stream; 2191 struct dc_link *link = stream->link; 2192 2193 /* There's some scenarios where driver is unloaded with display 2194 * still enabled. When driver is reloaded, it may cause a display 2195 * to not light up if there is a mismatch between old and new 2196 * link settings. Need to call disable first before enabling at 2197 * new link settings. 2198 */ 2199 if (link->link_status.link_active) { 2200 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2201 } 2202 2203 switch (pipe_ctx->stream->signal) { 2204 case SIGNAL_TYPE_DISPLAY_PORT: 2205 status = enable_link_dp(state, pipe_ctx); 2206 break; 2207 case SIGNAL_TYPE_EDP: 2208 status = enable_link_edp(state, pipe_ctx); 2209 break; 2210 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2211 status = enable_link_dp_mst(state, pipe_ctx); 2212 msleep(200); 2213 break; 2214 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2215 case SIGNAL_TYPE_DVI_DUAL_LINK: 2216 case SIGNAL_TYPE_HDMI_TYPE_A: 2217 enable_link_hdmi(pipe_ctx); 2218 status = DC_OK; 2219 break; 2220 case SIGNAL_TYPE_LVDS: 2221 enable_link_lvds(pipe_ctx); 2222 status = DC_OK; 2223 break; 2224 case SIGNAL_TYPE_VIRTUAL: 2225 status = DC_OK; 2226 break; 2227 default: 2228 break; 2229 } 2230 2231 if (status == DC_OK) { 2232 pipe_ctx->stream->link->link_status.link_active = true; 2233 } 2234 2235 return status; 2236 } 2237 2238 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2239 { 2240 struct dc *dc = pipe_ctx->stream->ctx->dc; 2241 struct dc_stream_state *stream = pipe_ctx->stream; 2242 struct dc_link *link = stream->sink->link; 2243 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2244 2245 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2246 2247 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2248 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2249 2250 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2251 2252 if (pipe_ctx->stream->sink) { 2253 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2254 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2255 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2256 pipe_ctx->stream->sink->edid_caps.display_name, 2257 pipe_ctx->stream->signal); 2258 } 2259 } 2260 2261 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2262 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2263 return; 2264 2265 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2266 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2267 set_avmute(pipe_ctx, true); 2268 } 2269 2270 dc->hwss.disable_audio_stream(pipe_ctx); 2271 2272 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2273 update_psp_stream_config(pipe_ctx, true); 2274 #endif 2275 dc->hwss.blank_stream(pipe_ctx); 2276 2277 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2278 deallocate_mst_payload(pipe_ctx); 2279 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2280 link_is_dp_128b_132b_signal(pipe_ctx)) 2281 update_sst_payload(pipe_ctx, false); 2282 2283 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2284 struct ext_hdmi_settings settings = {0}; 2285 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2286 2287 unsigned short masked_chip_caps = link->chip_caps & 2288 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2289 //Need to inform that sink is going to use legacy HDMI mode. 2290 write_scdc_data( 2291 link->ddc, 2292 165000,//vbios only handles 165Mhz. 2293 false); 2294 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2295 /* DP159, Retimer settings */ 2296 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2297 write_i2c_retimer_setting(pipe_ctx, 2298 false, false, &settings); 2299 else 2300 write_i2c_default_retimer_setting(pipe_ctx, 2301 false, false); 2302 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2303 /* PI3EQX1204, Redriver settings */ 2304 write_i2c_redriver_setting(pipe_ctx, false); 2305 } 2306 } 2307 2308 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2309 !link_is_dp_128b_132b_signal(pipe_ctx)) { 2310 2311 /* In DP1.x SST mode, our encoder will go to TPS1 2312 * when link is on but stream is off. 2313 * Disabling link before stream will avoid exposing TPS1 pattern 2314 * during the disable sequence as it will confuse some receivers 2315 * state machine. 2316 * In DP2 or MST mode, our encoder will stay video active 2317 */ 2318 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2319 dc->hwss.disable_stream(pipe_ctx); 2320 } else { 2321 dc->hwss.disable_stream(pipe_ctx); 2322 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2323 } 2324 2325 if (pipe_ctx->stream->timing.flags.DSC) { 2326 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2327 link_set_dsc_enable(pipe_ctx, false); 2328 } 2329 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2330 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2331 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2332 } 2333 2334 if (vpg && vpg->funcs->vpg_powerdown) 2335 vpg->funcs->vpg_powerdown(vpg); 2336 } 2337 2338 void link_set_dpms_on( 2339 struct dc_state *state, 2340 struct pipe_ctx *pipe_ctx) 2341 { 2342 struct dc *dc = pipe_ctx->stream->ctx->dc; 2343 struct dc_stream_state *stream = pipe_ctx->stream; 2344 struct dc_link *link = stream->sink->link; 2345 enum dc_status status; 2346 struct link_encoder *link_enc; 2347 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2348 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2349 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2350 2351 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2352 2353 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2354 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2355 2356 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2357 2358 if (pipe_ctx->stream->sink) { 2359 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2360 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2361 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2362 pipe_ctx->stream->sink->edid_caps.display_name, 2363 pipe_ctx->stream->signal); 2364 } 2365 } 2366 2367 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2368 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2369 return; 2370 2371 link_enc = link_enc_cfg_get_link_enc(link); 2372 ASSERT(link_enc); 2373 2374 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2375 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 2376 if (link_enc) 2377 link_enc->funcs->setup( 2378 link_enc, 2379 pipe_ctx->stream->signal); 2380 } 2381 2382 pipe_ctx->stream->link->link_state_valid = true; 2383 2384 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2385 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2386 otg_out_dest = OUT_MUX_HPO_DP; 2387 else 2388 otg_out_dest = OUT_MUX_DIO; 2389 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2390 } 2391 2392 link_hwss->setup_stream_attribute(pipe_ctx); 2393 2394 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2395 bool apply_edp_fast_boot_optimization = 2396 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2397 2398 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2399 2400 // Enable VPG before building infoframe 2401 if (vpg && vpg->funcs->vpg_poweron) 2402 vpg->funcs->vpg_poweron(vpg); 2403 2404 resource_build_info_frame(pipe_ctx); 2405 dc->hwss.update_info_frame(pipe_ctx); 2406 2407 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2408 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2409 2410 /* Do not touch link on seamless boot optimization. */ 2411 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2412 pipe_ctx->stream->dpms_off = false; 2413 2414 /* Still enable stream features & audio on seamless boot for DP external displays */ 2415 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2416 enable_stream_features(pipe_ctx); 2417 dc->hwss.enable_audio_stream(pipe_ctx); 2418 } 2419 2420 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2421 update_psp_stream_config(pipe_ctx, false); 2422 #endif 2423 return; 2424 } 2425 2426 /* eDP lit up by bios already, no need to enable again. */ 2427 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2428 apply_edp_fast_boot_optimization && 2429 !pipe_ctx->stream->timing.flags.DSC && 2430 !pipe_ctx->next_odm_pipe) { 2431 pipe_ctx->stream->dpms_off = false; 2432 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2433 update_psp_stream_config(pipe_ctx, false); 2434 #endif 2435 return; 2436 } 2437 2438 if (pipe_ctx->stream->dpms_off) 2439 return; 2440 2441 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2442 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2443 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2444 * will be automatically set at a later time when the video is enabled 2445 * (DP_VID_STREAM_EN = 1). 2446 */ 2447 if (pipe_ctx->stream->timing.flags.DSC) { 2448 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2449 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2450 link_set_dsc_enable(pipe_ctx, true); 2451 2452 } 2453 2454 status = enable_link(state, pipe_ctx); 2455 2456 if (status != DC_OK) { 2457 DC_LOG_WARNING("enabling link %u failed: %d\n", 2458 pipe_ctx->stream->link->link_index, 2459 status); 2460 2461 /* Abort stream enable *unless* the failure was due to 2462 * DP link training - some DP monitors will recover and 2463 * show the stream anyway. But MST displays can't proceed 2464 * without link training. 2465 */ 2466 if (status != DC_FAIL_DP_LINK_TRAINING || 2467 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2468 if (false == stream->link->link_status.link_active) 2469 disable_link(stream->link, &pipe_ctx->link_res, 2470 pipe_ctx->stream->signal); 2471 BREAK_TO_DEBUGGER(); 2472 return; 2473 } 2474 } 2475 2476 /* turn off otg test pattern if enable */ 2477 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2478 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2479 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2480 COLOR_DEPTH_UNDEFINED); 2481 2482 /* This second call is needed to reconfigure the DIG 2483 * as a workaround for the incorrect value being applied 2484 * from transmitter control. 2485 */ 2486 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2487 link_is_dp_128b_132b_signal(pipe_ctx))) 2488 if (link_enc) 2489 link_enc->funcs->setup( 2490 link_enc, 2491 pipe_ctx->stream->signal); 2492 2493 dc->hwss.enable_stream(pipe_ctx); 2494 2495 /* Set DPS PPS SDP (AKA "info frames") */ 2496 if (pipe_ctx->stream->timing.flags.DSC) { 2497 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2498 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2499 dp_set_dsc_on_rx(pipe_ctx, true); 2500 link_set_dsc_pps_packet(pipe_ctx, true, true); 2501 } 2502 } 2503 2504 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2505 allocate_mst_payload(pipe_ctx); 2506 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2507 link_is_dp_128b_132b_signal(pipe_ctx)) 2508 update_sst_payload(pipe_ctx, true); 2509 2510 dc->hwss.unblank_stream(pipe_ctx, 2511 &pipe_ctx->stream->link->cur_link_settings); 2512 2513 if (stream->sink_patches.delay_ignore_msa > 0) 2514 msleep(stream->sink_patches.delay_ignore_msa); 2515 2516 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2517 enable_stream_features(pipe_ctx); 2518 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2519 update_psp_stream_config(pipe_ctx, false); 2520 #endif 2521 2522 dc->hwss.enable_audio_stream(pipe_ctx); 2523 2524 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2525 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2526 dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx); 2527 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2528 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2529 link_set_dsc_enable(pipe_ctx, true); 2530 } 2531 2532 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2533 set_avmute(pipe_ctx, false); 2534 } 2535 } 2536