1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "accessories/link_fpga.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 50 #include "dm_helpers.h" 51 #include "link_enc_cfg.h" 52 #include "resource.h" 53 #include "dsc.h" 54 #include "link_hwss.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #define DC_LOGGER_INIT(logger) 59 60 #define LINK_INFO(...) \ 61 DC_LOG_HW_HOTPLUG( \ 62 __VA_ARGS__) 63 64 #define RETIMER_REDRIVER_INFO(...) \ 65 DC_LOG_RETIMER_REDRIVER( \ 66 __VA_ARGS__) 67 #include "dc/dcn30/dcn30_vpg.h" 68 69 #define MAX_MTP_SLOT_COUNT 64 70 #define LINK_TRAINING_ATTEMPTS 4 71 #define PEAK_FACTOR_X1000 1006 72 73 void link_blank_all_dp_displays(struct dc *dc) 74 { 75 unsigned int i; 76 uint8_t dpcd_power_state = '\0'; 77 enum dc_status status = DC_ERROR_UNEXPECTED; 78 79 for (i = 0; i < dc->link_count; i++) { 80 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 81 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 82 continue; 83 84 /* DP 2.0 spec requires that we read LTTPR caps first */ 85 dp_retrieve_lttpr_cap(dc->links[i]); 86 /* if any of the displays are lit up turn them off */ 87 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 88 &dpcd_power_state, sizeof(dpcd_power_state)); 89 90 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 91 link_blank_dp_stream(dc->links[i], true); 92 } 93 94 } 95 96 void link_blank_all_edp_displays(struct dc *dc) 97 { 98 unsigned int i; 99 uint8_t dpcd_power_state = '\0'; 100 enum dc_status status = DC_ERROR_UNEXPECTED; 101 102 for (i = 0; i < dc->link_count; i++) { 103 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 104 (!dc->links[i]->edp_sink_present)) 105 continue; 106 107 /* if any of the displays are lit up turn them off */ 108 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 109 &dpcd_power_state, sizeof(dpcd_power_state)); 110 111 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 112 link_blank_dp_stream(dc->links[i], true); 113 } 114 } 115 116 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 117 { 118 unsigned int j; 119 struct dc *dc = link->ctx->dc; 120 enum signal_type signal = link->connector_signal; 121 122 if ((signal == SIGNAL_TYPE_EDP) || 123 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 124 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 125 link->link_enc->funcs->get_dig_frontend && 126 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 127 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 128 129 if (fe != ENGINE_ID_UNKNOWN) 130 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 131 if (fe == dc->res_pool->stream_enc[j]->id) { 132 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 133 dc->res_pool->stream_enc[j]); 134 break; 135 } 136 } 137 } 138 139 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 140 dc_link_dp_receiver_power_ctrl(link, false); 141 } 142 } 143 144 void link_resume(struct dc_link *link) 145 { 146 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 147 program_hpd_filter(link); 148 } 149 150 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 151 enum engine_id eng_id, 152 struct ext_hdmi_settings *settings) 153 { 154 bool result = false; 155 int i = 0; 156 struct integrated_info *integrated_info = 157 pipe_ctx->stream->ctx->dc_bios->integrated_info; 158 159 if (integrated_info == NULL) 160 return false; 161 162 /* 163 * Get retimer settings from sbios for passing SI eye test for DCE11 164 * The setting values are varied based on board revision and port id 165 * Therefore the setting values of each ports is passed by sbios. 166 */ 167 168 // Check if current bios contains ext Hdmi settings 169 if (integrated_info->gpu_cap_info & 0x20) { 170 switch (eng_id) { 171 case ENGINE_ID_DIGA: 172 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 173 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 174 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 175 memmove(settings->reg_settings, 176 integrated_info->dp0_ext_hdmi_reg_settings, 177 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 178 memmove(settings->reg_settings_6g, 179 integrated_info->dp0_ext_hdmi_6g_reg_settings, 180 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 181 result = true; 182 break; 183 case ENGINE_ID_DIGB: 184 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 185 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 186 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 187 memmove(settings->reg_settings, 188 integrated_info->dp1_ext_hdmi_reg_settings, 189 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 190 memmove(settings->reg_settings_6g, 191 integrated_info->dp1_ext_hdmi_6g_reg_settings, 192 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 193 result = true; 194 break; 195 case ENGINE_ID_DIGC: 196 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 197 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 198 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 199 memmove(settings->reg_settings, 200 integrated_info->dp2_ext_hdmi_reg_settings, 201 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 202 memmove(settings->reg_settings_6g, 203 integrated_info->dp2_ext_hdmi_6g_reg_settings, 204 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 205 result = true; 206 break; 207 case ENGINE_ID_DIGD: 208 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 209 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 210 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 211 memmove(settings->reg_settings, 212 integrated_info->dp3_ext_hdmi_reg_settings, 213 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 214 memmove(settings->reg_settings_6g, 215 integrated_info->dp3_ext_hdmi_6g_reg_settings, 216 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 217 result = true; 218 break; 219 default: 220 break; 221 } 222 223 if (result == true) { 224 // Validate settings from bios integrated info table 225 if (settings->slv_addr == 0) 226 return false; 227 if (settings->reg_num > 9) 228 return false; 229 if (settings->reg_num_6g > 3) 230 return false; 231 232 for (i = 0; i < settings->reg_num; i++) { 233 if (settings->reg_settings[i].i2c_reg_index > 0x20) 234 return false; 235 } 236 237 for (i = 0; i < settings->reg_num_6g; i++) { 238 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 239 return false; 240 } 241 } 242 } 243 244 return result; 245 } 246 247 static bool write_i2c(struct pipe_ctx *pipe_ctx, 248 uint8_t address, uint8_t *buffer, uint32_t length) 249 { 250 struct i2c_command cmd = {0}; 251 struct i2c_payload payload = {0}; 252 253 memset(&payload, 0, sizeof(payload)); 254 memset(&cmd, 0, sizeof(cmd)); 255 256 cmd.number_of_payloads = 1; 257 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 258 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 259 260 payload.address = address; 261 payload.data = buffer; 262 payload.length = length; 263 payload.write = true; 264 cmd.payloads = &payload; 265 266 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 267 pipe_ctx->stream->link, &cmd)) 268 return true; 269 270 return false; 271 } 272 273 static void write_i2c_retimer_setting( 274 struct pipe_ctx *pipe_ctx, 275 bool is_vga_mode, 276 bool is_over_340mhz, 277 struct ext_hdmi_settings *settings) 278 { 279 uint8_t slave_address = (settings->slv_addr >> 1); 280 uint8_t buffer[2]; 281 const uint8_t apply_rx_tx_change = 0x4; 282 uint8_t offset = 0xA; 283 uint8_t value = 0; 284 int i = 0; 285 bool i2c_success = false; 286 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 287 288 memset(&buffer, 0, sizeof(buffer)); 289 290 /* Start Ext-Hdmi programming*/ 291 292 for (i = 0; i < settings->reg_num; i++) { 293 /* Apply 3G settings */ 294 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 295 296 buffer[0] = settings->reg_settings[i].i2c_reg_index; 297 buffer[1] = settings->reg_settings[i].i2c_reg_val; 298 i2c_success = write_i2c(pipe_ctx, slave_address, 299 buffer, sizeof(buffer)); 300 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 301 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 302 slave_address, buffer[0], buffer[1], i2c_success?1:0); 303 304 if (!i2c_success) 305 goto i2c_write_fail; 306 307 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 308 * needs to be set to 1 on every 0xA-0xC write. 309 */ 310 if (settings->reg_settings[i].i2c_reg_index == 0xA || 311 settings->reg_settings[i].i2c_reg_index == 0xB || 312 settings->reg_settings[i].i2c_reg_index == 0xC) { 313 314 /* Query current value from offset 0xA */ 315 if (settings->reg_settings[i].i2c_reg_index == 0xA) 316 value = settings->reg_settings[i].i2c_reg_val; 317 else { 318 i2c_success = 319 link_query_ddc_data( 320 pipe_ctx->stream->link->ddc, 321 slave_address, &offset, 1, &value, 1); 322 if (!i2c_success) 323 goto i2c_write_fail; 324 } 325 326 buffer[0] = offset; 327 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 328 buffer[1] = value | apply_rx_tx_change; 329 i2c_success = write_i2c(pipe_ctx, slave_address, 330 buffer, sizeof(buffer)); 331 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 332 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 333 slave_address, buffer[0], buffer[1], i2c_success?1:0); 334 if (!i2c_success) 335 goto i2c_write_fail; 336 } 337 } 338 } 339 340 /* Apply 3G settings */ 341 if (is_over_340mhz) { 342 for (i = 0; i < settings->reg_num_6g; i++) { 343 /* Apply 3G settings */ 344 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 345 346 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 347 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 348 i2c_success = write_i2c(pipe_ctx, slave_address, 349 buffer, sizeof(buffer)); 350 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 351 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 352 slave_address, buffer[0], buffer[1], i2c_success?1:0); 353 354 if (!i2c_success) 355 goto i2c_write_fail; 356 357 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 358 * needs to be set to 1 on every 0xA-0xC write. 359 */ 360 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 361 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 362 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 363 364 /* Query current value from offset 0xA */ 365 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 366 value = settings->reg_settings_6g[i].i2c_reg_val; 367 else { 368 i2c_success = 369 link_query_ddc_data( 370 pipe_ctx->stream->link->ddc, 371 slave_address, &offset, 1, &value, 1); 372 if (!i2c_success) 373 goto i2c_write_fail; 374 } 375 376 buffer[0] = offset; 377 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 378 buffer[1] = value | apply_rx_tx_change; 379 i2c_success = write_i2c(pipe_ctx, slave_address, 380 buffer, sizeof(buffer)); 381 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 382 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 383 slave_address, buffer[0], buffer[1], i2c_success?1:0); 384 if (!i2c_success) 385 goto i2c_write_fail; 386 } 387 } 388 } 389 } 390 391 if (is_vga_mode) { 392 /* Program additional settings if using 640x480 resolution */ 393 394 /* Write offset 0xFF to 0x01 */ 395 buffer[0] = 0xff; 396 buffer[1] = 0x01; 397 i2c_success = write_i2c(pipe_ctx, slave_address, 398 buffer, sizeof(buffer)); 399 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 400 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 401 slave_address, buffer[0], buffer[1], i2c_success?1:0); 402 if (!i2c_success) 403 goto i2c_write_fail; 404 405 /* Write offset 0x00 to 0x23 */ 406 buffer[0] = 0x00; 407 buffer[1] = 0x23; 408 i2c_success = write_i2c(pipe_ctx, slave_address, 409 buffer, sizeof(buffer)); 410 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 411 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 412 slave_address, buffer[0], buffer[1], i2c_success?1:0); 413 if (!i2c_success) 414 goto i2c_write_fail; 415 416 /* Write offset 0xff to 0x00 */ 417 buffer[0] = 0xff; 418 buffer[1] = 0x00; 419 i2c_success = write_i2c(pipe_ctx, slave_address, 420 buffer, sizeof(buffer)); 421 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 422 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 423 slave_address, buffer[0], buffer[1], i2c_success?1:0); 424 if (!i2c_success) 425 goto i2c_write_fail; 426 427 } 428 429 return; 430 431 i2c_write_fail: 432 DC_LOG_DEBUG("Set retimer failed"); 433 } 434 435 static void write_i2c_default_retimer_setting( 436 struct pipe_ctx *pipe_ctx, 437 bool is_vga_mode, 438 bool is_over_340mhz) 439 { 440 uint8_t slave_address = (0xBA >> 1); 441 uint8_t buffer[2]; 442 bool i2c_success = false; 443 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 444 445 memset(&buffer, 0, sizeof(buffer)); 446 447 /* Program Slave Address for tuning single integrity */ 448 /* Write offset 0x0A to 0x13 */ 449 buffer[0] = 0x0A; 450 buffer[1] = 0x13; 451 i2c_success = write_i2c(pipe_ctx, slave_address, 452 buffer, sizeof(buffer)); 453 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 454 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 455 slave_address, buffer[0], buffer[1], i2c_success?1:0); 456 if (!i2c_success) 457 goto i2c_write_fail; 458 459 /* Write offset 0x0A to 0x17 */ 460 buffer[0] = 0x0A; 461 buffer[1] = 0x17; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x0B to 0xDA or 0xD8 */ 471 buffer[0] = 0x0B; 472 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0x0A to 0x17 */ 482 buffer[0] = 0x0A; 483 buffer[1] = 0x17; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 487 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 /* Write offset 0x0C to 0x1D or 0x91 */ 493 buffer[0] = 0x0C; 494 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 495 i2c_success = write_i2c(pipe_ctx, slave_address, 496 buffer, sizeof(buffer)); 497 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 498 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 499 slave_address, buffer[0], buffer[1], i2c_success?1:0); 500 if (!i2c_success) 501 goto i2c_write_fail; 502 503 /* Write offset 0x0A to 0x17 */ 504 buffer[0] = 0x0A; 505 buffer[1] = 0x17; 506 i2c_success = write_i2c(pipe_ctx, slave_address, 507 buffer, sizeof(buffer)); 508 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 509 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 510 slave_address, buffer[0], buffer[1], i2c_success?1:0); 511 if (!i2c_success) 512 goto i2c_write_fail; 513 514 515 if (is_vga_mode) { 516 /* Program additional settings if using 640x480 resolution */ 517 518 /* Write offset 0xFF to 0x01 */ 519 buffer[0] = 0xff; 520 buffer[1] = 0x01; 521 i2c_success = write_i2c(pipe_ctx, slave_address, 522 buffer, sizeof(buffer)); 523 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 524 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 525 slave_address, buffer[0], buffer[1], i2c_success?1:0); 526 if (!i2c_success) 527 goto i2c_write_fail; 528 529 /* Write offset 0x00 to 0x23 */ 530 buffer[0] = 0x00; 531 buffer[1] = 0x23; 532 i2c_success = write_i2c(pipe_ctx, slave_address, 533 buffer, sizeof(buffer)); 534 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 535 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 536 slave_address, buffer[0], buffer[1], i2c_success?1:0); 537 if (!i2c_success) 538 goto i2c_write_fail; 539 540 /* Write offset 0xff to 0x00 */ 541 buffer[0] = 0xff; 542 buffer[1] = 0x00; 543 i2c_success = write_i2c(pipe_ctx, slave_address, 544 buffer, sizeof(buffer)); 545 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 546 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 547 slave_address, buffer[0], buffer[1], i2c_success?1:0); 548 if (!i2c_success) 549 goto i2c_write_fail; 550 } 551 552 return; 553 554 i2c_write_fail: 555 DC_LOG_DEBUG("Set default retimer failed"); 556 } 557 558 static void write_i2c_redriver_setting( 559 struct pipe_ctx *pipe_ctx, 560 bool is_over_340mhz) 561 { 562 uint8_t slave_address = (0xF0 >> 1); 563 uint8_t buffer[16]; 564 bool i2c_success = false; 565 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 566 567 memset(&buffer, 0, sizeof(buffer)); 568 569 // Program Slave Address for tuning single integrity 570 buffer[3] = 0x4E; 571 buffer[4] = 0x4E; 572 buffer[5] = 0x4E; 573 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 574 575 i2c_success = write_i2c(pipe_ctx, slave_address, 576 buffer, sizeof(buffer)); 577 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 578 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 579 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 580 i2c_success = %d\n", 581 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 582 583 if (!i2c_success) 584 DC_LOG_DEBUG("Set redriver failed"); 585 } 586 #if defined(CONFIG_DRM_AMD_DC_HDCP) 587 588 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 589 { 590 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 591 struct link_encoder *link_enc = NULL; 592 struct cp_psp_stream_config config = {0}; 593 enum dp_panel_mode panel_mode = 594 dp_get_panel_mode(pipe_ctx->stream->link); 595 596 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 597 return; 598 599 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 600 ASSERT(link_enc); 601 if (link_enc == NULL) 602 return; 603 604 /* otg instance */ 605 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 606 607 /* dig front end */ 608 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 609 610 /* stream encoder index */ 611 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 612 if (link_is_dp_128b_132b_signal(pipe_ctx)) 613 config.stream_enc_idx = 614 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 615 616 /* dig back end */ 617 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 618 619 /* link encoder index */ 620 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 621 if (link_is_dp_128b_132b_signal(pipe_ctx)) 622 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 623 624 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 625 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 626 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 627 else 628 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 629 630 631 /* phy index */ 632 config.phy_idx = resource_transmitter_to_phy_idx( 633 pipe_ctx->stream->link->dc, link_enc->transmitter); 634 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 635 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 636 config.phy_idx = 0; 637 638 /* stream properties */ 639 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 640 config.mst_enabled = (pipe_ctx->stream->signal == 641 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 642 config.dp2_enabled = link_is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0; 643 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 644 1 : 0; 645 config.dpms_off = dpms_off; 646 647 /* dm stream context */ 648 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 649 650 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 651 } 652 #endif 653 654 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 655 { 656 struct dc *dc = pipe_ctx->stream->ctx->dc; 657 658 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 659 return; 660 661 dc->hwss.set_avmute(pipe_ctx, enable); 662 } 663 664 static void enable_mst_on_sink(struct dc_link *link, bool enable) 665 { 666 unsigned char mstmCntl; 667 668 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 669 if (enable) 670 mstmCntl |= DP_MST_EN; 671 else 672 mstmCntl &= (~DP_MST_EN); 673 674 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 675 } 676 677 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 678 struct dsc_optc_config *config) 679 { 680 uint32_t precision = 1 << 28; 681 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 682 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 683 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 684 DC_LOGGER_INIT(dsc->ctx->logger); 685 686 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 687 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 688 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 689 */ 690 ll_bytes_per_pix_fraq *= 10000000; 691 ll_bytes_per_pix_fraq /= precision; 692 693 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 694 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 695 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 696 DC_LOG_DSC("\tslice_width %d", config->slice_width); 697 } 698 699 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 700 { 701 struct dc *dc = pipe_ctx->stream->ctx->dc; 702 struct dc_stream_state *stream = pipe_ctx->stream; 703 bool result = false; 704 705 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 706 result = true; 707 else 708 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 709 return result; 710 } 711 712 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 713 * i.e. after dp_enable_dsc_on_rx() had been called 714 */ 715 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 716 { 717 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 718 struct dc *dc = pipe_ctx->stream->ctx->dc; 719 struct dc_stream_state *stream = pipe_ctx->stream; 720 struct pipe_ctx *odm_pipe; 721 int opp_cnt = 1; 722 DC_LOGGER_INIT(dsc->ctx->logger); 723 724 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 725 opp_cnt++; 726 727 if (enable) { 728 struct dsc_config dsc_cfg; 729 struct dsc_optc_config dsc_optc_cfg; 730 enum optc_dsc_mode optc_dsc_mode; 731 732 /* Enable DSC hw block */ 733 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 734 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 735 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 736 dsc_cfg.color_depth = stream->timing.display_color_depth; 737 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 738 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 739 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 740 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 741 742 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 743 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 744 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 745 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 746 747 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 748 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 749 } 750 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 751 dsc_cfg.pic_width *= opp_cnt; 752 753 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 754 755 /* Enable DSC in encoder */ 756 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) 757 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 758 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 759 dsc_optc_config_log(dsc, &dsc_optc_cfg); 760 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 761 optc_dsc_mode, 762 dsc_optc_cfg.bytes_per_pixel, 763 dsc_optc_cfg.slice_width); 764 765 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 766 } 767 768 /* Enable DSC in OPTC */ 769 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 770 dsc_optc_config_log(dsc, &dsc_optc_cfg); 771 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 772 optc_dsc_mode, 773 dsc_optc_cfg.bytes_per_pixel, 774 dsc_optc_cfg.slice_width); 775 } else { 776 /* disable DSC in OPTC */ 777 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 778 pipe_ctx->stream_res.tg, 779 OPTC_DSC_DISABLED, 0, 0); 780 781 /* disable DSC in stream encoder */ 782 if (dc_is_dp_signal(stream->signal)) { 783 if (link_is_dp_128b_132b_signal(pipe_ctx)) 784 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 785 pipe_ctx->stream_res.hpo_dp_stream_enc, 786 false, 787 NULL, 788 true); 789 else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 790 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 791 pipe_ctx->stream_res.stream_enc, 792 OPTC_DSC_DISABLED, 0, 0); 793 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 794 pipe_ctx->stream_res.stream_enc, false, NULL, true); 795 } 796 } 797 798 /* disable DSC block */ 799 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 800 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 801 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 802 } 803 } 804 805 /* 806 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 807 * hence PPS info packet update need to use frame update instead of immediate update. 808 * Added parameter immediate_update for this purpose. 809 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 810 * which is the only place where a "false" would be passed in for param immediate_update. 811 * 812 * immediate_update is only applicable when DSC is enabled. 813 */ 814 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 815 { 816 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 817 struct dc_stream_state *stream = pipe_ctx->stream; 818 DC_LOGGER_INIT(dsc->ctx->logger); 819 820 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 821 return false; 822 823 if (enable) { 824 struct dsc_config dsc_cfg; 825 uint8_t dsc_packed_pps[128]; 826 827 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 828 memset(dsc_packed_pps, 0, 128); 829 830 /* Enable DSC hw block */ 831 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 832 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 833 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 834 dsc_cfg.color_depth = stream->timing.display_color_depth; 835 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 836 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 837 838 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 839 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 840 if (dc_is_dp_signal(stream->signal)) { 841 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 842 if (link_is_dp_128b_132b_signal(pipe_ctx)) 843 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 844 pipe_ctx->stream_res.hpo_dp_stream_enc, 845 true, 846 &dsc_packed_pps[0], 847 immediate_update); 848 else 849 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 850 pipe_ctx->stream_res.stream_enc, 851 true, 852 &dsc_packed_pps[0], 853 immediate_update); 854 } 855 } else { 856 /* disable DSC PPS in stream encoder */ 857 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 858 if (dc_is_dp_signal(stream->signal)) { 859 if (link_is_dp_128b_132b_signal(pipe_ctx)) 860 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 861 pipe_ctx->stream_res.hpo_dp_stream_enc, 862 false, 863 NULL, 864 true); 865 else 866 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 867 pipe_ctx->stream_res.stream_enc, false, NULL, true); 868 } 869 } 870 871 return true; 872 } 873 874 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 875 { 876 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 877 bool result = false; 878 879 if (!pipe_ctx->stream->timing.flags.DSC) 880 goto out; 881 if (!dsc) 882 goto out; 883 884 if (enable) { 885 { 886 link_set_dsc_on_stream(pipe_ctx, true); 887 result = true; 888 } 889 } else { 890 dp_set_dsc_on_rx(pipe_ctx, false); 891 link_set_dsc_on_stream(pipe_ctx, false); 892 result = true; 893 } 894 out: 895 return result; 896 } 897 898 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) 899 { 900 return link_update_dsc_config(pipe_ctx); 901 } 902 903 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 904 { 905 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 906 907 if (!pipe_ctx->stream->timing.flags.DSC) 908 return false; 909 if (!dsc) 910 return false; 911 912 link_set_dsc_on_stream(pipe_ctx, true); 913 link_set_dsc_pps_packet(pipe_ctx, true, false); 914 return true; 915 } 916 917 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 918 { 919 struct dc_stream_state *stream = pipe_ctx->stream; 920 921 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 922 struct dc_link *link = stream->link; 923 union down_spread_ctrl old_downspread; 924 union down_spread_ctrl new_downspread; 925 926 memset(&old_downspread, 0, sizeof(old_downspread)); 927 928 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 929 &old_downspread.raw, sizeof(old_downspread)); 930 931 new_downspread.raw = old_downspread.raw; 932 933 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 934 (stream->ignore_msa_timing_param) ? 1 : 0; 935 936 if (new_downspread.raw != old_downspread.raw) { 937 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 938 &new_downspread.raw, sizeof(new_downspread)); 939 } 940 941 } else { 942 dm_helpers_mst_enable_stream_features(stream); 943 } 944 } 945 946 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 947 { 948 const uint32_t VCP_Y_PRECISION = 1000; 949 uint64_t vcp_x, vcp_y; 950 DC_LOGGER_INIT(link->ctx->logger); 951 952 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 953 avg_time_slots_per_mtp = dc_fixpt_add( 954 avg_time_slots_per_mtp, 955 dc_fixpt_from_fraction( 956 1, 957 2*VCP_Y_PRECISION)); 958 959 vcp_x = dc_fixpt_floor( 960 avg_time_slots_per_mtp); 961 vcp_y = dc_fixpt_floor( 962 dc_fixpt_mul_int( 963 dc_fixpt_sub_int( 964 avg_time_slots_per_mtp, 965 dc_fixpt_floor( 966 avg_time_slots_per_mtp)), 967 VCP_Y_PRECISION)); 968 969 970 if (link->type == dc_connection_mst_branch) 971 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 972 "X: %llu " 973 "Y: %llu/%d", 974 vcp_x, 975 vcp_y, 976 VCP_Y_PRECISION); 977 else 978 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 979 "X: %llu " 980 "Y: %llu/%d", 981 vcp_x, 982 vcp_y, 983 VCP_Y_PRECISION); 984 } 985 986 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 987 { 988 struct fixed31_32 mbytes_per_sec; 989 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, 990 &stream->link->cur_link_settings); 991 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 992 993 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 994 995 return dc_fixpt_div_int(mbytes_per_sec, 54); 996 } 997 998 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 999 { 1000 struct fixed31_32 peak_kbps; 1001 uint32_t numerator = 0; 1002 uint32_t denominator = 1; 1003 1004 /* 1005 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1006 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1007 * common multiplier to render an integer PBN for all link rate/lane 1008 * counts combinations 1009 * calculate 1010 * peak_kbps *= (1006/1000) 1011 * peak_kbps *= (64/54) 1012 * peak_kbps *= 8 convert to bytes 1013 */ 1014 1015 numerator = 64 * PEAK_FACTOR_X1000; 1016 denominator = 54 * 8 * 1000 * 1000; 1017 kbps *= numerator; 1018 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1019 1020 return peak_kbps; 1021 } 1022 1023 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1024 { 1025 uint64_t kbps; 1026 1027 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1028 return get_pbn_from_bw_in_kbps(kbps); 1029 } 1030 1031 1032 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1033 static void get_lane_status( 1034 struct dc_link *link, 1035 uint32_t lane_count, 1036 union lane_status *status, 1037 union lane_align_status_updated *status_updated) 1038 { 1039 unsigned int lane; 1040 uint8_t dpcd_buf[3] = {0}; 1041 1042 if (status == NULL || status_updated == NULL) { 1043 return; 1044 } 1045 1046 core_link_read_dpcd( 1047 link, 1048 DP_LANE0_1_STATUS, 1049 dpcd_buf, 1050 sizeof(dpcd_buf)); 1051 1052 for (lane = 0; lane < lane_count; lane++) { 1053 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1054 } 1055 1056 status_updated->raw = dpcd_buf[2]; 1057 } 1058 1059 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1060 { 1061 /* 1062 * wait for ACT handled 1063 */ 1064 int i; 1065 const int act_retries = 30; 1066 enum act_return_status result = ACT_FAILED; 1067 union payload_table_update_status update_status = {0}; 1068 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1069 union lane_align_status_updated lane_status_updated; 1070 DC_LOGGER_INIT(link->ctx->logger); 1071 1072 if (link->aux_access_disabled) 1073 return true; 1074 for (i = 0; i < act_retries; i++) { 1075 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1076 1077 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1078 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1079 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1080 !dp_is_interlane_aligned(lane_status_updated)) { 1081 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1082 "polling for ACT handled."); 1083 result = ACT_LINK_LOST; 1084 break; 1085 } 1086 core_link_read_dpcd( 1087 link, 1088 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1089 &update_status.raw, 1090 1); 1091 1092 if (update_status.bits.ACT_HANDLED == 1) { 1093 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1094 result = ACT_SUCCESS; 1095 break; 1096 } 1097 1098 msleep(5); 1099 } 1100 1101 if (result == ACT_FAILED) { 1102 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1103 "continue on. Something is wrong with the branch."); 1104 } 1105 1106 return (result == ACT_SUCCESS); 1107 } 1108 1109 static void update_mst_stream_alloc_table( 1110 struct dc_link *link, 1111 struct stream_encoder *stream_enc, 1112 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1113 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1114 { 1115 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1116 struct link_mst_stream_allocation *dc_alloc; 1117 1118 int i; 1119 int j; 1120 1121 /* if DRM proposed_table has more than one new payload */ 1122 ASSERT(proposed_table->stream_count - 1123 link->mst_stream_alloc_table.stream_count < 2); 1124 1125 /* copy proposed_table to link, add stream encoder */ 1126 for (i = 0; i < proposed_table->stream_count; i++) { 1127 1128 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1129 dc_alloc = 1130 &link->mst_stream_alloc_table.stream_allocations[j]; 1131 1132 if (dc_alloc->vcp_id == 1133 proposed_table->stream_allocations[i].vcp_id) { 1134 1135 work_table[i] = *dc_alloc; 1136 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1137 break; /* exit j loop */ 1138 } 1139 } 1140 1141 /* new vcp_id */ 1142 if (j == link->mst_stream_alloc_table.stream_count) { 1143 work_table[i].vcp_id = 1144 proposed_table->stream_allocations[i].vcp_id; 1145 work_table[i].slot_count = 1146 proposed_table->stream_allocations[i].slot_count; 1147 work_table[i].stream_enc = stream_enc; 1148 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1149 } 1150 } 1151 1152 /* update link->mst_stream_alloc_table with work_table */ 1153 link->mst_stream_alloc_table.stream_count = 1154 proposed_table->stream_count; 1155 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1156 link->mst_stream_alloc_table.stream_allocations[i] = 1157 work_table[i]; 1158 } 1159 1160 static void remove_stream_from_alloc_table( 1161 struct dc_link *link, 1162 struct stream_encoder *dio_stream_enc, 1163 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1164 { 1165 int i = 0; 1166 struct link_mst_stream_allocation_table *table = 1167 &link->mst_stream_alloc_table; 1168 1169 if (hpo_dp_stream_enc) { 1170 for (; i < table->stream_count; i++) 1171 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1172 break; 1173 } else { 1174 for (; i < table->stream_count; i++) 1175 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1176 break; 1177 } 1178 1179 if (i < table->stream_count) { 1180 i++; 1181 for (; i < table->stream_count; i++) 1182 table->stream_allocations[i-1] = table->stream_allocations[i]; 1183 memset(&table->stream_allocations[table->stream_count-1], 0, 1184 sizeof(struct link_mst_stream_allocation)); 1185 table->stream_count--; 1186 } 1187 } 1188 1189 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1190 { 1191 struct dc_stream_state *stream = pipe_ctx->stream; 1192 struct dc_link *link = stream->link; 1193 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1194 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1195 int i; 1196 bool mst_mode = (link->type == dc_connection_mst_branch); 1197 /* adjust for drm changes*/ 1198 bool update_drm_mst_state = true; 1199 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1200 const struct dc_link_settings empty_link_settings = {0}; 1201 DC_LOGGER_INIT(link->ctx->logger); 1202 1203 1204 /* deallocate_mst_payload is called before disable link. When mode or 1205 * disable/enable monitor, new stream is created which is not in link 1206 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1207 * should not done. For new mode set, map_resources will get engine 1208 * for new stream, so stream_enc->id should be validated until here. 1209 */ 1210 1211 /* slot X.Y */ 1212 if (link_hwss->ext.set_throttled_vcp_size) 1213 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1214 if (link_hwss->ext.set_hblank_min_symbol_width) 1215 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1216 &empty_link_settings, 1217 avg_time_slots_per_mtp); 1218 1219 if (mst_mode || update_drm_mst_state) { 1220 /* when link is in mst mode, reply on mst manager to remove 1221 * payload 1222 */ 1223 if (dm_helpers_dp_mst_write_payload_allocation_table( 1224 stream->ctx, 1225 stream, 1226 &proposed_table, 1227 false)) 1228 update_mst_stream_alloc_table( 1229 link, 1230 pipe_ctx->stream_res.stream_enc, 1231 pipe_ctx->stream_res.hpo_dp_stream_enc, 1232 &proposed_table); 1233 else 1234 DC_LOG_WARNING("Failed to update" 1235 "MST allocation table for" 1236 "pipe idx:%d\n", 1237 pipe_ctx->pipe_idx); 1238 } else { 1239 /* when link is no longer in mst mode (mst hub unplugged), 1240 * remove payload with default dc logic 1241 */ 1242 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1243 pipe_ctx->stream_res.hpo_dp_stream_enc); 1244 } 1245 1246 DC_LOG_MST("%s" 1247 "stream_count: %d: ", 1248 __func__, 1249 link->mst_stream_alloc_table.stream_count); 1250 1251 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1252 DC_LOG_MST("stream_enc[%d]: %p " 1253 "stream[%d].hpo_dp_stream_enc: %p " 1254 "stream[%d].vcp_id: %d " 1255 "stream[%d].slot_count: %d\n", 1256 i, 1257 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1258 i, 1259 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1260 i, 1261 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1262 i, 1263 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1264 } 1265 1266 /* update mst stream allocation table hardware state */ 1267 if (link_hwss->ext.update_stream_allocation_table == NULL || 1268 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1269 DC_LOG_DEBUG("Unknown encoding format\n"); 1270 return DC_ERROR_UNEXPECTED; 1271 } 1272 1273 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1274 &link->mst_stream_alloc_table); 1275 1276 if (mst_mode) { 1277 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1278 stream->ctx, 1279 stream); 1280 1281 if (!update_drm_mst_state) 1282 dm_helpers_dp_mst_send_payload_allocation( 1283 stream->ctx, 1284 stream, 1285 false); 1286 } 1287 1288 if (update_drm_mst_state) 1289 dm_helpers_dp_mst_send_payload_allocation( 1290 stream->ctx, 1291 stream, 1292 false); 1293 1294 return DC_OK; 1295 } 1296 1297 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1298 * because stream_encoder is not exposed to dm 1299 */ 1300 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1301 { 1302 struct dc_stream_state *stream = pipe_ctx->stream; 1303 struct dc_link *link = stream->link; 1304 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1305 struct fixed31_32 avg_time_slots_per_mtp; 1306 struct fixed31_32 pbn; 1307 struct fixed31_32 pbn_per_slot; 1308 int i; 1309 enum act_return_status ret; 1310 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1311 DC_LOGGER_INIT(link->ctx->logger); 1312 1313 /* enable_link_dp_mst already check link->enabled_stream_count 1314 * and stream is in link->stream[]. This is called during set mode, 1315 * stream_enc is available. 1316 */ 1317 1318 /* get calculate VC payload for stream: stream_alloc */ 1319 if (dm_helpers_dp_mst_write_payload_allocation_table( 1320 stream->ctx, 1321 stream, 1322 &proposed_table, 1323 true)) 1324 update_mst_stream_alloc_table( 1325 link, 1326 pipe_ctx->stream_res.stream_enc, 1327 pipe_ctx->stream_res.hpo_dp_stream_enc, 1328 &proposed_table); 1329 else 1330 DC_LOG_WARNING("Failed to update" 1331 "MST allocation table for" 1332 "pipe idx:%d\n", 1333 pipe_ctx->pipe_idx); 1334 1335 DC_LOG_MST("%s " 1336 "stream_count: %d: \n ", 1337 __func__, 1338 link->mst_stream_alloc_table.stream_count); 1339 1340 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1341 DC_LOG_MST("stream_enc[%d]: %p " 1342 "stream[%d].hpo_dp_stream_enc: %p " 1343 "stream[%d].vcp_id: %d " 1344 "stream[%d].slot_count: %d\n", 1345 i, 1346 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1347 i, 1348 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1349 i, 1350 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1351 i, 1352 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1353 } 1354 1355 ASSERT(proposed_table.stream_count > 0); 1356 1357 /* program DP source TX for payload */ 1358 if (link_hwss->ext.update_stream_allocation_table == NULL || 1359 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1360 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1361 return DC_ERROR_UNEXPECTED; 1362 } 1363 1364 link_hwss->ext.update_stream_allocation_table(link, 1365 &pipe_ctx->link_res, 1366 &link->mst_stream_alloc_table); 1367 1368 /* send down message */ 1369 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1370 stream->ctx, 1371 stream); 1372 1373 if (ret != ACT_LINK_LOST) { 1374 dm_helpers_dp_mst_send_payload_allocation( 1375 stream->ctx, 1376 stream, 1377 true); 1378 } 1379 1380 /* slot X.Y for only current stream */ 1381 pbn_per_slot = get_pbn_per_slot(stream); 1382 if (pbn_per_slot.value == 0) { 1383 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1384 return DC_UNSUPPORTED_VALUE; 1385 } 1386 pbn = get_pbn_from_timing(pipe_ctx); 1387 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1388 1389 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1390 1391 if (link_hwss->ext.set_throttled_vcp_size) 1392 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1393 if (link_hwss->ext.set_hblank_min_symbol_width) 1394 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1395 &link->cur_link_settings, 1396 avg_time_slots_per_mtp); 1397 1398 return DC_OK; 1399 } 1400 1401 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1402 const struct dc_stream_state *stream, 1403 const struct dc_link *link) 1404 { 1405 struct fixed31_32 link_bw_effective = 1406 dc_fixpt_from_int( 1407 dc_link_bandwidth_kbps(link, &link->cur_link_settings)); 1408 struct fixed31_32 timeslot_bw_effective = 1409 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1410 struct fixed31_32 timing_bw = 1411 dc_fixpt_from_int( 1412 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1413 struct fixed31_32 avg_time_slots_per_mtp = 1414 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1415 1416 return avg_time_slots_per_mtp; 1417 } 1418 1419 1420 static bool write_128b_132b_sst_payload_allocation_table( 1421 const struct dc_stream_state *stream, 1422 struct dc_link *link, 1423 struct link_mst_stream_allocation_table *proposed_table, 1424 bool allocate) 1425 { 1426 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1427 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1428 bool result = false; 1429 uint8_t req_slot_count = 0; 1430 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1431 union payload_table_update_status update_status = { 0 }; 1432 const uint32_t max_retries = 30; 1433 uint32_t retries = 0; 1434 DC_LOGGER_INIT(link->ctx->logger); 1435 1436 if (allocate) { 1437 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1438 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1439 /// Validation should filter out modes that exceed link BW 1440 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1441 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1442 return false; 1443 } else { 1444 /// Leave req_slot_count = 0 if allocate is false. 1445 } 1446 1447 proposed_table->stream_count = 1; /// Always 1 stream for SST 1448 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1449 proposed_table->stream_allocations[0].vcp_id = vc_id; 1450 1451 if (link->aux_access_disabled) 1452 return true; 1453 1454 /// Write DPCD 2C0 = 1 to start updating 1455 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1456 core_link_write_dpcd( 1457 link, 1458 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1459 &update_status.raw, 1460 1); 1461 1462 /// Program the changes in DPCD 1C0 - 1C2 1463 ASSERT(vc_id == 1); 1464 core_link_write_dpcd( 1465 link, 1466 DP_PAYLOAD_ALLOCATE_SET, 1467 &vc_id, 1468 1); 1469 1470 ASSERT(start_time_slot == 0); 1471 core_link_write_dpcd( 1472 link, 1473 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1474 &start_time_slot, 1475 1); 1476 1477 core_link_write_dpcd( 1478 link, 1479 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1480 &req_slot_count, 1481 1); 1482 1483 /// Poll till DPCD 2C0 read 1 1484 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1485 1486 while (retries < max_retries) { 1487 if (core_link_read_dpcd( 1488 link, 1489 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1490 &update_status.raw, 1491 1) == DC_OK) { 1492 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1493 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1494 result = true; 1495 break; 1496 } 1497 } else { 1498 union dpcd_rev dpcdRev; 1499 1500 if (core_link_read_dpcd( 1501 link, 1502 DP_DPCD_REV, 1503 &dpcdRev.raw, 1504 1) != DC_OK) { 1505 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1506 "of sink while polling payload table " 1507 "updated status bit."); 1508 break; 1509 } 1510 } 1511 retries++; 1512 msleep(5); 1513 } 1514 1515 if (!result && retries == max_retries) { 1516 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1517 "continue on. Something is wrong with the branch."); 1518 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1519 } 1520 1521 return result; 1522 } 1523 1524 /* 1525 * Payload allocation/deallocation for SST introduced in DP2.0 1526 */ 1527 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1528 bool allocate) 1529 { 1530 struct dc_stream_state *stream = pipe_ctx->stream; 1531 struct dc_link *link = stream->link; 1532 struct link_mst_stream_allocation_table proposed_table = {0}; 1533 struct fixed31_32 avg_time_slots_per_mtp; 1534 const struct dc_link_settings empty_link_settings = {0}; 1535 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1536 DC_LOGGER_INIT(link->ctx->logger); 1537 1538 /* slot X.Y for SST payload deallocate */ 1539 if (!allocate) { 1540 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1541 1542 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1543 1544 if (link_hwss->ext.set_throttled_vcp_size) 1545 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1546 avg_time_slots_per_mtp); 1547 if (link_hwss->ext.set_hblank_min_symbol_width) 1548 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1549 &empty_link_settings, 1550 avg_time_slots_per_mtp); 1551 } 1552 1553 /* calculate VC payload and update branch with new payload allocation table*/ 1554 if (!write_128b_132b_sst_payload_allocation_table( 1555 stream, 1556 link, 1557 &proposed_table, 1558 allocate)) { 1559 DC_LOG_ERROR("SST Update Payload: Failed to update " 1560 "allocation table for " 1561 "pipe idx: %d\n", 1562 pipe_ctx->pipe_idx); 1563 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1564 } 1565 1566 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1567 1568 ASSERT(proposed_table.stream_count == 1); 1569 1570 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1571 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1572 "vcp_id: %d " 1573 "slot_count: %d\n", 1574 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1575 proposed_table.stream_allocations[0].vcp_id, 1576 proposed_table.stream_allocations[0].slot_count); 1577 1578 /* program DP source TX for payload */ 1579 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1580 &proposed_table); 1581 1582 /* poll for ACT handled */ 1583 if (!poll_for_allocation_change_trigger(link)) { 1584 // Failures will result in blackscreen and errors logged 1585 BREAK_TO_DEBUGGER(); 1586 } 1587 1588 /* slot X.Y for SST payload allocate */ 1589 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1590 DP_128b_132b_ENCODING) { 1591 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1592 1593 dc_log_vcp_x_y(link, avg_time_slots_per_mtp); 1594 1595 if (link_hwss->ext.set_throttled_vcp_size) 1596 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1597 avg_time_slots_per_mtp); 1598 if (link_hwss->ext.set_hblank_min_symbol_width) 1599 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1600 &link->cur_link_settings, 1601 avg_time_slots_per_mtp); 1602 } 1603 1604 /* Always return DC_OK. 1605 * If part of sequence fails, log failure(s) and show blackscreen 1606 */ 1607 return DC_OK; 1608 } 1609 1610 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1611 { 1612 struct dc_stream_state *stream = pipe_ctx->stream; 1613 struct dc_link *link = stream->link; 1614 struct fixed31_32 avg_time_slots_per_mtp; 1615 struct fixed31_32 pbn; 1616 struct fixed31_32 pbn_per_slot; 1617 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1618 uint8_t i; 1619 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1620 DC_LOGGER_INIT(link->ctx->logger); 1621 1622 /* decrease throttled vcp size */ 1623 pbn_per_slot = get_pbn_per_slot(stream); 1624 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1625 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1626 1627 if (link_hwss->ext.set_throttled_vcp_size) 1628 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1629 if (link_hwss->ext.set_hblank_min_symbol_width) 1630 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1631 &link->cur_link_settings, 1632 avg_time_slots_per_mtp); 1633 1634 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1635 dm_helpers_dp_mst_send_payload_allocation( 1636 stream->ctx, 1637 stream, 1638 true); 1639 1640 /* notify immediate branch device table update */ 1641 if (dm_helpers_dp_mst_write_payload_allocation_table( 1642 stream->ctx, 1643 stream, 1644 &proposed_table, 1645 true)) { 1646 /* update mst stream allocation table software state */ 1647 update_mst_stream_alloc_table( 1648 link, 1649 pipe_ctx->stream_res.stream_enc, 1650 pipe_ctx->stream_res.hpo_dp_stream_enc, 1651 &proposed_table); 1652 } else { 1653 DC_LOG_WARNING("Failed to update" 1654 "MST allocation table for" 1655 "pipe idx:%d\n", 1656 pipe_ctx->pipe_idx); 1657 } 1658 1659 DC_LOG_MST("%s " 1660 "stream_count: %d: \n ", 1661 __func__, 1662 link->mst_stream_alloc_table.stream_count); 1663 1664 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1665 DC_LOG_MST("stream_enc[%d]: %p " 1666 "stream[%d].hpo_dp_stream_enc: %p " 1667 "stream[%d].vcp_id: %d " 1668 "stream[%d].slot_count: %d\n", 1669 i, 1670 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1671 i, 1672 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1673 i, 1674 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1675 i, 1676 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1677 } 1678 1679 ASSERT(proposed_table.stream_count > 0); 1680 1681 /* update mst stream allocation table hardware state */ 1682 if (link_hwss->ext.update_stream_allocation_table == NULL || 1683 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1684 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1685 return DC_ERROR_UNEXPECTED; 1686 } 1687 1688 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1689 &link->mst_stream_alloc_table); 1690 1691 /* poll for immediate branch device ACT handled */ 1692 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1693 stream->ctx, 1694 stream); 1695 1696 return DC_OK; 1697 } 1698 1699 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1700 { 1701 struct dc_stream_state *stream = pipe_ctx->stream; 1702 struct dc_link *link = stream->link; 1703 struct fixed31_32 avg_time_slots_per_mtp; 1704 struct fixed31_32 pbn; 1705 struct fixed31_32 pbn_per_slot; 1706 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1707 uint8_t i; 1708 enum act_return_status ret; 1709 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1710 DC_LOGGER_INIT(link->ctx->logger); 1711 1712 /* notify immediate branch device table update */ 1713 if (dm_helpers_dp_mst_write_payload_allocation_table( 1714 stream->ctx, 1715 stream, 1716 &proposed_table, 1717 true)) { 1718 /* update mst stream allocation table software state */ 1719 update_mst_stream_alloc_table( 1720 link, 1721 pipe_ctx->stream_res.stream_enc, 1722 pipe_ctx->stream_res.hpo_dp_stream_enc, 1723 &proposed_table); 1724 } 1725 1726 DC_LOG_MST("%s " 1727 "stream_count: %d: \n ", 1728 __func__, 1729 link->mst_stream_alloc_table.stream_count); 1730 1731 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1732 DC_LOG_MST("stream_enc[%d]: %p " 1733 "stream[%d].hpo_dp_stream_enc: %p " 1734 "stream[%d].vcp_id: %d " 1735 "stream[%d].slot_count: %d\n", 1736 i, 1737 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1738 i, 1739 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1740 i, 1741 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1742 i, 1743 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1744 } 1745 1746 ASSERT(proposed_table.stream_count > 0); 1747 1748 /* update mst stream allocation table hardware state */ 1749 if (link_hwss->ext.update_stream_allocation_table == NULL || 1750 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1751 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1752 return DC_ERROR_UNEXPECTED; 1753 } 1754 1755 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1756 &link->mst_stream_alloc_table); 1757 1758 /* poll for immediate branch device ACT handled */ 1759 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1760 stream->ctx, 1761 stream); 1762 1763 if (ret != ACT_LINK_LOST) { 1764 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1765 dm_helpers_dp_mst_send_payload_allocation( 1766 stream->ctx, 1767 stream, 1768 true); 1769 } 1770 1771 /* increase throttled vcp size */ 1772 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1773 pbn_per_slot = get_pbn_per_slot(stream); 1774 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1775 1776 if (link_hwss->ext.set_throttled_vcp_size) 1777 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1778 if (link_hwss->ext.set_hblank_min_symbol_width) 1779 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1780 &link->cur_link_settings, 1781 avg_time_slots_per_mtp); 1782 1783 return DC_OK; 1784 } 1785 1786 static void disable_link(struct dc_link *link, const struct link_resource *link_res, 1787 enum signal_type signal) 1788 { 1789 /* 1790 * TODO: implement call for dp_set_hw_test_pattern 1791 * it is needed for compliance testing 1792 */ 1793 1794 /* Here we need to specify that encoder output settings 1795 * need to be calculated as for the set mode, 1796 * it will lead to querying dynamic link capabilities 1797 * which should be done before enable output 1798 */ 1799 1800 if (dc_is_dp_signal(signal)) { 1801 /* SST DP, eDP */ 1802 struct dc_link_settings link_settings = link->cur_link_settings; 1803 if (dc_is_dp_sst_signal(signal)) { 1804 dp_disable_link_phy(link, link_res, signal); 1805 } else { 1806 dp_disable_link_phy_mst(link, link_res, signal); 1807 /* set the sink to SST mode after disabling the link */ 1808 enable_mst_on_sink(link, false); 1809 } 1810 if (dc_is_dp_sst_signal(signal) || 1811 link->mst_stream_alloc_table.stream_count == 0) { 1812 if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { 1813 dp_set_fec_enable(link, false); 1814 dp_set_fec_ready(link, link_res, false); 1815 } 1816 } 1817 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1818 link->dc->hwss.disable_link_output(link, link_res, signal); 1819 } 1820 1821 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1822 /* MST disable link only when no stream use the link */ 1823 if (link->mst_stream_alloc_table.stream_count <= 0) 1824 link->link_status.link_active = false; 1825 } else { 1826 link->link_status.link_active = false; 1827 } 1828 } 1829 1830 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1831 { 1832 struct dc_stream_state *stream = pipe_ctx->stream; 1833 struct dc_link *link = stream->link; 1834 enum dc_color_depth display_color_depth; 1835 enum engine_id eng_id; 1836 struct ext_hdmi_settings settings = {0}; 1837 bool is_over_340mhz = false; 1838 bool is_vga_mode = (stream->timing.h_addressable == 640) 1839 && (stream->timing.v_addressable == 480); 1840 struct dc *dc = pipe_ctx->stream->ctx->dc; 1841 1842 if (stream->phy_pix_clk == 0) 1843 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1844 if (stream->phy_pix_clk > 340000) 1845 is_over_340mhz = true; 1846 1847 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1848 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1849 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1850 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1851 /* DP159, Retimer settings */ 1852 eng_id = pipe_ctx->stream_res.stream_enc->id; 1853 1854 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1855 write_i2c_retimer_setting(pipe_ctx, 1856 is_vga_mode, is_over_340mhz, &settings); 1857 } else { 1858 write_i2c_default_retimer_setting(pipe_ctx, 1859 is_vga_mode, is_over_340mhz); 1860 } 1861 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1862 /* PI3EQX1204, Redriver settings */ 1863 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1864 } 1865 } 1866 1867 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1868 write_scdc_data( 1869 stream->link->ddc, 1870 stream->phy_pix_clk, 1871 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 1872 1873 memset(&stream->link->cur_link_settings, 0, 1874 sizeof(struct dc_link_settings)); 1875 1876 display_color_depth = stream->timing.display_color_depth; 1877 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1878 display_color_depth = COLOR_DEPTH_888; 1879 1880 dc->hwss.enable_tmds_link_output( 1881 link, 1882 &pipe_ctx->link_res, 1883 pipe_ctx->stream->signal, 1884 pipe_ctx->clock_source->id, 1885 display_color_depth, 1886 stream->phy_pix_clk); 1887 1888 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1889 read_scdc_data(link->ddc); 1890 } 1891 1892 static enum dc_status enable_link_dp(struct dc_state *state, 1893 struct pipe_ctx *pipe_ctx) 1894 { 1895 struct dc_stream_state *stream = pipe_ctx->stream; 1896 enum dc_status status; 1897 bool skip_video_pattern; 1898 struct dc_link *link = stream->link; 1899 const struct dc_link_settings *link_settings = 1900 &pipe_ctx->link_config.dp_link_settings; 1901 bool fec_enable; 1902 int i; 1903 bool apply_seamless_boot_optimization = false; 1904 uint32_t bl_oled_enable_delay = 50; // in ms 1905 uint32_t post_oui_delay = 30; // 30ms 1906 /* Reduce link bandwidth between failed link training attempts. */ 1907 bool do_fallback = false; 1908 1909 // check for seamless boot 1910 for (i = 0; i < state->stream_count; i++) { 1911 if (state->streams[i]->apply_seamless_boot_optimization) { 1912 apply_seamless_boot_optimization = true; 1913 break; 1914 } 1915 } 1916 1917 /* Train with fallback when enabling DPIA link. Conventional links are 1918 * trained with fallback during sink detection. 1919 */ 1920 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 1921 do_fallback = true; 1922 1923 /* 1924 * Temporary w/a to get DP2.0 link rates to work with SST. 1925 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 1926 */ 1927 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 1928 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 1929 link->dc->debug.set_mst_en_for_sst) { 1930 enable_mst_on_sink(link, true); 1931 } 1932 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1933 /*in case it is not on*/ 1934 if (!link->dc->config.edp_no_power_sequencing) 1935 link->dc->hwss.edp_power_control(link, true); 1936 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1937 } 1938 1939 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 1940 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 1941 } else { 1942 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1943 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 1944 if (state->clk_mgr && !apply_seamless_boot_optimization) 1945 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 1946 state, false); 1947 } 1948 1949 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 1950 dpcd_set_source_specific_data(link); 1951 if (link->dpcd_sink_ext_caps.raw != 0) { 1952 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 1953 msleep(post_oui_delay); 1954 } 1955 1956 // similarly, mode switch can cause loss of cable ID 1957 dpcd_write_cable_id_to_dprx(link); 1958 1959 skip_video_pattern = true; 1960 1961 if (link_settings->link_rate == LINK_RATE_LOW) 1962 skip_video_pattern = false; 1963 1964 if (perform_link_training_with_retries(link_settings, 1965 skip_video_pattern, 1966 LINK_TRAINING_ATTEMPTS, 1967 pipe_ctx, 1968 pipe_ctx->stream->signal, 1969 do_fallback)) { 1970 status = DC_OK; 1971 } else { 1972 status = DC_FAIL_DP_LINK_TRAINING; 1973 } 1974 1975 if (link->preferred_training_settings.fec_enable) 1976 fec_enable = *link->preferred_training_settings.fec_enable; 1977 else 1978 fec_enable = true; 1979 1980 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 1981 dp_set_fec_enable(link, fec_enable); 1982 1983 // during mode set we do DP_SET_POWER off then on, aux writes are lost 1984 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 1985 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 1986 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 1987 set_default_brightness_aux(link); // TODO: use cached if known 1988 if (link->dpcd_sink_ext_caps.bits.oled == 1) 1989 msleep(bl_oled_enable_delay); 1990 link_backlight_enable_aux(link, true); 1991 } 1992 1993 return status; 1994 } 1995 1996 static enum dc_status enable_link_edp( 1997 struct dc_state *state, 1998 struct pipe_ctx *pipe_ctx) 1999 { 2000 return enable_link_dp(state, pipe_ctx); 2001 } 2002 2003 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2004 { 2005 struct dc_stream_state *stream = pipe_ctx->stream; 2006 struct dc_link *link = stream->link; 2007 struct dc *dc = stream->ctx->dc; 2008 2009 if (stream->phy_pix_clk == 0) 2010 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2011 2012 memset(&stream->link->cur_link_settings, 0, 2013 sizeof(struct dc_link_settings)); 2014 dc->hwss.enable_lvds_link_output( 2015 link, 2016 &pipe_ctx->link_res, 2017 pipe_ctx->clock_source->id, 2018 stream->phy_pix_clk); 2019 2020 } 2021 2022 static enum dc_status enable_link_dp_mst( 2023 struct dc_state *state, 2024 struct pipe_ctx *pipe_ctx) 2025 { 2026 struct dc_link *link = pipe_ctx->stream->link; 2027 2028 /* sink signal type after MST branch is MST. Multiple MST sinks 2029 * share one link. Link DP PHY is enable or training only once. 2030 */ 2031 if (link->link_status.link_active) 2032 return DC_OK; 2033 2034 /* clear payload table */ 2035 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2036 2037 /* to make sure the pending down rep can be processed 2038 * before enabling the link 2039 */ 2040 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2041 2042 /* set the sink to MST mode before enabling the link */ 2043 enable_mst_on_sink(link, true); 2044 2045 return enable_link_dp(state, pipe_ctx); 2046 } 2047 2048 static enum dc_status enable_link( 2049 struct dc_state *state, 2050 struct pipe_ctx *pipe_ctx) 2051 { 2052 enum dc_status status = DC_ERROR_UNEXPECTED; 2053 struct dc_stream_state *stream = pipe_ctx->stream; 2054 struct dc_link *link = stream->link; 2055 2056 /* There's some scenarios where driver is unloaded with display 2057 * still enabled. When driver is reloaded, it may cause a display 2058 * to not light up if there is a mismatch between old and new 2059 * link settings. Need to call disable first before enabling at 2060 * new link settings. 2061 */ 2062 if (link->link_status.link_active) { 2063 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2064 } 2065 2066 switch (pipe_ctx->stream->signal) { 2067 case SIGNAL_TYPE_DISPLAY_PORT: 2068 status = enable_link_dp(state, pipe_ctx); 2069 break; 2070 case SIGNAL_TYPE_EDP: 2071 status = enable_link_edp(state, pipe_ctx); 2072 break; 2073 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2074 status = enable_link_dp_mst(state, pipe_ctx); 2075 msleep(200); 2076 break; 2077 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2078 case SIGNAL_TYPE_DVI_DUAL_LINK: 2079 case SIGNAL_TYPE_HDMI_TYPE_A: 2080 enable_link_hdmi(pipe_ctx); 2081 status = DC_OK; 2082 break; 2083 case SIGNAL_TYPE_LVDS: 2084 enable_link_lvds(pipe_ctx); 2085 status = DC_OK; 2086 break; 2087 case SIGNAL_TYPE_VIRTUAL: 2088 status = DC_OK; 2089 break; 2090 default: 2091 break; 2092 } 2093 2094 if (status == DC_OK) { 2095 pipe_ctx->stream->link->link_status.link_active = true; 2096 } 2097 2098 return status; 2099 } 2100 2101 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2102 { 2103 struct dc *dc = pipe_ctx->stream->ctx->dc; 2104 struct dc_stream_state *stream = pipe_ctx->stream; 2105 struct dc_link *link = stream->sink->link; 2106 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2107 2108 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2109 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2110 2111 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2112 2113 if (pipe_ctx->stream->sink) { 2114 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2115 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2116 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2117 pipe_ctx->stream->sink->edid_caps.display_name, 2118 pipe_ctx->stream->signal); 2119 } 2120 } 2121 2122 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2123 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2124 return; 2125 2126 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2127 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2128 set_avmute(pipe_ctx, true); 2129 } 2130 2131 dc->hwss.disable_audio_stream(pipe_ctx); 2132 2133 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2134 update_psp_stream_config(pipe_ctx, true); 2135 #endif 2136 dc->hwss.blank_stream(pipe_ctx); 2137 2138 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2139 deallocate_mst_payload(pipe_ctx); 2140 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2141 link_is_dp_128b_132b_signal(pipe_ctx)) 2142 update_sst_payload(pipe_ctx, false); 2143 2144 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2145 struct ext_hdmi_settings settings = {0}; 2146 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2147 2148 unsigned short masked_chip_caps = link->chip_caps & 2149 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2150 //Need to inform that sink is going to use legacy HDMI mode. 2151 write_scdc_data( 2152 link->ddc, 2153 165000,//vbios only handles 165Mhz. 2154 false); 2155 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2156 /* DP159, Retimer settings */ 2157 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2158 write_i2c_retimer_setting(pipe_ctx, 2159 false, false, &settings); 2160 else 2161 write_i2c_default_retimer_setting(pipe_ctx, 2162 false, false); 2163 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2164 /* PI3EQX1204, Redriver settings */ 2165 write_i2c_redriver_setting(pipe_ctx, false); 2166 } 2167 } 2168 2169 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2170 !link_is_dp_128b_132b_signal(pipe_ctx)) { 2171 2172 /* In DP1.x SST mode, our encoder will go to TPS1 2173 * when link is on but stream is off. 2174 * Disabling link before stream will avoid exposing TPS1 pattern 2175 * during the disable sequence as it will confuse some receivers 2176 * state machine. 2177 * In DP2 or MST mode, our encoder will stay video active 2178 */ 2179 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2180 dc->hwss.disable_stream(pipe_ctx); 2181 } else { 2182 dc->hwss.disable_stream(pipe_ctx); 2183 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2184 } 2185 2186 if (pipe_ctx->stream->timing.flags.DSC) { 2187 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2188 link_set_dsc_enable(pipe_ctx, false); 2189 } 2190 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2191 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2192 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2193 } 2194 2195 if (vpg && vpg->funcs->vpg_powerdown) 2196 vpg->funcs->vpg_powerdown(vpg); 2197 } 2198 2199 void link_set_dpms_on( 2200 struct dc_state *state, 2201 struct pipe_ctx *pipe_ctx) 2202 { 2203 struct dc *dc = pipe_ctx->stream->ctx->dc; 2204 struct dc_stream_state *stream = pipe_ctx->stream; 2205 struct dc_link *link = stream->sink->link; 2206 enum dc_status status; 2207 struct link_encoder *link_enc; 2208 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2209 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2210 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2211 2212 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2213 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2214 2215 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2216 2217 if (pipe_ctx->stream->sink) { 2218 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2219 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2220 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2221 pipe_ctx->stream->sink->edid_caps.display_name, 2222 pipe_ctx->stream->signal); 2223 } 2224 } 2225 2226 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2227 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2228 return; 2229 2230 link_enc = link_enc_cfg_get_link_enc(link); 2231 ASSERT(link_enc); 2232 2233 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2234 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 2235 if (link_enc) 2236 link_enc->funcs->setup( 2237 link_enc, 2238 pipe_ctx->stream->signal); 2239 } 2240 2241 pipe_ctx->stream->link->link_state_valid = true; 2242 2243 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2244 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2245 otg_out_dest = OUT_MUX_HPO_DP; 2246 else 2247 otg_out_dest = OUT_MUX_DIO; 2248 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2249 } 2250 2251 link_hwss->setup_stream_attribute(pipe_ctx); 2252 2253 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2254 bool apply_edp_fast_boot_optimization = 2255 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2256 2257 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2258 2259 // Enable VPG before building infoframe 2260 if (vpg && vpg->funcs->vpg_poweron) 2261 vpg->funcs->vpg_poweron(vpg); 2262 2263 resource_build_info_frame(pipe_ctx); 2264 dc->hwss.update_info_frame(pipe_ctx); 2265 2266 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2267 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2268 2269 /* Do not touch link on seamless boot optimization. */ 2270 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2271 pipe_ctx->stream->dpms_off = false; 2272 2273 /* Still enable stream features & audio on seamless boot for DP external displays */ 2274 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2275 enable_stream_features(pipe_ctx); 2276 dc->hwss.enable_audio_stream(pipe_ctx); 2277 } 2278 2279 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2280 update_psp_stream_config(pipe_ctx, false); 2281 #endif 2282 return; 2283 } 2284 2285 /* eDP lit up by bios already, no need to enable again. */ 2286 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2287 apply_edp_fast_boot_optimization && 2288 !pipe_ctx->stream->timing.flags.DSC && 2289 !pipe_ctx->next_odm_pipe) { 2290 pipe_ctx->stream->dpms_off = false; 2291 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2292 update_psp_stream_config(pipe_ctx, false); 2293 #endif 2294 return; 2295 } 2296 2297 if (pipe_ctx->stream->dpms_off) 2298 return; 2299 2300 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2301 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2302 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2303 * will be automatically set at a later time when the video is enabled 2304 * (DP_VID_STREAM_EN = 1). 2305 */ 2306 if (pipe_ctx->stream->timing.flags.DSC) { 2307 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2308 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2309 link_set_dsc_enable(pipe_ctx, true); 2310 2311 } 2312 2313 status = enable_link(state, pipe_ctx); 2314 2315 if (status != DC_OK) { 2316 DC_LOG_WARNING("enabling link %u failed: %d\n", 2317 pipe_ctx->stream->link->link_index, 2318 status); 2319 2320 /* Abort stream enable *unless* the failure was due to 2321 * DP link training - some DP monitors will recover and 2322 * show the stream anyway. But MST displays can't proceed 2323 * without link training. 2324 */ 2325 if (status != DC_FAIL_DP_LINK_TRAINING || 2326 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2327 if (false == stream->link->link_status.link_active) 2328 disable_link(stream->link, &pipe_ctx->link_res, 2329 pipe_ctx->stream->signal); 2330 BREAK_TO_DEBUGGER(); 2331 return; 2332 } 2333 } 2334 2335 /* turn off otg test pattern if enable */ 2336 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2337 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2338 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2339 COLOR_DEPTH_UNDEFINED); 2340 2341 /* This second call is needed to reconfigure the DIG 2342 * as a workaround for the incorrect value being applied 2343 * from transmitter control. 2344 */ 2345 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2346 link_is_dp_128b_132b_signal(pipe_ctx))) 2347 if (link_enc) 2348 link_enc->funcs->setup( 2349 link_enc, 2350 pipe_ctx->stream->signal); 2351 2352 dc->hwss.enable_stream(pipe_ctx); 2353 2354 /* Set DPS PPS SDP (AKA "info frames") */ 2355 if (pipe_ctx->stream->timing.flags.DSC) { 2356 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2357 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2358 dp_set_dsc_on_rx(pipe_ctx, true); 2359 link_set_dsc_pps_packet(pipe_ctx, true, true); 2360 } 2361 } 2362 2363 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2364 allocate_mst_payload(pipe_ctx); 2365 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2366 link_is_dp_128b_132b_signal(pipe_ctx)) 2367 update_sst_payload(pipe_ctx, true); 2368 2369 dc->hwss.unblank_stream(pipe_ctx, 2370 &pipe_ctx->stream->link->cur_link_settings); 2371 2372 if (stream->sink_patches.delay_ignore_msa > 0) 2373 msleep(stream->sink_patches.delay_ignore_msa); 2374 2375 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2376 enable_stream_features(pipe_ctx); 2377 #if defined(CONFIG_DRM_AMD_DC_HDCP) 2378 update_psp_stream_config(pipe_ctx, false); 2379 #endif 2380 2381 dc->hwss.enable_audio_stream(pipe_ctx); 2382 2383 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2384 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2385 dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx); 2386 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2387 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2388 link_set_dsc_enable(pipe_ctx, true); 2389 } 2390 2391 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2392 set_avmute(pipe_ctx, false); 2393 } 2394 } 2395 2396