1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* FILE POLICY AND INTENDED USAGE:
27  * This file owns the programming sequence of stream's dpms state associated
28  * with the link and link's enable/disable sequences as result of the stream's
29  * dpms state change.
30  *
31  * TODO - The reason link owns stream's dpms programming sequence is
32  * because dpms programming sequence is highly dependent on underlying signal
33  * specific link protocols. This unfortunately causes link to own a portion of
34  * stream state programming sequence. This creates a gray area where the
35  * boundary between link and stream is not clearly defined.
36  */
37 
38 #include "link_dpms.h"
39 #include "link_hwss.h"
40 #include "link_validation.h"
41 #include "accessories/link_fpga.h"
42 #include "accessories/link_dp_trace.h"
43 #include "protocols/link_dpcd.h"
44 #include "protocols/link_ddc.h"
45 #include "protocols/link_hpd.h"
46 #include "protocols/link_dp_phy.h"
47 #include "protocols/link_dp_capability.h"
48 #include "protocols/link_dp_training.h"
49 #include "protocols/link_edp_panel_control.h"
50 #include "protocols/link_dp_dpia_bw.h"
51 
52 #include "dm_helpers.h"
53 #include "link_enc_cfg.h"
54 #include "resource.h"
55 #include "dsc.h"
56 #include "dccg.h"
57 #include "clk_mgr.h"
58 #include "atomfirmware.h"
59 #define DC_LOGGER_INIT(logger)
60 
61 #define LINK_INFO(...) \
62 	DC_LOG_HW_HOTPLUG(  \
63 		__VA_ARGS__)
64 
65 #define RETIMER_REDRIVER_INFO(...) \
66 	DC_LOG_RETIMER_REDRIVER(  \
67 		__VA_ARGS__)
68 #include "dc/dcn30/dcn30_vpg.h"
69 
70 #define MAX_MTP_SLOT_COUNT 64
71 #define LINK_TRAINING_ATTEMPTS 4
72 #define PEAK_FACTOR_X1000 1006
73 
74 void link_blank_all_dp_displays(struct dc *dc)
75 {
76 	unsigned int i;
77 	uint8_t dpcd_power_state = '\0';
78 	enum dc_status status = DC_ERROR_UNEXPECTED;
79 
80 	for (i = 0; i < dc->link_count; i++) {
81 		if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
82 			(dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
83 			continue;
84 
85 		/* DP 2.0 spec requires that we read LTTPR caps first */
86 		dp_retrieve_lttpr_cap(dc->links[i]);
87 		/* if any of the displays are lit up turn them off */
88 		status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
89 							&dpcd_power_state, sizeof(dpcd_power_state));
90 
91 		if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
92 			link_blank_dp_stream(dc->links[i], true);
93 	}
94 
95 }
96 
97 void link_blank_all_edp_displays(struct dc *dc)
98 {
99 	unsigned int i;
100 	uint8_t dpcd_power_state = '\0';
101 	enum dc_status status = DC_ERROR_UNEXPECTED;
102 
103 	for (i = 0; i < dc->link_count; i++) {
104 		if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
105 			(!dc->links[i]->edp_sink_present))
106 			continue;
107 
108 		/* if any of the displays are lit up turn them off */
109 		status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
110 							&dpcd_power_state, sizeof(dpcd_power_state));
111 
112 		if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
113 			link_blank_dp_stream(dc->links[i], true);
114 	}
115 }
116 
117 void link_blank_dp_stream(struct dc_link *link, bool hw_init)
118 {
119 	unsigned int j;
120 	struct dc  *dc = link->ctx->dc;
121 	enum signal_type signal = link->connector_signal;
122 
123 	if ((signal == SIGNAL_TYPE_EDP) ||
124 		(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
125 		if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
126 			link->link_enc->funcs->get_dig_frontend &&
127 			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
128 			unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
129 
130 			if (fe != ENGINE_ID_UNKNOWN)
131 				for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
132 					if (fe == dc->res_pool->stream_enc[j]->id) {
133 						dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
134 									dc->res_pool->stream_enc[j]);
135 						break;
136 					}
137 				}
138 		}
139 
140 		if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
141 			dpcd_write_rx_power_ctrl(link, false);
142 	}
143 }
144 
145 void link_set_all_streams_dpms_off_for_link(struct dc_link *link)
146 {
147 	struct pipe_ctx *pipes[MAX_PIPES];
148 	struct dc_state *state = link->dc->current_state;
149 	uint8_t count;
150 	int i;
151 	struct dc_stream_update stream_update;
152 	bool dpms_off = true;
153 	struct link_resource link_res = {0};
154 
155 	memset(&stream_update, 0, sizeof(stream_update));
156 	stream_update.dpms_off = &dpms_off;
157 
158 	link_get_master_pipes_with_dpms_on(link, state, &count, pipes);
159 
160 	for (i = 0; i < count; i++) {
161 		stream_update.stream = pipes[i]->stream;
162 		dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
163 				pipes[i]->stream, &stream_update,
164 				state);
165 	}
166 
167 	/* link can be also enabled by vbios. In this case it is not recorded
168 	 * in pipe_ctx. Disable link phy here to make sure it is completely off
169 	 */
170 	dp_disable_link_phy(link, &link_res, link->connector_signal);
171 }
172 
173 void link_resume(struct dc_link *link)
174 {
175 	if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
176 		program_hpd_filter(link);
177 }
178 
179 /* This function returns true if the pipe is used to feed video signal directly
180  * to the link.
181  */
182 static bool is_master_pipe_for_link(const struct dc_link *link,
183 		const struct pipe_ctx *pipe)
184 {
185 	return resource_is_pipe_type(pipe, OTG_MASTER) &&
186 			pipe->stream->link == link;
187 }
188 
189 /*
190  * This function finds all master pipes feeding to a given link with dpms set to
191  * on in given dc state.
192  */
193 void link_get_master_pipes_with_dpms_on(const struct dc_link *link,
194 		struct dc_state *state,
195 		uint8_t *count,
196 		struct pipe_ctx *pipes[MAX_PIPES])
197 {
198 	int i;
199 	struct pipe_ctx *pipe = NULL;
200 
201 	*count = 0;
202 	for (i = 0; i < MAX_PIPES; i++) {
203 		pipe = &state->res_ctx.pipe_ctx[i];
204 
205 		if (is_master_pipe_for_link(link, pipe) &&
206 				pipe->stream->dpms_off == false) {
207 			pipes[(*count)++] = pipe;
208 		}
209 	}
210 }
211 
212 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
213 		enum engine_id eng_id,
214 		struct ext_hdmi_settings *settings)
215 {
216 	bool result = false;
217 	int i = 0;
218 	struct integrated_info *integrated_info =
219 			pipe_ctx->stream->ctx->dc_bios->integrated_info;
220 
221 	if (integrated_info == NULL)
222 		return false;
223 
224 	/*
225 	 * Get retimer settings from sbios for passing SI eye test for DCE11
226 	 * The setting values are varied based on board revision and port id
227 	 * Therefore the setting values of each ports is passed by sbios.
228 	 */
229 
230 	// Check if current bios contains ext Hdmi settings
231 	if (integrated_info->gpu_cap_info & 0x20) {
232 		switch (eng_id) {
233 		case ENGINE_ID_DIGA:
234 			settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
235 			settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
236 			settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
237 			memmove(settings->reg_settings,
238 					integrated_info->dp0_ext_hdmi_reg_settings,
239 					sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
240 			memmove(settings->reg_settings_6g,
241 					integrated_info->dp0_ext_hdmi_6g_reg_settings,
242 					sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
243 			result = true;
244 			break;
245 		case ENGINE_ID_DIGB:
246 			settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
247 			settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
248 			settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
249 			memmove(settings->reg_settings,
250 					integrated_info->dp1_ext_hdmi_reg_settings,
251 					sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
252 			memmove(settings->reg_settings_6g,
253 					integrated_info->dp1_ext_hdmi_6g_reg_settings,
254 					sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
255 			result = true;
256 			break;
257 		case ENGINE_ID_DIGC:
258 			settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
259 			settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
260 			settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
261 			memmove(settings->reg_settings,
262 					integrated_info->dp2_ext_hdmi_reg_settings,
263 					sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
264 			memmove(settings->reg_settings_6g,
265 					integrated_info->dp2_ext_hdmi_6g_reg_settings,
266 					sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
267 			result = true;
268 			break;
269 		case ENGINE_ID_DIGD:
270 			settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
271 			settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
272 			settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
273 			memmove(settings->reg_settings,
274 					integrated_info->dp3_ext_hdmi_reg_settings,
275 					sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
276 			memmove(settings->reg_settings_6g,
277 					integrated_info->dp3_ext_hdmi_6g_reg_settings,
278 					sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
279 			result = true;
280 			break;
281 		default:
282 			break;
283 		}
284 
285 		if (result == true) {
286 			// Validate settings from bios integrated info table
287 			if (settings->slv_addr == 0)
288 				return false;
289 			if (settings->reg_num > 9)
290 				return false;
291 			if (settings->reg_num_6g > 3)
292 				return false;
293 
294 			for (i = 0; i < settings->reg_num; i++) {
295 				if (settings->reg_settings[i].i2c_reg_index > 0x20)
296 					return false;
297 			}
298 
299 			for (i = 0; i < settings->reg_num_6g; i++) {
300 				if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
301 					return false;
302 			}
303 		}
304 	}
305 
306 	return result;
307 }
308 
309 static bool write_i2c(struct pipe_ctx *pipe_ctx,
310 		uint8_t address, uint8_t *buffer, uint32_t length)
311 {
312 	struct i2c_command cmd = {0};
313 	struct i2c_payload payload = {0};
314 
315 	memset(&payload, 0, sizeof(payload));
316 	memset(&cmd, 0, sizeof(cmd));
317 
318 	cmd.number_of_payloads = 1;
319 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
320 	cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
321 
322 	payload.address = address;
323 	payload.data = buffer;
324 	payload.length = length;
325 	payload.write = true;
326 	cmd.payloads = &payload;
327 
328 	if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
329 			pipe_ctx->stream->link, &cmd))
330 		return true;
331 
332 	return false;
333 }
334 
335 static void write_i2c_retimer_setting(
336 		struct pipe_ctx *pipe_ctx,
337 		bool is_vga_mode,
338 		bool is_over_340mhz,
339 		struct ext_hdmi_settings *settings)
340 {
341 	uint8_t slave_address = (settings->slv_addr >> 1);
342 	uint8_t buffer[2];
343 	const uint8_t apply_rx_tx_change = 0x4;
344 	uint8_t offset = 0xA;
345 	uint8_t value = 0;
346 	int i = 0;
347 	bool i2c_success = false;
348 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
349 
350 	memset(&buffer, 0, sizeof(buffer));
351 
352 	/* Start Ext-Hdmi programming*/
353 
354 	for (i = 0; i < settings->reg_num; i++) {
355 		/* Apply 3G settings */
356 		if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
357 
358 			buffer[0] = settings->reg_settings[i].i2c_reg_index;
359 			buffer[1] = settings->reg_settings[i].i2c_reg_val;
360 			i2c_success = write_i2c(pipe_ctx, slave_address,
361 						buffer, sizeof(buffer));
362 			RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
363 				offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
364 				slave_address, buffer[0], buffer[1], i2c_success?1:0);
365 
366 			if (!i2c_success)
367 				goto i2c_write_fail;
368 
369 			/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
370 			 * needs to be set to 1 on every 0xA-0xC write.
371 			 */
372 			if (settings->reg_settings[i].i2c_reg_index == 0xA ||
373 				settings->reg_settings[i].i2c_reg_index == 0xB ||
374 				settings->reg_settings[i].i2c_reg_index == 0xC) {
375 
376 				/* Query current value from offset 0xA */
377 				if (settings->reg_settings[i].i2c_reg_index == 0xA)
378 					value = settings->reg_settings[i].i2c_reg_val;
379 				else {
380 					i2c_success =
381 						link_query_ddc_data(
382 						pipe_ctx->stream->link->ddc,
383 						slave_address, &offset, 1, &value, 1);
384 					if (!i2c_success)
385 						goto i2c_write_fail;
386 				}
387 
388 				buffer[0] = offset;
389 				/* Set APPLY_RX_TX_CHANGE bit to 1 */
390 				buffer[1] = value | apply_rx_tx_change;
391 				i2c_success = write_i2c(pipe_ctx, slave_address,
392 						buffer, sizeof(buffer));
393 				RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
394 					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
395 					slave_address, buffer[0], buffer[1], i2c_success?1:0);
396 				if (!i2c_success)
397 					goto i2c_write_fail;
398 			}
399 		}
400 	}
401 
402 	/* Apply 3G settings */
403 	if (is_over_340mhz) {
404 		for (i = 0; i < settings->reg_num_6g; i++) {
405 			/* Apply 3G settings */
406 			if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
407 
408 				buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
409 				buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
410 				i2c_success = write_i2c(pipe_ctx, slave_address,
411 							buffer, sizeof(buffer));
412 				RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
413 					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
414 					slave_address, buffer[0], buffer[1], i2c_success?1:0);
415 
416 				if (!i2c_success)
417 					goto i2c_write_fail;
418 
419 				/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
420 				 * needs to be set to 1 on every 0xA-0xC write.
421 				 */
422 				if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
423 					settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
424 					settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
425 
426 					/* Query current value from offset 0xA */
427 					if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
428 						value = settings->reg_settings_6g[i].i2c_reg_val;
429 					else {
430 						i2c_success =
431 								link_query_ddc_data(
432 								pipe_ctx->stream->link->ddc,
433 								slave_address, &offset, 1, &value, 1);
434 						if (!i2c_success)
435 							goto i2c_write_fail;
436 					}
437 
438 					buffer[0] = offset;
439 					/* Set APPLY_RX_TX_CHANGE bit to 1 */
440 					buffer[1] = value | apply_rx_tx_change;
441 					i2c_success = write_i2c(pipe_ctx, slave_address,
442 							buffer, sizeof(buffer));
443 					RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
444 						offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
445 						slave_address, buffer[0], buffer[1], i2c_success?1:0);
446 					if (!i2c_success)
447 						goto i2c_write_fail;
448 				}
449 			}
450 		}
451 	}
452 
453 	if (is_vga_mode) {
454 		/* Program additional settings if using 640x480 resolution */
455 
456 		/* Write offset 0xFF to 0x01 */
457 		buffer[0] = 0xff;
458 		buffer[1] = 0x01;
459 		i2c_success = write_i2c(pipe_ctx, slave_address,
460 				buffer, sizeof(buffer));
461 		RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
462 				offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
463 				slave_address, buffer[0], buffer[1], i2c_success?1:0);
464 		if (!i2c_success)
465 			goto i2c_write_fail;
466 
467 		/* Write offset 0x00 to 0x23 */
468 		buffer[0] = 0x00;
469 		buffer[1] = 0x23;
470 		i2c_success = write_i2c(pipe_ctx, slave_address,
471 				buffer, sizeof(buffer));
472 		RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
473 			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
474 			slave_address, buffer[0], buffer[1], i2c_success?1:0);
475 		if (!i2c_success)
476 			goto i2c_write_fail;
477 
478 		/* Write offset 0xff to 0x00 */
479 		buffer[0] = 0xff;
480 		buffer[1] = 0x00;
481 		i2c_success = write_i2c(pipe_ctx, slave_address,
482 				buffer, sizeof(buffer));
483 		RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
484 			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
485 			slave_address, buffer[0], buffer[1], i2c_success?1:0);
486 		if (!i2c_success)
487 			goto i2c_write_fail;
488 
489 	}
490 
491 	return;
492 
493 i2c_write_fail:
494 	DC_LOG_DEBUG("Set retimer failed");
495 }
496 
497 static void write_i2c_default_retimer_setting(
498 		struct pipe_ctx *pipe_ctx,
499 		bool is_vga_mode,
500 		bool is_over_340mhz)
501 {
502 	uint8_t slave_address = (0xBA >> 1);
503 	uint8_t buffer[2];
504 	bool i2c_success = false;
505 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
506 
507 	memset(&buffer, 0, sizeof(buffer));
508 
509 	/* Program Slave Address for tuning single integrity */
510 	/* Write offset 0x0A to 0x13 */
511 	buffer[0] = 0x0A;
512 	buffer[1] = 0x13;
513 	i2c_success = write_i2c(pipe_ctx, slave_address,
514 			buffer, sizeof(buffer));
515 	RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
516 		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
517 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
518 	if (!i2c_success)
519 		goto i2c_write_fail;
520 
521 	/* Write offset 0x0A to 0x17 */
522 	buffer[0] = 0x0A;
523 	buffer[1] = 0x17;
524 	i2c_success = write_i2c(pipe_ctx, slave_address,
525 			buffer, sizeof(buffer));
526 	RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
527 		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
528 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
529 	if (!i2c_success)
530 		goto i2c_write_fail;
531 
532 	/* Write offset 0x0B to 0xDA or 0xD8 */
533 	buffer[0] = 0x0B;
534 	buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
535 	i2c_success = write_i2c(pipe_ctx, slave_address,
536 			buffer, sizeof(buffer));
537 	RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
538 		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
539 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
540 	if (!i2c_success)
541 		goto i2c_write_fail;
542 
543 	/* Write offset 0x0A to 0x17 */
544 	buffer[0] = 0x0A;
545 	buffer[1] = 0x17;
546 	i2c_success = write_i2c(pipe_ctx, slave_address,
547 			buffer, sizeof(buffer));
548 	RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
549 		offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
550 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
551 	if (!i2c_success)
552 		goto i2c_write_fail;
553 
554 	/* Write offset 0x0C to 0x1D or 0x91 */
555 	buffer[0] = 0x0C;
556 	buffer[1] = is_over_340mhz ? 0x1D : 0x91;
557 	i2c_success = write_i2c(pipe_ctx, slave_address,
558 			buffer, sizeof(buffer));
559 	RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
560 		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
561 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
562 	if (!i2c_success)
563 		goto i2c_write_fail;
564 
565 	/* Write offset 0x0A to 0x17 */
566 	buffer[0] = 0x0A;
567 	buffer[1] = 0x17;
568 	i2c_success = write_i2c(pipe_ctx, slave_address,
569 			buffer, sizeof(buffer));
570 	RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
571 		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
572 		slave_address, buffer[0], buffer[1], i2c_success?1:0);
573 	if (!i2c_success)
574 		goto i2c_write_fail;
575 
576 
577 	if (is_vga_mode) {
578 		/* Program additional settings if using 640x480 resolution */
579 
580 		/* Write offset 0xFF to 0x01 */
581 		buffer[0] = 0xff;
582 		buffer[1] = 0x01;
583 		i2c_success = write_i2c(pipe_ctx, slave_address,
584 				buffer, sizeof(buffer));
585 		RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
586 			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
587 			slave_address, buffer[0], buffer[1], i2c_success?1:0);
588 		if (!i2c_success)
589 			goto i2c_write_fail;
590 
591 		/* Write offset 0x00 to 0x23 */
592 		buffer[0] = 0x00;
593 		buffer[1] = 0x23;
594 		i2c_success = write_i2c(pipe_ctx, slave_address,
595 				buffer, sizeof(buffer));
596 		RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
597 			offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
598 			slave_address, buffer[0], buffer[1], i2c_success?1:0);
599 		if (!i2c_success)
600 			goto i2c_write_fail;
601 
602 		/* Write offset 0xff to 0x00 */
603 		buffer[0] = 0xff;
604 		buffer[1] = 0x00;
605 		i2c_success = write_i2c(pipe_ctx, slave_address,
606 				buffer, sizeof(buffer));
607 		RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
608 			offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
609 			slave_address, buffer[0], buffer[1], i2c_success?1:0);
610 		if (!i2c_success)
611 			goto i2c_write_fail;
612 	}
613 
614 	return;
615 
616 i2c_write_fail:
617 	DC_LOG_DEBUG("Set default retimer failed");
618 }
619 
620 static void write_i2c_redriver_setting(
621 		struct pipe_ctx *pipe_ctx,
622 		bool is_over_340mhz)
623 {
624 	uint8_t slave_address = (0xF0 >> 1);
625 	uint8_t buffer[16];
626 	bool i2c_success = false;
627 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
628 
629 	memset(&buffer, 0, sizeof(buffer));
630 
631 	// Program Slave Address for tuning single integrity
632 	buffer[3] = 0x4E;
633 	buffer[4] = 0x4E;
634 	buffer[5] = 0x4E;
635 	buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
636 
637 	i2c_success = write_i2c(pipe_ctx, slave_address,
638 					buffer, sizeof(buffer));
639 	RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
640 		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
641 		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
642 		i2c_success = %d\n",
643 		slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
644 
645 	if (!i2c_success)
646 		DC_LOG_DEBUG("Set redriver failed");
647 }
648 
649 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
650 {
651 	struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
652 	struct link_encoder *link_enc = NULL;
653 	struct cp_psp_stream_config config = {0};
654 	enum dp_panel_mode panel_mode =
655 			dp_get_panel_mode(pipe_ctx->stream->link);
656 
657 	if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
658 		return;
659 
660 	link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
661 	ASSERT(link_enc);
662 	if (link_enc == NULL)
663 		return;
664 
665 	/* otg instance */
666 	config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
667 
668 	/* dig front end */
669 	config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
670 
671 	/* stream encoder index */
672 	config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
673 	if (dp_is_128b_132b_signal(pipe_ctx))
674 		config.stream_enc_idx =
675 				pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
676 
677 	/* dig back end */
678 	config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
679 
680 	/* link encoder index */
681 	config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
682 	if (dp_is_128b_132b_signal(pipe_ctx))
683 		config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
684 
685 	/* dio output index is dpia index for DPIA endpoint & dcio index by default */
686 	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
687 		config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
688 	else
689 		config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
690 
691 
692 	/* phy index */
693 	config.phy_idx = resource_transmitter_to_phy_idx(
694 			pipe_ctx->stream->link->dc, link_enc->transmitter);
695 	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
696 		/* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
697 		config.phy_idx = 0;
698 
699 	/* stream properties */
700 	config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
701 	config.mst_enabled = (pipe_ctx->stream->signal ==
702 			SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
703 	config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0;
704 	config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
705 			1 : 0;
706 	config.dpms_off = dpms_off;
707 
708 	/* dm stream context */
709 	config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
710 
711 	cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
712 }
713 
714 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
715 {
716 	struct dc  *dc = pipe_ctx->stream->ctx->dc;
717 
718 	if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
719 		return;
720 
721 	dc->hwss.set_avmute(pipe_ctx, enable);
722 }
723 
724 static void enable_mst_on_sink(struct dc_link *link, bool enable)
725 {
726 	unsigned char mstmCntl;
727 
728 	core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
729 	if (enable)
730 		mstmCntl |= DP_MST_EN;
731 	else
732 		mstmCntl &= (~DP_MST_EN);
733 
734 	core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
735 }
736 
737 static void dsc_optc_config_log(struct display_stream_compressor *dsc,
738 		struct dsc_optc_config *config)
739 {
740 	uint32_t precision = 1 << 28;
741 	uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
742 	uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
743 	uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
744 	DC_LOGGER_INIT(dsc->ctx->logger);
745 
746 	/* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
747 	 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
748 	 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
749 	 */
750 	ll_bytes_per_pix_fraq *= 10000000;
751 	ll_bytes_per_pix_fraq /= precision;
752 
753 	DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
754 			config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
755 	DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
756 	DC_LOG_DSC("\tslice_width %d", config->slice_width);
757 }
758 
759 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
760 {
761 	struct dc *dc = pipe_ctx->stream->ctx->dc;
762 	struct dc_stream_state *stream = pipe_ctx->stream;
763 	bool result = false;
764 
765 	if (dc_is_virtual_signal(stream->signal))
766 		result = true;
767 	else
768 		result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
769 	return result;
770 }
771 
772 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
773  * i.e. after dp_enable_dsc_on_rx() had been called
774  */
775 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
776 {
777 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
778 	struct dc_stream_state *stream = pipe_ctx->stream;
779 	struct pipe_ctx *odm_pipe;
780 	int opp_cnt = 1;
781 	DC_LOGGER_INIT(dsc->ctx->logger);
782 
783 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
784 		opp_cnt++;
785 
786 	if (enable) {
787 		struct dsc_config dsc_cfg;
788 		struct dsc_optc_config dsc_optc_cfg;
789 		enum optc_dsc_mode optc_dsc_mode;
790 
791 		/* Enable DSC hw block */
792 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
793 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
794 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
795 		dsc_cfg.color_depth = stream->timing.display_color_depth;
796 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
797 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
798 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
799 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
800 
801 		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
802 		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
803 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
804 			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
805 
806 			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
807 			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
808 		}
809 		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
810 		dsc_cfg.pic_width *= opp_cnt;
811 
812 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
813 
814 		/* Enable DSC in encoder */
815 		if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) {
816 			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
817 			dsc_optc_config_log(dsc, &dsc_optc_cfg);
818 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
819 									optc_dsc_mode,
820 									dsc_optc_cfg.bytes_per_pixel,
821 									dsc_optc_cfg.slice_width);
822 
823 			/* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
824 		}
825 
826 		/* Enable DSC in OPTC */
827 		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
828 		dsc_optc_config_log(dsc, &dsc_optc_cfg);
829 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
830 							optc_dsc_mode,
831 							dsc_optc_cfg.bytes_per_pixel,
832 							dsc_optc_cfg.slice_width);
833 	} else {
834 		/* disable DSC in OPTC */
835 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(
836 				pipe_ctx->stream_res.tg,
837 				OPTC_DSC_DISABLED, 0, 0);
838 
839 		/* disable DSC in stream encoder */
840 		if (dc_is_dp_signal(stream->signal)) {
841 			if (dp_is_128b_132b_signal(pipe_ctx))
842 				pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
843 										pipe_ctx->stream_res.hpo_dp_stream_enc,
844 										false,
845 										NULL,
846 										true);
847 			else {
848 				pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
849 						pipe_ctx->stream_res.stream_enc,
850 						OPTC_DSC_DISABLED, 0, 0);
851 				pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
852 							pipe_ctx->stream_res.stream_enc, false, NULL, true);
853 			}
854 		}
855 
856 		/* disable DSC block */
857 		pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
858 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
859 			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
860 	}
861 }
862 
863 /*
864  * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled;
865  * hence PPS info packet update need to use frame update instead of immediate update.
866  * Added parameter immediate_update for this purpose.
867  * The decision to use frame update is hard-coded in function dp_update_dsc_config(),
868  * which is the only place where a "false" would be passed in for param immediate_update.
869  *
870  * immediate_update is only applicable when DSC is enabled.
871  */
872 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)
873 {
874 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
875 	struct dc_stream_state *stream = pipe_ctx->stream;
876 
877 	if (!pipe_ctx->stream->timing.flags.DSC)
878 		return false;
879 
880 	if (!dsc)
881 		return false;
882 
883 	DC_LOGGER_INIT(dsc->ctx->logger);
884 
885 	if (enable) {
886 		struct dsc_config dsc_cfg;
887 		uint8_t dsc_packed_pps[128];
888 
889 		memset(&dsc_cfg, 0, sizeof(dsc_cfg));
890 		memset(dsc_packed_pps, 0, 128);
891 
892 		/* Enable DSC hw block */
893 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
894 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
895 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
896 		dsc_cfg.color_depth = stream->timing.display_color_depth;
897 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
898 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
899 
900 		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
901 		memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps));
902 		if (dc_is_dp_signal(stream->signal)) {
903 			DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
904 			if (dp_is_128b_132b_signal(pipe_ctx))
905 				pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
906 										pipe_ctx->stream_res.hpo_dp_stream_enc,
907 										true,
908 										&dsc_packed_pps[0],
909 										immediate_update);
910 			else
911 				pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
912 						pipe_ctx->stream_res.stream_enc,
913 						true,
914 						&dsc_packed_pps[0],
915 						immediate_update);
916 		}
917 	} else {
918 		/* disable DSC PPS in stream encoder */
919 		memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps));
920 		if (dc_is_dp_signal(stream->signal)) {
921 			if (dp_is_128b_132b_signal(pipe_ctx))
922 				pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
923 										pipe_ctx->stream_res.hpo_dp_stream_enc,
924 										false,
925 										NULL,
926 										true);
927 			else
928 				pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
929 						pipe_ctx->stream_res.stream_enc, false, NULL, true);
930 		}
931 	}
932 
933 	return true;
934 }
935 
936 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
937 {
938 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
939 	bool result = false;
940 
941 	if (!pipe_ctx->stream->timing.flags.DSC)
942 		goto out;
943 	if (!dsc)
944 		goto out;
945 
946 	if (enable) {
947 		{
948 			link_set_dsc_on_stream(pipe_ctx, true);
949 			result = true;
950 		}
951 	} else {
952 		dp_set_dsc_on_rx(pipe_ctx, false);
953 		link_set_dsc_on_stream(pipe_ctx, false);
954 		result = true;
955 	}
956 out:
957 	return result;
958 }
959 
960 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)
961 {
962 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
963 
964 	if (!pipe_ctx->stream->timing.flags.DSC)
965 		return false;
966 	if (!dsc)
967 		return false;
968 
969 	link_set_dsc_on_stream(pipe_ctx, true);
970 	link_set_dsc_pps_packet(pipe_ctx, true, false);
971 	return true;
972 }
973 
974 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
975 {
976 	struct dc_stream_state *stream = pipe_ctx->stream;
977 
978 	if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
979 		struct dc_link *link = stream->link;
980 		union down_spread_ctrl old_downspread;
981 		union down_spread_ctrl new_downspread;
982 
983 		memset(&old_downspread, 0, sizeof(old_downspread));
984 
985 		core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
986 				&old_downspread.raw, sizeof(old_downspread));
987 
988 		new_downspread.raw = old_downspread.raw;
989 
990 		new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
991 				(stream->ignore_msa_timing_param) ? 1 : 0;
992 
993 		if (new_downspread.raw != old_downspread.raw) {
994 			core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
995 				&new_downspread.raw, sizeof(new_downspread));
996 		}
997 
998 	} else {
999 		dm_helpers_mst_enable_stream_features(stream);
1000 	}
1001 }
1002 
1003 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
1004 {
1005 	const uint32_t VCP_Y_PRECISION = 1000;
1006 	uint64_t vcp_x, vcp_y;
1007 	DC_LOGGER_INIT(link->ctx->logger);
1008 
1009 	// Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
1010 	avg_time_slots_per_mtp = dc_fixpt_add(
1011 			avg_time_slots_per_mtp,
1012 			dc_fixpt_from_fraction(
1013 				1,
1014 				2*VCP_Y_PRECISION));
1015 
1016 	vcp_x = dc_fixpt_floor(
1017 			avg_time_slots_per_mtp);
1018 	vcp_y = dc_fixpt_floor(
1019 			dc_fixpt_mul_int(
1020 				dc_fixpt_sub_int(
1021 					avg_time_slots_per_mtp,
1022 					dc_fixpt_floor(
1023 							avg_time_slots_per_mtp)),
1024 				VCP_Y_PRECISION));
1025 
1026 
1027 	if (link->type == dc_connection_mst_branch)
1028 		DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
1029 				"X: %llu "
1030 				"Y: %llu/%d",
1031 				vcp_x,
1032 				vcp_y,
1033 				VCP_Y_PRECISION);
1034 	else
1035 		DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
1036 				"X: %llu "
1037 				"Y: %llu/%d",
1038 				vcp_x,
1039 				vcp_y,
1040 				VCP_Y_PRECISION);
1041 }
1042 
1043 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
1044 {
1045 	struct fixed31_32 mbytes_per_sec;
1046 	uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link,
1047 			&stream->link->cur_link_settings);
1048 	link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
1049 
1050 	mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
1051 
1052 	return dc_fixpt_div_int(mbytes_per_sec, 54);
1053 }
1054 
1055 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
1056 {
1057 	struct fixed31_32 peak_kbps;
1058 	uint32_t numerator = 0;
1059 	uint32_t denominator = 1;
1060 
1061 	/*
1062 	 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not
1063 	 * required when determining PBN/time slot utilization on the link between
1064 	 * us and the branch, since that overhead is already accounted for in
1065 	 * the get_pbn_per_slot function.
1066 	 *
1067 	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
1068 	 * common multiplier to render an integer PBN for all link rate/lane
1069 	 * counts combinations
1070 	 * calculate
1071 	 * peak_kbps *= (64/54)
1072 	 * peak_kbps /= (8 * 1000) convert to bytes
1073 	 */
1074 
1075 	numerator = 64;
1076 	denominator = 54 * 8 * 1000;
1077 	kbps *= numerator;
1078 	peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
1079 
1080 	return peak_kbps;
1081 }
1082 
1083 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
1084 {
1085 	uint64_t kbps;
1086 	enum dc_link_encoding_format link_encoding;
1087 
1088 	if (dp_is_128b_132b_signal(pipe_ctx))
1089 		link_encoding = DC_LINK_ENCODING_DP_128b_132b;
1090 	else
1091 		link_encoding = DC_LINK_ENCODING_DP_8b_10b;
1092 
1093 	kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);
1094 	return get_pbn_from_bw_in_kbps(kbps);
1095 }
1096 
1097 
1098 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST)
1099 static void get_lane_status(
1100 	struct dc_link *link,
1101 	uint32_t lane_count,
1102 	union lane_status *status,
1103 	union lane_align_status_updated *status_updated)
1104 {
1105 	unsigned int lane;
1106 	uint8_t dpcd_buf[3] = {0};
1107 
1108 	if (status == NULL || status_updated == NULL) {
1109 		return;
1110 	}
1111 
1112 	core_link_read_dpcd(
1113 			link,
1114 			DP_LANE0_1_STATUS,
1115 			dpcd_buf,
1116 			sizeof(dpcd_buf));
1117 
1118 	for (lane = 0; lane < lane_count; lane++) {
1119 		status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane);
1120 	}
1121 
1122 	status_updated->raw = dpcd_buf[2];
1123 }
1124 
1125 static bool poll_for_allocation_change_trigger(struct dc_link *link)
1126 {
1127 	/*
1128 	 * wait for ACT handled
1129 	 */
1130 	int i;
1131 	const int act_retries = 30;
1132 	enum act_return_status result = ACT_FAILED;
1133 	union payload_table_update_status update_status = {0};
1134 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1135 	union lane_align_status_updated lane_status_updated;
1136 	DC_LOGGER_INIT(link->ctx->logger);
1137 
1138 	if (link->aux_access_disabled)
1139 		return true;
1140 	for (i = 0; i < act_retries; i++) {
1141 		get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated);
1142 
1143 		if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) ||
1144 				!dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) ||
1145 				!dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) ||
1146 				!dp_is_interlane_aligned(lane_status_updated)) {
1147 			DC_LOG_ERROR("SST Update Payload: Link loss occurred while "
1148 					"polling for ACT handled.");
1149 			result = ACT_LINK_LOST;
1150 			break;
1151 		}
1152 		core_link_read_dpcd(
1153 				link,
1154 				DP_PAYLOAD_TABLE_UPDATE_STATUS,
1155 				&update_status.raw,
1156 				1);
1157 
1158 		if (update_status.bits.ACT_HANDLED == 1) {
1159 			DC_LOG_DP2("SST Update Payload: ACT handled by downstream.");
1160 			result = ACT_SUCCESS;
1161 			break;
1162 		}
1163 
1164 		fsleep(5000);
1165 	}
1166 
1167 	if (result == ACT_FAILED) {
1168 		DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, "
1169 				"continue on. Something is wrong with the branch.");
1170 	}
1171 
1172 	return (result == ACT_SUCCESS);
1173 }
1174 
1175 static void update_mst_stream_alloc_table(
1176 	struct dc_link *link,
1177 	struct stream_encoder *stream_enc,
1178 	struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
1179 	const struct dc_dp_mst_stream_allocation_table *proposed_table)
1180 {
1181 	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
1182 	struct link_mst_stream_allocation *dc_alloc;
1183 
1184 	int i;
1185 	int j;
1186 
1187 	/* if DRM proposed_table has more than one new payload */
1188 	ASSERT(proposed_table->stream_count -
1189 			link->mst_stream_alloc_table.stream_count < 2);
1190 
1191 	/* copy proposed_table to link, add stream encoder */
1192 	for (i = 0; i < proposed_table->stream_count; i++) {
1193 
1194 		for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
1195 			dc_alloc =
1196 			&link->mst_stream_alloc_table.stream_allocations[j];
1197 
1198 			if (dc_alloc->vcp_id ==
1199 				proposed_table->stream_allocations[i].vcp_id) {
1200 
1201 				work_table[i] = *dc_alloc;
1202 				work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
1203 				break; /* exit j loop */
1204 			}
1205 		}
1206 
1207 		/* new vcp_id */
1208 		if (j == link->mst_stream_alloc_table.stream_count) {
1209 			work_table[i].vcp_id =
1210 				proposed_table->stream_allocations[i].vcp_id;
1211 			work_table[i].slot_count =
1212 				proposed_table->stream_allocations[i].slot_count;
1213 			work_table[i].stream_enc = stream_enc;
1214 			work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
1215 		}
1216 	}
1217 
1218 	/* update link->mst_stream_alloc_table with work_table */
1219 	link->mst_stream_alloc_table.stream_count =
1220 			proposed_table->stream_count;
1221 	for (i = 0; i < MAX_CONTROLLER_NUM; i++)
1222 		link->mst_stream_alloc_table.stream_allocations[i] =
1223 				work_table[i];
1224 }
1225 
1226 static void remove_stream_from_alloc_table(
1227 		struct dc_link *link,
1228 		struct stream_encoder *dio_stream_enc,
1229 		struct hpo_dp_stream_encoder *hpo_dp_stream_enc)
1230 {
1231 	int i = 0;
1232 	struct link_mst_stream_allocation_table *table =
1233 			&link->mst_stream_alloc_table;
1234 
1235 	if (hpo_dp_stream_enc) {
1236 		for (; i < table->stream_count; i++)
1237 			if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc)
1238 				break;
1239 	} else {
1240 		for (; i < table->stream_count; i++)
1241 			if (dio_stream_enc == table->stream_allocations[i].stream_enc)
1242 				break;
1243 	}
1244 
1245 	if (i < table->stream_count) {
1246 		i++;
1247 		for (; i < table->stream_count; i++)
1248 			table->stream_allocations[i-1] = table->stream_allocations[i];
1249 		memset(&table->stream_allocations[table->stream_count-1], 0,
1250 				sizeof(struct link_mst_stream_allocation));
1251 		table->stream_count--;
1252 	}
1253 }
1254 
1255 static enum dc_status deallocate_mst_payload_with_temp_drm_wa(
1256 		struct pipe_ctx *pipe_ctx)
1257 {
1258 	struct dc_stream_state *stream = pipe_ctx->stream;
1259 	struct dc_link *link = stream->link;
1260 	struct dc_dp_mst_stream_allocation_table proposed_table = {0};
1261 	struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
1262 	int i;
1263 	bool mst_mode = (link->type == dc_connection_mst_branch);
1264 	/* adjust for drm changes*/
1265 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1266 	const struct dc_link_settings empty_link_settings = {0};
1267 	DC_LOGGER_INIT(link->ctx->logger);
1268 
1269 	if (link_hwss->ext.set_throttled_vcp_size)
1270 		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
1271 	if (link_hwss->ext.set_hblank_min_symbol_width)
1272 		link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1273 				&empty_link_settings,
1274 				avg_time_slots_per_mtp);
1275 
1276 	if (dm_helpers_dp_mst_write_payload_allocation_table(
1277 			stream->ctx,
1278 			stream,
1279 			&proposed_table,
1280 			false))
1281 		update_mst_stream_alloc_table(
1282 				link,
1283 				pipe_ctx->stream_res.stream_enc,
1284 				pipe_ctx->stream_res.hpo_dp_stream_enc,
1285 				&proposed_table);
1286 	else
1287 		DC_LOG_WARNING("Failed to update"
1288 				"MST allocation table for"
1289 				"pipe idx:%d\n",
1290 				pipe_ctx->pipe_idx);
1291 
1292 	DC_LOG_MST("%s"
1293 			"stream_count: %d: ",
1294 			__func__,
1295 			link->mst_stream_alloc_table.stream_count);
1296 
1297 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
1298 		DC_LOG_MST("stream_enc[%d]: %p      "
1299 		"stream[%d].hpo_dp_stream_enc: %p      "
1300 		"stream[%d].vcp_id: %d      "
1301 		"stream[%d].slot_count: %d\n",
1302 		i,
1303 		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
1304 		i,
1305 		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
1306 		i,
1307 		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
1308 		i,
1309 		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
1310 	}
1311 
1312 	if (link_hwss->ext.update_stream_allocation_table == NULL ||
1313 			link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
1314 		DC_LOG_DEBUG("Unknown encoding format\n");
1315 		return DC_ERROR_UNEXPECTED;
1316 	}
1317 
1318 	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
1319 			&link->mst_stream_alloc_table);
1320 
1321 	if (mst_mode) {
1322 		dm_helpers_dp_mst_poll_for_allocation_change_trigger(
1323 			stream->ctx,
1324 			stream);
1325 	}
1326 
1327 	dm_helpers_dp_mst_send_payload_allocation(
1328 			stream->ctx,
1329 			stream,
1330 			false);
1331 
1332 	return DC_OK;
1333 }
1334 
1335 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
1336 {
1337 	struct dc_stream_state *stream = pipe_ctx->stream;
1338 	struct dc_link *link = stream->link;
1339 	struct dc_dp_mst_stream_allocation_table proposed_table = {0};
1340 	struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
1341 	int i;
1342 	bool mst_mode = (link->type == dc_connection_mst_branch);
1343 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1344 	const struct dc_link_settings empty_link_settings = {0};
1345 	DC_LOGGER_INIT(link->ctx->logger);
1346 
1347 	if (link->dc->debug.temp_mst_deallocation_sequence)
1348 		return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx);
1349 
1350 	/* deallocate_mst_payload is called before disable link. When mode or
1351 	 * disable/enable monitor, new stream is created which is not in link
1352 	 * stream[] yet. For this, payload is not allocated yet, so de-alloc
1353 	 * should not done. For new mode set, map_resources will get engine
1354 	 * for new stream, so stream_enc->id should be validated until here.
1355 	 */
1356 
1357 	/* slot X.Y */
1358 	if (link_hwss->ext.set_throttled_vcp_size)
1359 		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
1360 	if (link_hwss->ext.set_hblank_min_symbol_width)
1361 		link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1362 				&empty_link_settings,
1363 				avg_time_slots_per_mtp);
1364 
1365 	if (mst_mode) {
1366 		/* when link is in mst mode, reply on mst manager to remove
1367 		 * payload
1368 		 */
1369 		if (dm_helpers_dp_mst_write_payload_allocation_table(
1370 				stream->ctx,
1371 				stream,
1372 				&proposed_table,
1373 				false))
1374 			update_mst_stream_alloc_table(
1375 					link,
1376 					pipe_ctx->stream_res.stream_enc,
1377 					pipe_ctx->stream_res.hpo_dp_stream_enc,
1378 					&proposed_table);
1379 		else
1380 			DC_LOG_WARNING("Failed to update"
1381 					"MST allocation table for"
1382 					"pipe idx:%d\n",
1383 					pipe_ctx->pipe_idx);
1384 	} else {
1385 		/* when link is no longer in mst mode (mst hub unplugged),
1386 		 * remove payload with default dc logic
1387 		 */
1388 		remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,
1389 				pipe_ctx->stream_res.hpo_dp_stream_enc);
1390 	}
1391 
1392 	DC_LOG_MST("%s"
1393 			"stream_count: %d: ",
1394 			__func__,
1395 			link->mst_stream_alloc_table.stream_count);
1396 
1397 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
1398 		DC_LOG_MST("stream_enc[%d]: %p      "
1399 		"stream[%d].hpo_dp_stream_enc: %p      "
1400 		"stream[%d].vcp_id: %d      "
1401 		"stream[%d].slot_count: %d\n",
1402 		i,
1403 		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
1404 		i,
1405 		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
1406 		i,
1407 		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
1408 		i,
1409 		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
1410 	}
1411 
1412 	/* update mst stream allocation table hardware state */
1413 	if (link_hwss->ext.update_stream_allocation_table == NULL ||
1414 			link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
1415 		DC_LOG_DEBUG("Unknown encoding format\n");
1416 		return DC_ERROR_UNEXPECTED;
1417 	}
1418 
1419 	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
1420 			&link->mst_stream_alloc_table);
1421 
1422 	if (mst_mode) {
1423 		dm_helpers_dp_mst_poll_for_allocation_change_trigger(
1424 			stream->ctx,
1425 			stream);
1426 
1427 		dm_helpers_dp_mst_send_payload_allocation(
1428 				stream->ctx,
1429 				stream,
1430 				false);
1431 	}
1432 
1433 	return DC_OK;
1434 }
1435 
1436 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
1437  * because stream_encoder is not exposed to dm
1438  */
1439 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
1440 {
1441 	struct dc_stream_state *stream = pipe_ctx->stream;
1442 	struct dc_link *link = stream->link;
1443 	struct dc_dp_mst_stream_allocation_table proposed_table = {0};
1444 	struct fixed31_32 avg_time_slots_per_mtp;
1445 	struct fixed31_32 pbn;
1446 	struct fixed31_32 pbn_per_slot;
1447 	int i;
1448 	enum act_return_status ret;
1449 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1450 	DC_LOGGER_INIT(link->ctx->logger);
1451 
1452 	/* enable_link_dp_mst already check link->enabled_stream_count
1453 	 * and stream is in link->stream[]. This is called during set mode,
1454 	 * stream_enc is available.
1455 	 */
1456 
1457 	/* get calculate VC payload for stream: stream_alloc */
1458 	if (dm_helpers_dp_mst_write_payload_allocation_table(
1459 		stream->ctx,
1460 		stream,
1461 		&proposed_table,
1462 		true))
1463 		update_mst_stream_alloc_table(
1464 					link,
1465 					pipe_ctx->stream_res.stream_enc,
1466 					pipe_ctx->stream_res.hpo_dp_stream_enc,
1467 					&proposed_table);
1468 	else
1469 		DC_LOG_WARNING("Failed to update"
1470 				"MST allocation table for"
1471 				"pipe idx:%d\n",
1472 				pipe_ctx->pipe_idx);
1473 
1474 	DC_LOG_MST("%s  "
1475 			"stream_count: %d: \n ",
1476 			__func__,
1477 			link->mst_stream_alloc_table.stream_count);
1478 
1479 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
1480 		DC_LOG_MST("stream_enc[%d]: %p      "
1481 		"stream[%d].hpo_dp_stream_enc: %p      "
1482 		"stream[%d].vcp_id: %d      "
1483 		"stream[%d].slot_count: %d\n",
1484 		i,
1485 		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
1486 		i,
1487 		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
1488 		i,
1489 		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
1490 		i,
1491 		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
1492 	}
1493 
1494 	ASSERT(proposed_table.stream_count > 0);
1495 
1496 	/* program DP source TX for payload */
1497 	if (link_hwss->ext.update_stream_allocation_table == NULL ||
1498 			link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
1499 		DC_LOG_ERROR("Failure: unknown encoding format\n");
1500 		return DC_ERROR_UNEXPECTED;
1501 	}
1502 
1503 	link_hwss->ext.update_stream_allocation_table(link,
1504 			&pipe_ctx->link_res,
1505 			&link->mst_stream_alloc_table);
1506 
1507 	/* send down message */
1508 	ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
1509 			stream->ctx,
1510 			stream);
1511 
1512 	if (ret != ACT_LINK_LOST) {
1513 		dm_helpers_dp_mst_send_payload_allocation(
1514 				stream->ctx,
1515 				stream,
1516 				true);
1517 	}
1518 
1519 	/* slot X.Y for only current stream */
1520 	pbn_per_slot = get_pbn_per_slot(stream);
1521 	if (pbn_per_slot.value == 0) {
1522 		DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
1523 		return DC_UNSUPPORTED_VALUE;
1524 	}
1525 	pbn = get_pbn_from_timing(pipe_ctx);
1526 	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
1527 
1528 	log_vcp_x_y(link, avg_time_slots_per_mtp);
1529 
1530 	if (link_hwss->ext.set_throttled_vcp_size)
1531 		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
1532 	if (link_hwss->ext.set_hblank_min_symbol_width)
1533 		link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1534 				&link->cur_link_settings,
1535 				avg_time_slots_per_mtp);
1536 
1537 	return DC_OK;
1538 }
1539 
1540 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp(
1541 		const struct dc_stream_state *stream,
1542 		const struct dc_link *link)
1543 {
1544 	struct fixed31_32 link_bw_effective =
1545 			dc_fixpt_from_int(
1546 					dp_link_bandwidth_kbps(link, &link->cur_link_settings));
1547 	struct fixed31_32 timeslot_bw_effective =
1548 			dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT);
1549 	struct fixed31_32 timing_bw =
1550 			dc_fixpt_from_int(
1551 					dc_bandwidth_in_kbps_from_timing(&stream->timing,
1552 							dc_link_get_highest_encoding_format(link)));
1553 	struct fixed31_32 avg_time_slots_per_mtp =
1554 			dc_fixpt_div(timing_bw, timeslot_bw_effective);
1555 
1556 	return avg_time_slots_per_mtp;
1557 }
1558 
1559 
1560 static bool write_128b_132b_sst_payload_allocation_table(
1561 		const struct dc_stream_state *stream,
1562 		struct dc_link *link,
1563 		struct link_mst_stream_allocation_table *proposed_table,
1564 		bool allocate)
1565 {
1566 	const uint8_t vc_id = 1; /// VC ID always 1 for SST
1567 	const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST
1568 	bool result = false;
1569 	uint8_t req_slot_count = 0;
1570 	struct fixed31_32 avg_time_slots_per_mtp = { 0 };
1571 	union payload_table_update_status update_status = { 0 };
1572 	const uint32_t max_retries = 30;
1573 	uint32_t retries = 0;
1574 	DC_LOGGER_INIT(link->ctx->logger);
1575 
1576 	if (allocate)	{
1577 		avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link);
1578 		req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
1579 		/// Validation should filter out modes that exceed link BW
1580 		ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
1581 		if (req_slot_count > MAX_MTP_SLOT_COUNT)
1582 			return false;
1583 	} else {
1584 		/// Leave req_slot_count = 0 if allocate is false.
1585 	}
1586 
1587 	proposed_table->stream_count = 1; /// Always 1 stream for SST
1588 	proposed_table->stream_allocations[0].slot_count = req_slot_count;
1589 	proposed_table->stream_allocations[0].vcp_id = vc_id;
1590 
1591 	if (link->aux_access_disabled)
1592 		return true;
1593 
1594 	/// Write DPCD 2C0 = 1 to start updating
1595 	update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;
1596 	core_link_write_dpcd(
1597 			link,
1598 			DP_PAYLOAD_TABLE_UPDATE_STATUS,
1599 			&update_status.raw,
1600 			1);
1601 
1602 	/// Program the changes in DPCD 1C0 - 1C2
1603 	ASSERT(vc_id == 1);
1604 	core_link_write_dpcd(
1605 			link,
1606 			DP_PAYLOAD_ALLOCATE_SET,
1607 			&vc_id,
1608 			1);
1609 
1610 	ASSERT(start_time_slot == 0);
1611 	core_link_write_dpcd(
1612 			link,
1613 			DP_PAYLOAD_ALLOCATE_START_TIME_SLOT,
1614 			&start_time_slot,
1615 			1);
1616 
1617 	core_link_write_dpcd(
1618 			link,
1619 			DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT,
1620 			&req_slot_count,
1621 			1);
1622 
1623 	/// Poll till DPCD 2C0 read 1
1624 	/// Try for at least 150ms (30 retries, with 5ms delay after each attempt)
1625 
1626 	while (retries < max_retries) {
1627 		if (core_link_read_dpcd(
1628 				link,
1629 				DP_PAYLOAD_TABLE_UPDATE_STATUS,
1630 				&update_status.raw,
1631 				1) == DC_OK) {
1632 			if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) {
1633 				DC_LOG_DP2("SST Update Payload: downstream payload table updated.");
1634 				result = true;
1635 				break;
1636 			}
1637 		} else {
1638 			union dpcd_rev dpcdRev;
1639 
1640 			if (core_link_read_dpcd(
1641 					link,
1642 					DP_DPCD_REV,
1643 					&dpcdRev.raw,
1644 					1) != DC_OK) {
1645 				DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision "
1646 						"of sink while polling payload table "
1647 						"updated status bit.");
1648 				break;
1649 			}
1650 		}
1651 		retries++;
1652 		fsleep(5000);
1653 	}
1654 
1655 	if (!result && retries == max_retries) {
1656 		DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, "
1657 				"continue on. Something is wrong with the branch.");
1658 		// TODO - DP2.0 Payload: Read and log the payload table from downstream branch
1659 	}
1660 
1661 	return result;
1662 }
1663 
1664 /*
1665  * Payload allocation/deallocation for SST introduced in DP2.0
1666  */
1667 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx,
1668 						 bool allocate)
1669 {
1670 	struct dc_stream_state *stream = pipe_ctx->stream;
1671 	struct dc_link *link = stream->link;
1672 	struct link_mst_stream_allocation_table proposed_table = {0};
1673 	struct fixed31_32 avg_time_slots_per_mtp;
1674 	const struct dc_link_settings empty_link_settings = {0};
1675 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1676 	DC_LOGGER_INIT(link->ctx->logger);
1677 
1678 	/* slot X.Y for SST payload deallocate */
1679 	if (!allocate) {
1680 		avg_time_slots_per_mtp = dc_fixpt_from_int(0);
1681 
1682 		log_vcp_x_y(link, avg_time_slots_per_mtp);
1683 
1684 		if (link_hwss->ext.set_throttled_vcp_size)
1685 			link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
1686 					avg_time_slots_per_mtp);
1687 		if (link_hwss->ext.set_hblank_min_symbol_width)
1688 			link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1689 					&empty_link_settings,
1690 					avg_time_slots_per_mtp);
1691 	}
1692 
1693 	/* calculate VC payload and update branch with new payload allocation table*/
1694 	if (!write_128b_132b_sst_payload_allocation_table(
1695 			stream,
1696 			link,
1697 			&proposed_table,
1698 			allocate)) {
1699 		DC_LOG_ERROR("SST Update Payload: Failed to update "
1700 						"allocation table for "
1701 						"pipe idx: %d\n",
1702 						pipe_ctx->pipe_idx);
1703 		return DC_FAIL_DP_PAYLOAD_ALLOCATION;
1704 	}
1705 
1706 	proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
1707 
1708 	ASSERT(proposed_table.stream_count == 1);
1709 
1710 	//TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
1711 	DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
1712 		"vcp_id: %d      "
1713 		"slot_count: %d\n",
1714 		(void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
1715 		proposed_table.stream_allocations[0].vcp_id,
1716 		proposed_table.stream_allocations[0].slot_count);
1717 
1718 	/* program DP source TX for payload */
1719 	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
1720 			&proposed_table);
1721 
1722 	/* poll for ACT handled */
1723 	if (!poll_for_allocation_change_trigger(link)) {
1724 		// Failures will result in blackscreen and errors logged
1725 		BREAK_TO_DEBUGGER();
1726 	}
1727 
1728 	/* slot X.Y for SST payload allocate */
1729 	if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) ==
1730 			DP_128b_132b_ENCODING) {
1731 		avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link);
1732 
1733 		log_vcp_x_y(link, avg_time_slots_per_mtp);
1734 
1735 		if (link_hwss->ext.set_throttled_vcp_size)
1736 			link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
1737 					avg_time_slots_per_mtp);
1738 		if (link_hwss->ext.set_hblank_min_symbol_width)
1739 			link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1740 					&link->cur_link_settings,
1741 					avg_time_slots_per_mtp);
1742 	}
1743 
1744 	/* Always return DC_OK.
1745 	 * If part of sequence fails, log failure(s) and show blackscreen
1746 	 */
1747 	return DC_OK;
1748 }
1749 
1750 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
1751 {
1752 	struct dc_stream_state *stream = pipe_ctx->stream;
1753 	struct dc_link *link = stream->link;
1754 	struct fixed31_32 avg_time_slots_per_mtp;
1755 	struct fixed31_32 pbn;
1756 	struct fixed31_32 pbn_per_slot;
1757 	struct dc_dp_mst_stream_allocation_table proposed_table = {0};
1758 	uint8_t i;
1759 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1760 	DC_LOGGER_INIT(link->ctx->logger);
1761 
1762 	/* decrease throttled vcp size */
1763 	pbn_per_slot = get_pbn_per_slot(stream);
1764 	pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
1765 	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
1766 
1767 	if (link_hwss->ext.set_throttled_vcp_size)
1768 		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
1769 	if (link_hwss->ext.set_hblank_min_symbol_width)
1770 		link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1771 				&link->cur_link_settings,
1772 				avg_time_slots_per_mtp);
1773 
1774 	/* send ALLOCATE_PAYLOAD sideband message with updated pbn */
1775 	dm_helpers_dp_mst_send_payload_allocation(
1776 			stream->ctx,
1777 			stream,
1778 			true);
1779 
1780 	/* notify immediate branch device table update */
1781 	if (dm_helpers_dp_mst_write_payload_allocation_table(
1782 			stream->ctx,
1783 			stream,
1784 			&proposed_table,
1785 			true)) {
1786 		/* update mst stream allocation table software state */
1787 		update_mst_stream_alloc_table(
1788 				link,
1789 				pipe_ctx->stream_res.stream_enc,
1790 				pipe_ctx->stream_res.hpo_dp_stream_enc,
1791 				&proposed_table);
1792 	} else {
1793 		DC_LOG_WARNING("Failed to update"
1794 				"MST allocation table for"
1795 				"pipe idx:%d\n",
1796 				pipe_ctx->pipe_idx);
1797 	}
1798 
1799 	DC_LOG_MST("%s  "
1800 			"stream_count: %d: \n ",
1801 			__func__,
1802 			link->mst_stream_alloc_table.stream_count);
1803 
1804 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
1805 		DC_LOG_MST("stream_enc[%d]: %p      "
1806 		"stream[%d].hpo_dp_stream_enc: %p      "
1807 		"stream[%d].vcp_id: %d      "
1808 		"stream[%d].slot_count: %d\n",
1809 		i,
1810 		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
1811 		i,
1812 		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
1813 		i,
1814 		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
1815 		i,
1816 		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
1817 	}
1818 
1819 	ASSERT(proposed_table.stream_count > 0);
1820 
1821 	/* update mst stream allocation table hardware state */
1822 	if (link_hwss->ext.update_stream_allocation_table == NULL ||
1823 			link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
1824 		DC_LOG_ERROR("Failure: unknown encoding format\n");
1825 		return DC_ERROR_UNEXPECTED;
1826 	}
1827 
1828 	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
1829 			&link->mst_stream_alloc_table);
1830 
1831 	/* poll for immediate branch device ACT handled */
1832 	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
1833 			stream->ctx,
1834 			stream);
1835 
1836 	return DC_OK;
1837 }
1838 
1839 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
1840 {
1841 	struct dc_stream_state *stream = pipe_ctx->stream;
1842 	struct dc_link *link = stream->link;
1843 	struct fixed31_32 avg_time_slots_per_mtp;
1844 	struct fixed31_32 pbn;
1845 	struct fixed31_32 pbn_per_slot;
1846 	struct dc_dp_mst_stream_allocation_table proposed_table = {0};
1847 	uint8_t i;
1848 	enum act_return_status ret;
1849 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1850 	DC_LOGGER_INIT(link->ctx->logger);
1851 
1852 	/* notify immediate branch device table update */
1853 	if (dm_helpers_dp_mst_write_payload_allocation_table(
1854 				stream->ctx,
1855 				stream,
1856 				&proposed_table,
1857 				true)) {
1858 		/* update mst stream allocation table software state */
1859 		update_mst_stream_alloc_table(
1860 				link,
1861 				pipe_ctx->stream_res.stream_enc,
1862 				pipe_ctx->stream_res.hpo_dp_stream_enc,
1863 				&proposed_table);
1864 	}
1865 
1866 	DC_LOG_MST("%s  "
1867 			"stream_count: %d: \n ",
1868 			__func__,
1869 			link->mst_stream_alloc_table.stream_count);
1870 
1871 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
1872 		DC_LOG_MST("stream_enc[%d]: %p      "
1873 		"stream[%d].hpo_dp_stream_enc: %p      "
1874 		"stream[%d].vcp_id: %d      "
1875 		"stream[%d].slot_count: %d\n",
1876 		i,
1877 		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
1878 		i,
1879 		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
1880 		i,
1881 		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
1882 		i,
1883 		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
1884 	}
1885 
1886 	ASSERT(proposed_table.stream_count > 0);
1887 
1888 	/* update mst stream allocation table hardware state */
1889 	if (link_hwss->ext.update_stream_allocation_table == NULL ||
1890 			link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
1891 		DC_LOG_ERROR("Failure: unknown encoding format\n");
1892 		return DC_ERROR_UNEXPECTED;
1893 	}
1894 
1895 	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
1896 			&link->mst_stream_alloc_table);
1897 
1898 	/* poll for immediate branch device ACT handled */
1899 	ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
1900 			stream->ctx,
1901 			stream);
1902 
1903 	if (ret != ACT_LINK_LOST) {
1904 		/* send ALLOCATE_PAYLOAD sideband message with updated pbn */
1905 		dm_helpers_dp_mst_send_payload_allocation(
1906 				stream->ctx,
1907 				stream,
1908 				true);
1909 	}
1910 
1911 	/* increase throttled vcp size */
1912 	pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
1913 	pbn_per_slot = get_pbn_per_slot(stream);
1914 	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
1915 
1916 	if (link_hwss->ext.set_throttled_vcp_size)
1917 		link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
1918 	if (link_hwss->ext.set_hblank_min_symbol_width)
1919 		link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
1920 				&link->cur_link_settings,
1921 				avg_time_slots_per_mtp);
1922 
1923 	return DC_OK;
1924 }
1925 
1926 static void disable_link_dp(struct dc_link *link,
1927 		const struct link_resource *link_res,
1928 		enum signal_type signal)
1929 {
1930 	struct dc_link_settings link_settings = link->cur_link_settings;
1931 
1932 	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST &&
1933 			link->mst_stream_alloc_table.stream_count > 0)
1934 		/* disable MST link only when last vc payload is deallocated */
1935 		return;
1936 
1937 	dp_disable_link_phy(link, link_res, signal);
1938 
1939 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
1940 		if (!link->skip_implict_edp_power_control)
1941 			link->dc->hwss.edp_power_control(link, false);
1942 	}
1943 
1944 	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1945 		/* set the sink to SST mode after disabling the link */
1946 		enable_mst_on_sink(link, false);
1947 
1948 	if (link_dp_get_encoding_format(&link_settings) ==
1949 			DP_8b_10b_ENCODING) {
1950 		dp_set_fec_enable(link, false);
1951 		dp_set_fec_ready(link, link_res, false);
1952 	}
1953 }
1954 
1955 static void disable_link(struct dc_link *link,
1956 		const struct link_resource *link_res,
1957 		enum signal_type signal)
1958 {
1959 	if (dc_is_dp_signal(signal)) {
1960 		disable_link_dp(link, link_res, signal);
1961 	} else if (signal != SIGNAL_TYPE_VIRTUAL) {
1962 		link->dc->hwss.disable_link_output(link, link_res, signal);
1963 	}
1964 
1965 	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1966 		/* MST disable link only when no stream use the link */
1967 		if (link->mst_stream_alloc_table.stream_count <= 0)
1968 			link->link_status.link_active = false;
1969 	} else {
1970 		link->link_status.link_active = false;
1971 	}
1972 }
1973 
1974 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1975 {
1976 	struct dc_stream_state *stream = pipe_ctx->stream;
1977 	struct dc_link *link = stream->link;
1978 	enum dc_color_depth display_color_depth;
1979 	enum engine_id eng_id;
1980 	struct ext_hdmi_settings settings = {0};
1981 	bool is_over_340mhz = false;
1982 	bool is_vga_mode = (stream->timing.h_addressable == 640)
1983 			&& (stream->timing.v_addressable == 480);
1984 	struct dc *dc = pipe_ctx->stream->ctx->dc;
1985 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1986 
1987 	if (stream->phy_pix_clk == 0)
1988 		stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
1989 	if (stream->phy_pix_clk > 340000)
1990 		is_over_340mhz = true;
1991 
1992 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1993 		unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
1994 				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1995 		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1996 			/* DP159, Retimer settings */
1997 			eng_id = pipe_ctx->stream_res.stream_enc->id;
1998 
1999 			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2000 				write_i2c_retimer_setting(pipe_ctx,
2001 						is_vga_mode, is_over_340mhz, &settings);
2002 			} else {
2003 				write_i2c_default_retimer_setting(pipe_ctx,
2004 						is_vga_mode, is_over_340mhz);
2005 			}
2006 		} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2007 			/* PI3EQX1204, Redriver settings */
2008 			write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2009 		}
2010 	}
2011 
2012 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2013 		write_scdc_data(
2014 			stream->link->ddc,
2015 			stream->phy_pix_clk,
2016 			stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2017 
2018 	memset(&stream->link->cur_link_settings, 0,
2019 			sizeof(struct dc_link_settings));
2020 
2021 	display_color_depth = stream->timing.display_color_depth;
2022 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2023 		display_color_depth = COLOR_DEPTH_888;
2024 
2025 	/* We need to enable stream encoder for TMDS first to apply 1/4 TMDS
2026 	 * character clock in case that beyond 340MHz.
2027 	 */
2028 	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2029 		link_hwss->setup_stream_encoder(pipe_ctx);
2030 
2031 	dc->hwss.enable_tmds_link_output(
2032 			link,
2033 			&pipe_ctx->link_res,
2034 			pipe_ctx->stream->signal,
2035 			pipe_ctx->clock_source->id,
2036 			display_color_depth,
2037 			stream->phy_pix_clk);
2038 
2039 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2040 		read_scdc_data(link->ddc);
2041 }
2042 
2043 static enum dc_status enable_link_dp(struct dc_state *state,
2044 				     struct pipe_ctx *pipe_ctx)
2045 {
2046 	struct dc_stream_state *stream = pipe_ctx->stream;
2047 	enum dc_status status;
2048 	bool skip_video_pattern;
2049 	struct dc_link *link = stream->link;
2050 	const struct dc_link_settings *link_settings =
2051 			&pipe_ctx->link_config.dp_link_settings;
2052 	bool fec_enable;
2053 	int i;
2054 	bool apply_seamless_boot_optimization = false;
2055 	uint32_t bl_oled_enable_delay = 50; // in ms
2056 	uint32_t post_oui_delay = 30; // 30ms
2057 	/* Reduce link bandwidth between failed link training attempts. */
2058 	bool do_fallback = false;
2059 	int lt_attempts = LINK_TRAINING_ATTEMPTS;
2060 
2061 	// Increase retry count if attempting DP1.x on FIXED_VS link
2062 	if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
2063 			link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2064 		lt_attempts = 10;
2065 
2066 	// check for seamless boot
2067 	for (i = 0; i < state->stream_count; i++) {
2068 		if (state->streams[i]->apply_seamless_boot_optimization) {
2069 			apply_seamless_boot_optimization = true;
2070 			break;
2071 		}
2072 	}
2073 
2074 	/*
2075 	 * If the link is DP-over-USB4 do the following:
2076 	 * - Train with fallback when enabling DPIA link. Conventional links are
2077 	 * trained with fallback during sink detection.
2078 	 * - Allocate only what the stream needs for bw in Gbps. Inform the CM
2079 	 * in case stream needs more or less bw from what has been allocated
2080 	 * earlier at plug time.
2081 	 */
2082 	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
2083 		do_fallback = true;
2084 	}
2085 
2086 	/*
2087 	 * Temporary w/a to get DP2.0 link rates to work with SST.
2088 	 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
2089 	 */
2090 	if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
2091 			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2092 			link->dc->debug.set_mst_en_for_sst) {
2093 		enable_mst_on_sink(link, true);
2094 	}
2095 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2096 		/*in case it is not on*/
2097 		if (!link->dc->config.edp_no_power_sequencing)
2098 			link->dc->hwss.edp_power_control(link, true);
2099 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2100 	}
2101 
2102 	if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
2103 		/* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2104 	} else {
2105 		pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2106 				link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2107 		if (state->clk_mgr && !apply_seamless_boot_optimization)
2108 			state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2109 					state, false);
2110 	}
2111 
2112 	// during mode switch we do DP_SET_POWER off then on, and OUI is lost
2113 	dpcd_set_source_specific_data(link);
2114 	if (link->dpcd_sink_ext_caps.raw != 0) {
2115 		post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;
2116 		msleep(post_oui_delay);
2117 	}
2118 
2119 	// similarly, mode switch can cause loss of cable ID
2120 	dpcd_write_cable_id_to_dprx(link);
2121 
2122 	skip_video_pattern = true;
2123 
2124 	if (link_settings->link_rate == LINK_RATE_LOW)
2125 		skip_video_pattern = false;
2126 
2127 	if (perform_link_training_with_retries(link_settings,
2128 					       skip_video_pattern,
2129 					       lt_attempts,
2130 					       pipe_ctx,
2131 					       pipe_ctx->stream->signal,
2132 					       do_fallback)) {
2133 		status = DC_OK;
2134 	} else {
2135 		status = DC_FAIL_DP_LINK_TRAINING;
2136 	}
2137 
2138 	if (link->preferred_training_settings.fec_enable)
2139 		fec_enable = *link->preferred_training_settings.fec_enable;
2140 	else
2141 		fec_enable = true;
2142 
2143 	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2144 		dp_set_fec_enable(link, fec_enable);
2145 
2146 	// during mode set we do DP_SET_POWER off then on, aux writes are lost
2147 	if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2148 		link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2149 		link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2150 		set_default_brightness_aux(link);
2151 		if (link->dpcd_sink_ext_caps.bits.oled == 1)
2152 			msleep(bl_oled_enable_delay);
2153 		edp_backlight_enable_aux(link, true);
2154 	}
2155 
2156 	return status;
2157 }
2158 
2159 static enum dc_status enable_link_edp(
2160 		struct dc_state *state,
2161 		struct pipe_ctx *pipe_ctx)
2162 {
2163 	return enable_link_dp(state, pipe_ctx);
2164 }
2165 
2166 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2167 {
2168 	struct dc_stream_state *stream = pipe_ctx->stream;
2169 	struct dc_link *link = stream->link;
2170 	struct dc *dc = stream->ctx->dc;
2171 
2172 	if (stream->phy_pix_clk == 0)
2173 		stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2174 
2175 	memset(&stream->link->cur_link_settings, 0,
2176 			sizeof(struct dc_link_settings));
2177 	dc->hwss.enable_lvds_link_output(
2178 			link,
2179 			&pipe_ctx->link_res,
2180 			pipe_ctx->clock_source->id,
2181 			stream->phy_pix_clk);
2182 
2183 }
2184 
2185 static enum dc_status enable_link_dp_mst(
2186 		struct dc_state *state,
2187 		struct pipe_ctx *pipe_ctx)
2188 {
2189 	struct dc_link *link = pipe_ctx->stream->link;
2190 	unsigned char mstm_cntl;
2191 
2192 	/* sink signal type after MST branch is MST. Multiple MST sinks
2193 	 * share one link. Link DP PHY is enable or training only once.
2194 	 */
2195 	if (link->link_status.link_active)
2196 		return DC_OK;
2197 
2198 	/* clear payload table */
2199 	core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1);
2200 	if (mstm_cntl & DP_MST_EN)
2201 		dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2202 
2203 	/* to make sure the pending down rep can be processed
2204 	 * before enabling the link
2205 	 */
2206 	dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2207 
2208 	/* set the sink to MST mode before enabling the link */
2209 	enable_mst_on_sink(link, true);
2210 
2211 	return enable_link_dp(state, pipe_ctx);
2212 }
2213 
2214 static enum dc_status enable_link(
2215 		struct dc_state *state,
2216 		struct pipe_ctx *pipe_ctx)
2217 {
2218 	enum dc_status status = DC_ERROR_UNEXPECTED;
2219 	struct dc_stream_state *stream = pipe_ctx->stream;
2220 	struct dc_link *link = stream->link;
2221 
2222 	/* There's some scenarios where driver is unloaded with display
2223 	 * still enabled. When driver is reloaded, it may cause a display
2224 	 * to not light up if there is a mismatch between old and new
2225 	 * link settings. Need to call disable first before enabling at
2226 	 * new link settings.
2227 	 */
2228 	if (link->link_status.link_active)
2229 		disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2230 
2231 	switch (pipe_ctx->stream->signal) {
2232 	case SIGNAL_TYPE_DISPLAY_PORT:
2233 		status = enable_link_dp(state, pipe_ctx);
2234 		break;
2235 	case SIGNAL_TYPE_EDP:
2236 		status = enable_link_edp(state, pipe_ctx);
2237 		break;
2238 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
2239 		status = enable_link_dp_mst(state, pipe_ctx);
2240 		msleep(200);
2241 		break;
2242 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
2243 	case SIGNAL_TYPE_DVI_DUAL_LINK:
2244 	case SIGNAL_TYPE_HDMI_TYPE_A:
2245 		enable_link_hdmi(pipe_ctx);
2246 		status = DC_OK;
2247 		break;
2248 	case SIGNAL_TYPE_LVDS:
2249 		enable_link_lvds(pipe_ctx);
2250 		status = DC_OK;
2251 		break;
2252 	case SIGNAL_TYPE_VIRTUAL:
2253 		status = DC_OK;
2254 		break;
2255 	default:
2256 		break;
2257 	}
2258 
2259 	if (status == DC_OK) {
2260 		pipe_ctx->stream->link->link_status.link_active = true;
2261 	}
2262 
2263 	return status;
2264 }
2265 
2266 void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
2267 {
2268 	struct dc  *dc = pipe_ctx->stream->ctx->dc;
2269 	struct dc_stream_state *stream = pipe_ctx->stream;
2270 	struct dc_link *link = stream->sink->link;
2271 	struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
2272 
2273 	ASSERT(is_master_pipe_for_link(link, pipe_ctx));
2274 
2275 	if (dp_is_128b_132b_signal(pipe_ctx))
2276 		vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
2277 
2278 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2279 
2280 	if (pipe_ctx->stream->sink) {
2281 		if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
2282 			pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
2283 			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
2284 			pipe_ctx->stream->sink->edid_caps.display_name,
2285 			pipe_ctx->stream->signal);
2286 		}
2287 	}
2288 
2289 	if (dc_is_virtual_signal(pipe_ctx->stream->signal))
2290 		return;
2291 
2292 	if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
2293 		if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2294 			set_avmute(pipe_ctx, true);
2295 	}
2296 
2297 	dc->hwss.disable_audio_stream(pipe_ctx);
2298 
2299 	update_psp_stream_config(pipe_ctx, true);
2300 	dc->hwss.blank_stream(pipe_ctx);
2301 
2302 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2303 		deallocate_mst_payload(pipe_ctx);
2304 	else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2305 			dp_is_128b_132b_signal(pipe_ctx))
2306 		update_sst_payload(pipe_ctx, false);
2307 
2308 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2309 		struct ext_hdmi_settings settings = {0};
2310 		enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
2311 
2312 		unsigned short masked_chip_caps = link->chip_caps &
2313 				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2314 		//Need to inform that sink is going to use legacy HDMI mode.
2315 		write_scdc_data(
2316 			link->ddc,
2317 			165000,//vbios only handles 165Mhz.
2318 			false);
2319 		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2320 			/* DP159, Retimer settings */
2321 			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
2322 				write_i2c_retimer_setting(pipe_ctx,
2323 						false, false, &settings);
2324 			else
2325 				write_i2c_default_retimer_setting(pipe_ctx,
2326 						false, false);
2327 		} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2328 			/* PI3EQX1204, Redriver settings */
2329 			write_i2c_redriver_setting(pipe_ctx, false);
2330 		}
2331 	}
2332 
2333 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2334 			!dp_is_128b_132b_signal(pipe_ctx)) {
2335 
2336 		/* In DP1.x SST mode, our encoder will go to TPS1
2337 		 * when link is on but stream is off.
2338 		 * Disabling link before stream will avoid exposing TPS1 pattern
2339 		 * during the disable sequence as it will confuse some receivers
2340 		 * state machine.
2341 		 * In DP2 or MST mode, our encoder will stay video active
2342 		 */
2343 		disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2344 		dc->hwss.disable_stream(pipe_ctx);
2345 	} else {
2346 		dc->hwss.disable_stream(pipe_ctx);
2347 		disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2348 	}
2349 
2350 	if (pipe_ctx->stream->timing.flags.DSC) {
2351 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
2352 			link_set_dsc_enable(pipe_ctx, false);
2353 	}
2354 	if (dp_is_128b_132b_signal(pipe_ctx)) {
2355 		if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
2356 			pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
2357 	}
2358 
2359 	if (vpg && vpg->funcs->vpg_powerdown)
2360 		vpg->funcs->vpg_powerdown(vpg);
2361 }
2362 
2363 void link_set_dpms_on(
2364 		struct dc_state *state,
2365 		struct pipe_ctx *pipe_ctx)
2366 {
2367 	struct dc *dc = pipe_ctx->stream->ctx->dc;
2368 	struct dc_stream_state *stream = pipe_ctx->stream;
2369 	struct dc_link *link = stream->sink->link;
2370 	enum dc_status status;
2371 	struct link_encoder *link_enc;
2372 	enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
2373 	struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
2374 	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2375 	bool apply_edp_fast_boot_optimization =
2376 		pipe_ctx->stream->apply_edp_fast_boot_optimization;
2377 
2378 	ASSERT(is_master_pipe_for_link(link, pipe_ctx));
2379 
2380 	if (dp_is_128b_132b_signal(pipe_ctx))
2381 		vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
2382 
2383 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2384 
2385 	if (pipe_ctx->stream->sink) {
2386 		if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
2387 			pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
2388 			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
2389 			pipe_ctx->stream->sink->edid_caps.display_name,
2390 			pipe_ctx->stream->signal);
2391 		}
2392 	}
2393 
2394 	if (dc_is_virtual_signal(pipe_ctx->stream->signal))
2395 		return;
2396 
2397 	link_enc = link_enc_cfg_get_link_enc(link);
2398 	ASSERT(link_enc);
2399 
2400 	if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
2401 			&& !dp_is_128b_132b_signal(pipe_ctx)) {
2402 		if (link_enc)
2403 			link_enc->funcs->setup(
2404 				link_enc,
2405 				pipe_ctx->stream->signal);
2406 	}
2407 
2408 	pipe_ctx->stream->link->link_state_valid = true;
2409 
2410 	if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
2411 		if (dp_is_128b_132b_signal(pipe_ctx))
2412 			otg_out_dest = OUT_MUX_HPO_DP;
2413 		else
2414 			otg_out_dest = OUT_MUX_DIO;
2415 		pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
2416 	}
2417 
2418 	link_hwss->setup_stream_attribute(pipe_ctx);
2419 
2420 	pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2421 
2422 	// Enable VPG before building infoframe
2423 	if (vpg && vpg->funcs->vpg_poweron)
2424 		vpg->funcs->vpg_poweron(vpg);
2425 
2426 	resource_build_info_frame(pipe_ctx);
2427 	dc->hwss.update_info_frame(pipe_ctx);
2428 
2429 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
2430 		dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2431 
2432 	/* Do not touch link on seamless boot optimization. */
2433 	if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2434 		pipe_ctx->stream->dpms_off = false;
2435 
2436 		/* Still enable stream features & audio on seamless boot for DP external displays */
2437 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
2438 			enable_stream_features(pipe_ctx);
2439 			dc->hwss.enable_audio_stream(pipe_ctx);
2440 		}
2441 
2442 		update_psp_stream_config(pipe_ctx, false);
2443 		return;
2444 	}
2445 
2446 	/* eDP lit up by bios already, no need to enable again. */
2447 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2448 				apply_edp_fast_boot_optimization &&
2449 				!pipe_ctx->stream->timing.flags.DSC &&
2450 				!pipe_ctx->next_odm_pipe) {
2451 		pipe_ctx->stream->dpms_off = false;
2452 		update_psp_stream_config(pipe_ctx, false);
2453 		return;
2454 	}
2455 
2456 	if (pipe_ctx->stream->dpms_off)
2457 		return;
2458 
2459 	/* Have to setup DSC before DIG FE and BE are connected (which happens before the
2460 	 * link training). This is to make sure the bandwidth sent to DIG BE won't be
2461 	 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
2462 	 * will be automatically set at a later time when the video is enabled
2463 	 * (DP_VID_STREAM_EN = 1).
2464 	 */
2465 	if (pipe_ctx->stream->timing.flags.DSC) {
2466 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2467 			dc_is_virtual_signal(pipe_ctx->stream->signal))
2468 		link_set_dsc_enable(pipe_ctx, true);
2469 
2470 	}
2471 
2472 	status = enable_link(state, pipe_ctx);
2473 
2474 	if (status != DC_OK) {
2475 		DC_LOG_WARNING("enabling link %u failed: %d\n",
2476 		pipe_ctx->stream->link->link_index,
2477 		status);
2478 
2479 		/* Abort stream enable *unless* the failure was due to
2480 		 * DP link training - some DP monitors will recover and
2481 		 * show the stream anyway. But MST displays can't proceed
2482 		 * without link training.
2483 		 */
2484 		if (status != DC_FAIL_DP_LINK_TRAINING ||
2485 				pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2486 			if (false == stream->link->link_status.link_active)
2487 				disable_link(stream->link, &pipe_ctx->link_res,
2488 						pipe_ctx->stream->signal);
2489 			BREAK_TO_DEBUGGER();
2490 			return;
2491 		}
2492 	}
2493 
2494 	/* turn off otg test pattern if enable */
2495 	if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2496 		pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2497 				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2498 				COLOR_DEPTH_UNDEFINED);
2499 
2500 	/* This second call is needed to reconfigure the DIG
2501 	 * as a workaround for the incorrect value being applied
2502 	 * from transmitter control.
2503 	 */
2504 	if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
2505 			dp_is_128b_132b_signal(pipe_ctx))) {
2506 			if (link_enc)
2507 				link_enc->funcs->setup(
2508 					link_enc,
2509 					pipe_ctx->stream->signal);
2510 		}
2511 
2512 	dc->hwss.enable_stream(pipe_ctx);
2513 
2514 	/* Set DPS PPS SDP (AKA "info frames") */
2515 	if (pipe_ctx->stream->timing.flags.DSC) {
2516 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2517 				dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2518 			dp_set_dsc_on_rx(pipe_ctx, true);
2519 			link_set_dsc_pps_packet(pipe_ctx, true, true);
2520 		}
2521 	}
2522 
2523 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2524 		allocate_mst_payload(pipe_ctx);
2525 	else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2526 			dp_is_128b_132b_signal(pipe_ctx))
2527 		update_sst_payload(pipe_ctx, true);
2528 
2529 	dc->hwss.unblank_stream(pipe_ctx,
2530 		&pipe_ctx->stream->link->cur_link_settings);
2531 
2532 	if (stream->sink_patches.delay_ignore_msa > 0)
2533 		msleep(stream->sink_patches.delay_ignore_msa);
2534 
2535 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
2536 		enable_stream_features(pipe_ctx);
2537 	update_psp_stream_config(pipe_ctx, false);
2538 
2539 	dc->hwss.enable_audio_stream(pipe_ctx);
2540 
2541 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2542 		set_avmute(pipe_ctx, false);
2543 	}
2544 }
2545