1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "accessories/link_fpga.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #define DC_LOGGER_INIT(logger) 59 60 #define LINK_INFO(...) \ 61 DC_LOG_HW_HOTPLUG( \ 62 __VA_ARGS__) 63 64 #define RETIMER_REDRIVER_INFO(...) \ 65 DC_LOG_RETIMER_REDRIVER( \ 66 __VA_ARGS__) 67 #include "dc/dcn30/dcn30_vpg.h" 68 69 #define MAX_MTP_SLOT_COUNT 64 70 #define LINK_TRAINING_ATTEMPTS 4 71 #define PEAK_FACTOR_X1000 1006 72 73 void link_blank_all_dp_displays(struct dc *dc) 74 { 75 unsigned int i; 76 uint8_t dpcd_power_state = '\0'; 77 enum dc_status status = DC_ERROR_UNEXPECTED; 78 79 for (i = 0; i < dc->link_count; i++) { 80 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 81 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 82 continue; 83 84 /* DP 2.0 spec requires that we read LTTPR caps first */ 85 dp_retrieve_lttpr_cap(dc->links[i]); 86 /* if any of the displays are lit up turn them off */ 87 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 88 &dpcd_power_state, sizeof(dpcd_power_state)); 89 90 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 91 link_blank_dp_stream(dc->links[i], true); 92 } 93 94 } 95 96 void link_blank_all_edp_displays(struct dc *dc) 97 { 98 unsigned int i; 99 uint8_t dpcd_power_state = '\0'; 100 enum dc_status status = DC_ERROR_UNEXPECTED; 101 102 for (i = 0; i < dc->link_count; i++) { 103 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 104 (!dc->links[i]->edp_sink_present)) 105 continue; 106 107 /* if any of the displays are lit up turn them off */ 108 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 109 &dpcd_power_state, sizeof(dpcd_power_state)); 110 111 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 112 link_blank_dp_stream(dc->links[i], true); 113 } 114 } 115 116 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 117 { 118 unsigned int j; 119 struct dc *dc = link->ctx->dc; 120 enum signal_type signal = link->connector_signal; 121 122 if ((signal == SIGNAL_TYPE_EDP) || 123 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 124 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 125 link->link_enc->funcs->get_dig_frontend && 126 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 127 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 128 129 if (fe != ENGINE_ID_UNKNOWN) 130 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 131 if (fe == dc->res_pool->stream_enc[j]->id) { 132 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 133 dc->res_pool->stream_enc[j]); 134 break; 135 } 136 } 137 } 138 139 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 140 dpcd_write_rx_power_ctrl(link, false); 141 } 142 } 143 144 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 145 { 146 struct pipe_ctx *pipes[MAX_PIPES]; 147 struct dc_state *state = link->dc->current_state; 148 uint8_t count; 149 int i; 150 struct dc_stream_update stream_update; 151 bool dpms_off = true; 152 struct link_resource link_res = {0}; 153 154 memset(&stream_update, 0, sizeof(stream_update)); 155 stream_update.dpms_off = &dpms_off; 156 157 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 158 159 for (i = 0; i < count; i++) { 160 stream_update.stream = pipes[i]->stream; 161 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 162 pipes[i]->stream, &stream_update, 163 state); 164 } 165 166 /* link can be also enabled by vbios. In this case it is not recorded 167 * in pipe_ctx. Disable link phy here to make sure it is completely off 168 */ 169 dp_disable_link_phy(link, &link_res, link->connector_signal); 170 } 171 172 void link_resume(struct dc_link *link) 173 { 174 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 175 program_hpd_filter(link); 176 } 177 178 /* This function returns true if the pipe is used to feed video signal directly 179 * to the link. 180 */ 181 static bool is_master_pipe_for_link(const struct dc_link *link, 182 const struct pipe_ctx *pipe) 183 { 184 return (pipe->stream && 185 pipe->stream->link && 186 pipe->stream->link == link && 187 pipe->top_pipe == NULL && 188 pipe->prev_odm_pipe == NULL); 189 } 190 191 /* 192 * This function finds all master pipes feeding to a given link with dpms set to 193 * on in given dc state. 194 */ 195 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 196 struct dc_state *state, 197 uint8_t *count, 198 struct pipe_ctx *pipes[MAX_PIPES]) 199 { 200 int i; 201 struct pipe_ctx *pipe = NULL; 202 203 *count = 0; 204 for (i = 0; i < MAX_PIPES; i++) { 205 pipe = &state->res_ctx.pipe_ctx[i]; 206 207 if (is_master_pipe_for_link(link, pipe) && 208 pipe->stream->dpms_off == false) { 209 pipes[(*count)++] = pipe; 210 } 211 } 212 } 213 214 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 215 enum engine_id eng_id, 216 struct ext_hdmi_settings *settings) 217 { 218 bool result = false; 219 int i = 0; 220 struct integrated_info *integrated_info = 221 pipe_ctx->stream->ctx->dc_bios->integrated_info; 222 223 if (integrated_info == NULL) 224 return false; 225 226 /* 227 * Get retimer settings from sbios for passing SI eye test for DCE11 228 * The setting values are varied based on board revision and port id 229 * Therefore the setting values of each ports is passed by sbios. 230 */ 231 232 // Check if current bios contains ext Hdmi settings 233 if (integrated_info->gpu_cap_info & 0x20) { 234 switch (eng_id) { 235 case ENGINE_ID_DIGA: 236 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 237 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 238 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 memmove(settings->reg_settings, 240 integrated_info->dp0_ext_hdmi_reg_settings, 241 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 242 memmove(settings->reg_settings_6g, 243 integrated_info->dp0_ext_hdmi_6g_reg_settings, 244 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 245 result = true; 246 break; 247 case ENGINE_ID_DIGB: 248 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 249 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 250 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 memmove(settings->reg_settings, 252 integrated_info->dp1_ext_hdmi_reg_settings, 253 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 254 memmove(settings->reg_settings_6g, 255 integrated_info->dp1_ext_hdmi_6g_reg_settings, 256 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 257 result = true; 258 break; 259 case ENGINE_ID_DIGC: 260 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 261 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 262 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 memmove(settings->reg_settings, 264 integrated_info->dp2_ext_hdmi_reg_settings, 265 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 266 memmove(settings->reg_settings_6g, 267 integrated_info->dp2_ext_hdmi_6g_reg_settings, 268 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 269 result = true; 270 break; 271 case ENGINE_ID_DIGD: 272 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 273 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 274 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 memmove(settings->reg_settings, 276 integrated_info->dp3_ext_hdmi_reg_settings, 277 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 278 memmove(settings->reg_settings_6g, 279 integrated_info->dp3_ext_hdmi_6g_reg_settings, 280 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 281 result = true; 282 break; 283 default: 284 break; 285 } 286 287 if (result == true) { 288 // Validate settings from bios integrated info table 289 if (settings->slv_addr == 0) 290 return false; 291 if (settings->reg_num > 9) 292 return false; 293 if (settings->reg_num_6g > 3) 294 return false; 295 296 for (i = 0; i < settings->reg_num; i++) { 297 if (settings->reg_settings[i].i2c_reg_index > 0x20) 298 return false; 299 } 300 301 for (i = 0; i < settings->reg_num_6g; i++) { 302 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 303 return false; 304 } 305 } 306 } 307 308 return result; 309 } 310 311 static bool write_i2c(struct pipe_ctx *pipe_ctx, 312 uint8_t address, uint8_t *buffer, uint32_t length) 313 { 314 struct i2c_command cmd = {0}; 315 struct i2c_payload payload = {0}; 316 317 memset(&payload, 0, sizeof(payload)); 318 memset(&cmd, 0, sizeof(cmd)); 319 320 cmd.number_of_payloads = 1; 321 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 322 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 323 324 payload.address = address; 325 payload.data = buffer; 326 payload.length = length; 327 payload.write = true; 328 cmd.payloads = &payload; 329 330 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 331 pipe_ctx->stream->link, &cmd)) 332 return true; 333 334 return false; 335 } 336 337 static void write_i2c_retimer_setting( 338 struct pipe_ctx *pipe_ctx, 339 bool is_vga_mode, 340 bool is_over_340mhz, 341 struct ext_hdmi_settings *settings) 342 { 343 uint8_t slave_address = (settings->slv_addr >> 1); 344 uint8_t buffer[2]; 345 const uint8_t apply_rx_tx_change = 0x4; 346 uint8_t offset = 0xA; 347 uint8_t value = 0; 348 int i = 0; 349 bool i2c_success = false; 350 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 351 352 memset(&buffer, 0, sizeof(buffer)); 353 354 /* Start Ext-Hdmi programming*/ 355 356 for (i = 0; i < settings->reg_num; i++) { 357 /* Apply 3G settings */ 358 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 359 360 buffer[0] = settings->reg_settings[i].i2c_reg_index; 361 buffer[1] = settings->reg_settings[i].i2c_reg_val; 362 i2c_success = write_i2c(pipe_ctx, slave_address, 363 buffer, sizeof(buffer)); 364 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 365 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 366 slave_address, buffer[0], buffer[1], i2c_success?1:0); 367 368 if (!i2c_success) 369 goto i2c_write_fail; 370 371 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 372 * needs to be set to 1 on every 0xA-0xC write. 373 */ 374 if (settings->reg_settings[i].i2c_reg_index == 0xA || 375 settings->reg_settings[i].i2c_reg_index == 0xB || 376 settings->reg_settings[i].i2c_reg_index == 0xC) { 377 378 /* Query current value from offset 0xA */ 379 if (settings->reg_settings[i].i2c_reg_index == 0xA) 380 value = settings->reg_settings[i].i2c_reg_val; 381 else { 382 i2c_success = 383 link_query_ddc_data( 384 pipe_ctx->stream->link->ddc, 385 slave_address, &offset, 1, &value, 1); 386 if (!i2c_success) 387 goto i2c_write_fail; 388 } 389 390 buffer[0] = offset; 391 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 392 buffer[1] = value | apply_rx_tx_change; 393 i2c_success = write_i2c(pipe_ctx, slave_address, 394 buffer, sizeof(buffer)); 395 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 396 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 397 slave_address, buffer[0], buffer[1], i2c_success?1:0); 398 if (!i2c_success) 399 goto i2c_write_fail; 400 } 401 } 402 } 403 404 /* Apply 3G settings */ 405 if (is_over_340mhz) { 406 for (i = 0; i < settings->reg_num_6g; i++) { 407 /* Apply 3G settings */ 408 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 409 410 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 411 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 412 i2c_success = write_i2c(pipe_ctx, slave_address, 413 buffer, sizeof(buffer)); 414 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 415 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 416 slave_address, buffer[0], buffer[1], i2c_success?1:0); 417 418 if (!i2c_success) 419 goto i2c_write_fail; 420 421 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 422 * needs to be set to 1 on every 0xA-0xC write. 423 */ 424 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 425 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 427 428 /* Query current value from offset 0xA */ 429 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 430 value = settings->reg_settings_6g[i].i2c_reg_val; 431 else { 432 i2c_success = 433 link_query_ddc_data( 434 pipe_ctx->stream->link->ddc, 435 slave_address, &offset, 1, &value, 1); 436 if (!i2c_success) 437 goto i2c_write_fail; 438 } 439 440 buffer[0] = offset; 441 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 442 buffer[1] = value | apply_rx_tx_change; 443 i2c_success = write_i2c(pipe_ctx, slave_address, 444 buffer, sizeof(buffer)); 445 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 446 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 447 slave_address, buffer[0], buffer[1], i2c_success?1:0); 448 if (!i2c_success) 449 goto i2c_write_fail; 450 } 451 } 452 } 453 } 454 455 if (is_vga_mode) { 456 /* Program additional settings if using 640x480 resolution */ 457 458 /* Write offset 0xFF to 0x01 */ 459 buffer[0] = 0xff; 460 buffer[1] = 0x01; 461 i2c_success = write_i2c(pipe_ctx, slave_address, 462 buffer, sizeof(buffer)); 463 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 464 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 465 slave_address, buffer[0], buffer[1], i2c_success?1:0); 466 if (!i2c_success) 467 goto i2c_write_fail; 468 469 /* Write offset 0x00 to 0x23 */ 470 buffer[0] = 0x00; 471 buffer[1] = 0x23; 472 i2c_success = write_i2c(pipe_ctx, slave_address, 473 buffer, sizeof(buffer)); 474 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 475 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 476 slave_address, buffer[0], buffer[1], i2c_success?1:0); 477 if (!i2c_success) 478 goto i2c_write_fail; 479 480 /* Write offset 0xff to 0x00 */ 481 buffer[0] = 0xff; 482 buffer[1] = 0x00; 483 i2c_success = write_i2c(pipe_ctx, slave_address, 484 buffer, sizeof(buffer)); 485 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 486 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 487 slave_address, buffer[0], buffer[1], i2c_success?1:0); 488 if (!i2c_success) 489 goto i2c_write_fail; 490 491 } 492 493 return; 494 495 i2c_write_fail: 496 DC_LOG_DEBUG("Set retimer failed"); 497 } 498 499 static void write_i2c_default_retimer_setting( 500 struct pipe_ctx *pipe_ctx, 501 bool is_vga_mode, 502 bool is_over_340mhz) 503 { 504 uint8_t slave_address = (0xBA >> 1); 505 uint8_t buffer[2]; 506 bool i2c_success = false; 507 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 508 509 memset(&buffer, 0, sizeof(buffer)); 510 511 /* Program Slave Address for tuning single integrity */ 512 /* Write offset 0x0A to 0x13 */ 513 buffer[0] = 0x0A; 514 buffer[1] = 0x13; 515 i2c_success = write_i2c(pipe_ctx, slave_address, 516 buffer, sizeof(buffer)); 517 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 518 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 519 slave_address, buffer[0], buffer[1], i2c_success?1:0); 520 if (!i2c_success) 521 goto i2c_write_fail; 522 523 /* Write offset 0x0A to 0x17 */ 524 buffer[0] = 0x0A; 525 buffer[1] = 0x17; 526 i2c_success = write_i2c(pipe_ctx, slave_address, 527 buffer, sizeof(buffer)); 528 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 529 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 530 slave_address, buffer[0], buffer[1], i2c_success?1:0); 531 if (!i2c_success) 532 goto i2c_write_fail; 533 534 /* Write offset 0x0B to 0xDA or 0xD8 */ 535 buffer[0] = 0x0B; 536 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 537 i2c_success = write_i2c(pipe_ctx, slave_address, 538 buffer, sizeof(buffer)); 539 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 540 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 541 slave_address, buffer[0], buffer[1], i2c_success?1:0); 542 if (!i2c_success) 543 goto i2c_write_fail; 544 545 /* Write offset 0x0A to 0x17 */ 546 buffer[0] = 0x0A; 547 buffer[1] = 0x17; 548 i2c_success = write_i2c(pipe_ctx, slave_address, 549 buffer, sizeof(buffer)); 550 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 551 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 552 slave_address, buffer[0], buffer[1], i2c_success?1:0); 553 if (!i2c_success) 554 goto i2c_write_fail; 555 556 /* Write offset 0x0C to 0x1D or 0x91 */ 557 buffer[0] = 0x0C; 558 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 559 i2c_success = write_i2c(pipe_ctx, slave_address, 560 buffer, sizeof(buffer)); 561 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 562 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 563 slave_address, buffer[0], buffer[1], i2c_success?1:0); 564 if (!i2c_success) 565 goto i2c_write_fail; 566 567 /* Write offset 0x0A to 0x17 */ 568 buffer[0] = 0x0A; 569 buffer[1] = 0x17; 570 i2c_success = write_i2c(pipe_ctx, slave_address, 571 buffer, sizeof(buffer)); 572 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 573 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 574 slave_address, buffer[0], buffer[1], i2c_success?1:0); 575 if (!i2c_success) 576 goto i2c_write_fail; 577 578 579 if (is_vga_mode) { 580 /* Program additional settings if using 640x480 resolution */ 581 582 /* Write offset 0xFF to 0x01 */ 583 buffer[0] = 0xff; 584 buffer[1] = 0x01; 585 i2c_success = write_i2c(pipe_ctx, slave_address, 586 buffer, sizeof(buffer)); 587 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 588 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 589 slave_address, buffer[0], buffer[1], i2c_success?1:0); 590 if (!i2c_success) 591 goto i2c_write_fail; 592 593 /* Write offset 0x00 to 0x23 */ 594 buffer[0] = 0x00; 595 buffer[1] = 0x23; 596 i2c_success = write_i2c(pipe_ctx, slave_address, 597 buffer, sizeof(buffer)); 598 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 599 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 600 slave_address, buffer[0], buffer[1], i2c_success?1:0); 601 if (!i2c_success) 602 goto i2c_write_fail; 603 604 /* Write offset 0xff to 0x00 */ 605 buffer[0] = 0xff; 606 buffer[1] = 0x00; 607 i2c_success = write_i2c(pipe_ctx, slave_address, 608 buffer, sizeof(buffer)); 609 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 610 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 611 slave_address, buffer[0], buffer[1], i2c_success?1:0); 612 if (!i2c_success) 613 goto i2c_write_fail; 614 } 615 616 return; 617 618 i2c_write_fail: 619 DC_LOG_DEBUG("Set default retimer failed"); 620 } 621 622 static void write_i2c_redriver_setting( 623 struct pipe_ctx *pipe_ctx, 624 bool is_over_340mhz) 625 { 626 uint8_t slave_address = (0xF0 >> 1); 627 uint8_t buffer[16]; 628 bool i2c_success = false; 629 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 630 631 memset(&buffer, 0, sizeof(buffer)); 632 633 // Program Slave Address for tuning single integrity 634 buffer[3] = 0x4E; 635 buffer[4] = 0x4E; 636 buffer[5] = 0x4E; 637 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 638 639 i2c_success = write_i2c(pipe_ctx, slave_address, 640 buffer, sizeof(buffer)); 641 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 642 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 643 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 644 i2c_success = %d\n", 645 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 646 647 if (!i2c_success) 648 DC_LOG_DEBUG("Set redriver failed"); 649 } 650 651 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 652 { 653 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 654 struct link_encoder *link_enc = NULL; 655 struct cp_psp_stream_config config = {0}; 656 enum dp_panel_mode panel_mode = 657 dp_get_panel_mode(pipe_ctx->stream->link); 658 659 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 660 return; 661 662 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 663 ASSERT(link_enc); 664 if (link_enc == NULL) 665 return; 666 667 /* otg instance */ 668 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 669 670 /* dig front end */ 671 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 672 673 /* stream encoder index */ 674 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 675 if (link_is_dp_128b_132b_signal(pipe_ctx)) 676 config.stream_enc_idx = 677 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 678 679 /* dig back end */ 680 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 681 682 /* link encoder index */ 683 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 684 if (link_is_dp_128b_132b_signal(pipe_ctx)) 685 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 686 687 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 688 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 689 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 690 else 691 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 692 693 694 /* phy index */ 695 config.phy_idx = resource_transmitter_to_phy_idx( 696 pipe_ctx->stream->link->dc, link_enc->transmitter); 697 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 698 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 699 config.phy_idx = 0; 700 701 /* stream properties */ 702 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 703 config.mst_enabled = (pipe_ctx->stream->signal == 704 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 705 config.dp2_enabled = link_is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0; 706 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 707 1 : 0; 708 config.dpms_off = dpms_off; 709 710 /* dm stream context */ 711 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 712 713 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 714 } 715 716 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 717 { 718 struct dc *dc = pipe_ctx->stream->ctx->dc; 719 720 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 721 return; 722 723 dc->hwss.set_avmute(pipe_ctx, enable); 724 } 725 726 static void enable_mst_on_sink(struct dc_link *link, bool enable) 727 { 728 unsigned char mstmCntl; 729 730 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 731 if (enable) 732 mstmCntl |= DP_MST_EN; 733 else 734 mstmCntl &= (~DP_MST_EN); 735 736 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 737 } 738 739 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 740 struct dsc_optc_config *config) 741 { 742 uint32_t precision = 1 << 28; 743 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 744 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 745 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 746 DC_LOGGER_INIT(dsc->ctx->logger); 747 748 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 749 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 750 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 751 */ 752 ll_bytes_per_pix_fraq *= 10000000; 753 ll_bytes_per_pix_fraq /= precision; 754 755 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 756 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 757 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 758 DC_LOG_DSC("\tslice_width %d", config->slice_width); 759 } 760 761 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 762 { 763 struct dc *dc = pipe_ctx->stream->ctx->dc; 764 struct dc_stream_state *stream = pipe_ctx->stream; 765 bool result = false; 766 767 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 768 result = true; 769 else 770 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 771 return result; 772 } 773 774 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 775 * i.e. after dp_enable_dsc_on_rx() had been called 776 */ 777 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 778 { 779 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 780 struct dc *dc = pipe_ctx->stream->ctx->dc; 781 struct dc_stream_state *stream = pipe_ctx->stream; 782 struct pipe_ctx *odm_pipe; 783 int opp_cnt = 1; 784 DC_LOGGER_INIT(dsc->ctx->logger); 785 786 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 787 opp_cnt++; 788 789 if (enable) { 790 struct dsc_config dsc_cfg; 791 struct dsc_optc_config dsc_optc_cfg; 792 enum optc_dsc_mode optc_dsc_mode; 793 794 /* Enable DSC hw block */ 795 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 796 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 797 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 798 dsc_cfg.color_depth = stream->timing.display_color_depth; 799 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 800 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 801 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 802 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 803 804 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 805 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 806 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 807 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 808 809 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 810 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 811 } 812 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 813 dsc_cfg.pic_width *= opp_cnt; 814 815 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 816 817 /* Enable DSC in encoder */ 818 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) 819 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 820 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 821 dsc_optc_config_log(dsc, &dsc_optc_cfg); 822 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 823 optc_dsc_mode, 824 dsc_optc_cfg.bytes_per_pixel, 825 dsc_optc_cfg.slice_width); 826 827 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 828 } 829 830 /* Enable DSC in OPTC */ 831 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 832 dsc_optc_config_log(dsc, &dsc_optc_cfg); 833 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 834 optc_dsc_mode, 835 dsc_optc_cfg.bytes_per_pixel, 836 dsc_optc_cfg.slice_width); 837 } else { 838 /* disable DSC in OPTC */ 839 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 840 pipe_ctx->stream_res.tg, 841 OPTC_DSC_DISABLED, 0, 0); 842 843 /* disable DSC in stream encoder */ 844 if (dc_is_dp_signal(stream->signal)) { 845 if (link_is_dp_128b_132b_signal(pipe_ctx)) 846 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 847 pipe_ctx->stream_res.hpo_dp_stream_enc, 848 false, 849 NULL, 850 true); 851 else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 852 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 853 pipe_ctx->stream_res.stream_enc, 854 OPTC_DSC_DISABLED, 0, 0); 855 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 856 pipe_ctx->stream_res.stream_enc, false, NULL, true); 857 } 858 } 859 860 /* disable DSC block */ 861 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 862 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 863 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 864 } 865 } 866 867 /* 868 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 869 * hence PPS info packet update need to use frame update instead of immediate update. 870 * Added parameter immediate_update for this purpose. 871 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 872 * which is the only place where a "false" would be passed in for param immediate_update. 873 * 874 * immediate_update is only applicable when DSC is enabled. 875 */ 876 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 877 { 878 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 879 struct dc_stream_state *stream = pipe_ctx->stream; 880 DC_LOGGER_INIT(dsc->ctx->logger); 881 882 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 883 return false; 884 885 if (enable) { 886 struct dsc_config dsc_cfg; 887 uint8_t dsc_packed_pps[128]; 888 889 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 890 memset(dsc_packed_pps, 0, 128); 891 892 /* Enable DSC hw block */ 893 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 894 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 895 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 896 dsc_cfg.color_depth = stream->timing.display_color_depth; 897 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 898 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 899 900 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 901 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 902 if (dc_is_dp_signal(stream->signal)) { 903 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 904 if (link_is_dp_128b_132b_signal(pipe_ctx)) 905 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 906 pipe_ctx->stream_res.hpo_dp_stream_enc, 907 true, 908 &dsc_packed_pps[0], 909 immediate_update); 910 else 911 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 912 pipe_ctx->stream_res.stream_enc, 913 true, 914 &dsc_packed_pps[0], 915 immediate_update); 916 } 917 } else { 918 /* disable DSC PPS in stream encoder */ 919 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 920 if (dc_is_dp_signal(stream->signal)) { 921 if (link_is_dp_128b_132b_signal(pipe_ctx)) 922 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 923 pipe_ctx->stream_res.hpo_dp_stream_enc, 924 false, 925 NULL, 926 true); 927 else 928 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 929 pipe_ctx->stream_res.stream_enc, false, NULL, true); 930 } 931 } 932 933 return true; 934 } 935 936 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 937 { 938 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 939 bool result = false; 940 941 if (!pipe_ctx->stream->timing.flags.DSC) 942 goto out; 943 if (!dsc) 944 goto out; 945 946 if (enable) { 947 { 948 link_set_dsc_on_stream(pipe_ctx, true); 949 result = true; 950 } 951 } else { 952 dp_set_dsc_on_rx(pipe_ctx, false); 953 link_set_dsc_on_stream(pipe_ctx, false); 954 result = true; 955 } 956 out: 957 return result; 958 } 959 960 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 961 { 962 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 963 964 if (!pipe_ctx->stream->timing.flags.DSC) 965 return false; 966 if (!dsc) 967 return false; 968 969 link_set_dsc_on_stream(pipe_ctx, true); 970 link_set_dsc_pps_packet(pipe_ctx, true, false); 971 return true; 972 } 973 974 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 975 { 976 struct dc_stream_state *stream = pipe_ctx->stream; 977 978 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 979 struct dc_link *link = stream->link; 980 union down_spread_ctrl old_downspread; 981 union down_spread_ctrl new_downspread; 982 983 memset(&old_downspread, 0, sizeof(old_downspread)); 984 985 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 986 &old_downspread.raw, sizeof(old_downspread)); 987 988 new_downspread.raw = old_downspread.raw; 989 990 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 991 (stream->ignore_msa_timing_param) ? 1 : 0; 992 993 if (new_downspread.raw != old_downspread.raw) { 994 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 995 &new_downspread.raw, sizeof(new_downspread)); 996 } 997 998 } else { 999 dm_helpers_mst_enable_stream_features(stream); 1000 } 1001 } 1002 1003 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1004 { 1005 const uint32_t VCP_Y_PRECISION = 1000; 1006 uint64_t vcp_x, vcp_y; 1007 DC_LOGGER_INIT(link->ctx->logger); 1008 1009 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1010 avg_time_slots_per_mtp = dc_fixpt_add( 1011 avg_time_slots_per_mtp, 1012 dc_fixpt_from_fraction( 1013 1, 1014 2*VCP_Y_PRECISION)); 1015 1016 vcp_x = dc_fixpt_floor( 1017 avg_time_slots_per_mtp); 1018 vcp_y = dc_fixpt_floor( 1019 dc_fixpt_mul_int( 1020 dc_fixpt_sub_int( 1021 avg_time_slots_per_mtp, 1022 dc_fixpt_floor( 1023 avg_time_slots_per_mtp)), 1024 VCP_Y_PRECISION)); 1025 1026 1027 if (link->type == dc_connection_mst_branch) 1028 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1029 "X: %llu " 1030 "Y: %llu/%d", 1031 vcp_x, 1032 vcp_y, 1033 VCP_Y_PRECISION); 1034 else 1035 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1036 "X: %llu " 1037 "Y: %llu/%d", 1038 vcp_x, 1039 vcp_y, 1040 VCP_Y_PRECISION); 1041 } 1042 1043 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1044 { 1045 struct fixed31_32 mbytes_per_sec; 1046 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, 1047 &stream->link->cur_link_settings); 1048 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1049 1050 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1051 1052 return dc_fixpt_div_int(mbytes_per_sec, 54); 1053 } 1054 1055 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1056 { 1057 struct fixed31_32 peak_kbps; 1058 uint32_t numerator = 0; 1059 uint32_t denominator = 1; 1060 1061 /* 1062 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1063 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1064 * common multiplier to render an integer PBN for all link rate/lane 1065 * counts combinations 1066 * calculate 1067 * peak_kbps *= (1006/1000) 1068 * peak_kbps *= (64/54) 1069 * peak_kbps *= 8 convert to bytes 1070 */ 1071 1072 numerator = 64 * PEAK_FACTOR_X1000; 1073 denominator = 54 * 8 * 1000 * 1000; 1074 kbps *= numerator; 1075 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1076 1077 return peak_kbps; 1078 } 1079 1080 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1081 { 1082 uint64_t kbps; 1083 1084 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1085 return get_pbn_from_bw_in_kbps(kbps); 1086 } 1087 1088 1089 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1090 static void get_lane_status( 1091 struct dc_link *link, 1092 uint32_t lane_count, 1093 union lane_status *status, 1094 union lane_align_status_updated *status_updated) 1095 { 1096 unsigned int lane; 1097 uint8_t dpcd_buf[3] = {0}; 1098 1099 if (status == NULL || status_updated == NULL) { 1100 return; 1101 } 1102 1103 core_link_read_dpcd( 1104 link, 1105 DP_LANE0_1_STATUS, 1106 dpcd_buf, 1107 sizeof(dpcd_buf)); 1108 1109 for (lane = 0; lane < lane_count; lane++) { 1110 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1111 } 1112 1113 status_updated->raw = dpcd_buf[2]; 1114 } 1115 1116 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1117 { 1118 /* 1119 * wait for ACT handled 1120 */ 1121 int i; 1122 const int act_retries = 30; 1123 enum act_return_status result = ACT_FAILED; 1124 union payload_table_update_status update_status = {0}; 1125 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1126 union lane_align_status_updated lane_status_updated; 1127 DC_LOGGER_INIT(link->ctx->logger); 1128 1129 if (link->aux_access_disabled) 1130 return true; 1131 for (i = 0; i < act_retries; i++) { 1132 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1133 1134 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1135 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1136 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1137 !dp_is_interlane_aligned(lane_status_updated)) { 1138 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1139 "polling for ACT handled."); 1140 result = ACT_LINK_LOST; 1141 break; 1142 } 1143 core_link_read_dpcd( 1144 link, 1145 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1146 &update_status.raw, 1147 1); 1148 1149 if (update_status.bits.ACT_HANDLED == 1) { 1150 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1151 result = ACT_SUCCESS; 1152 break; 1153 } 1154 1155 fsleep(5000); 1156 } 1157 1158 if (result == ACT_FAILED) { 1159 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1160 "continue on. Something is wrong with the branch."); 1161 } 1162 1163 return (result == ACT_SUCCESS); 1164 } 1165 1166 static void update_mst_stream_alloc_table( 1167 struct dc_link *link, 1168 struct stream_encoder *stream_enc, 1169 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1170 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1171 { 1172 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1173 struct link_mst_stream_allocation *dc_alloc; 1174 1175 int i; 1176 int j; 1177 1178 /* if DRM proposed_table has more than one new payload */ 1179 ASSERT(proposed_table->stream_count - 1180 link->mst_stream_alloc_table.stream_count < 2); 1181 1182 /* copy proposed_table to link, add stream encoder */ 1183 for (i = 0; i < proposed_table->stream_count; i++) { 1184 1185 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1186 dc_alloc = 1187 &link->mst_stream_alloc_table.stream_allocations[j]; 1188 1189 if (dc_alloc->vcp_id == 1190 proposed_table->stream_allocations[i].vcp_id) { 1191 1192 work_table[i] = *dc_alloc; 1193 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1194 break; /* exit j loop */ 1195 } 1196 } 1197 1198 /* new vcp_id */ 1199 if (j == link->mst_stream_alloc_table.stream_count) { 1200 work_table[i].vcp_id = 1201 proposed_table->stream_allocations[i].vcp_id; 1202 work_table[i].slot_count = 1203 proposed_table->stream_allocations[i].slot_count; 1204 work_table[i].stream_enc = stream_enc; 1205 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1206 } 1207 } 1208 1209 /* update link->mst_stream_alloc_table with work_table */ 1210 link->mst_stream_alloc_table.stream_count = 1211 proposed_table->stream_count; 1212 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1213 link->mst_stream_alloc_table.stream_allocations[i] = 1214 work_table[i]; 1215 } 1216 1217 static void remove_stream_from_alloc_table( 1218 struct dc_link *link, 1219 struct stream_encoder *dio_stream_enc, 1220 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1221 { 1222 int i = 0; 1223 struct link_mst_stream_allocation_table *table = 1224 &link->mst_stream_alloc_table; 1225 1226 if (hpo_dp_stream_enc) { 1227 for (; i < table->stream_count; i++) 1228 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1229 break; 1230 } else { 1231 for (; i < table->stream_count; i++) 1232 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1233 break; 1234 } 1235 1236 if (i < table->stream_count) { 1237 i++; 1238 for (; i < table->stream_count; i++) 1239 table->stream_allocations[i-1] = table->stream_allocations[i]; 1240 memset(&table->stream_allocations[table->stream_count-1], 0, 1241 sizeof(struct link_mst_stream_allocation)); 1242 table->stream_count--; 1243 } 1244 } 1245 1246 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1247 struct pipe_ctx *pipe_ctx) 1248 { 1249 struct dc_stream_state *stream = pipe_ctx->stream; 1250 struct dc_link *link = stream->link; 1251 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1252 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1253 int i; 1254 bool mst_mode = (link->type == dc_connection_mst_branch); 1255 /* adjust for drm changes*/ 1256 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1257 const struct dc_link_settings empty_link_settings = {0}; 1258 DC_LOGGER_INIT(link->ctx->logger); 1259 1260 if (link_hwss->ext.set_throttled_vcp_size) 1261 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1262 if (link_hwss->ext.set_hblank_min_symbol_width) 1263 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1264 &empty_link_settings, 1265 avg_time_slots_per_mtp); 1266 1267 if (dm_helpers_dp_mst_write_payload_allocation_table( 1268 stream->ctx, 1269 stream, 1270 &proposed_table, 1271 false)) 1272 update_mst_stream_alloc_table( 1273 link, 1274 pipe_ctx->stream_res.stream_enc, 1275 pipe_ctx->stream_res.hpo_dp_stream_enc, 1276 &proposed_table); 1277 else 1278 DC_LOG_WARNING("Failed to update" 1279 "MST allocation table for" 1280 "pipe idx:%d\n", 1281 pipe_ctx->pipe_idx); 1282 1283 DC_LOG_MST("%s" 1284 "stream_count: %d: ", 1285 __func__, 1286 link->mst_stream_alloc_table.stream_count); 1287 1288 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1289 DC_LOG_MST("stream_enc[%d]: %p " 1290 "stream[%d].hpo_dp_stream_enc: %p " 1291 "stream[%d].vcp_id: %d " 1292 "stream[%d].slot_count: %d\n", 1293 i, 1294 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1295 i, 1296 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1297 i, 1298 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1299 i, 1300 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1301 } 1302 1303 if (link_hwss->ext.update_stream_allocation_table == NULL || 1304 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1305 DC_LOG_DEBUG("Unknown encoding format\n"); 1306 return DC_ERROR_UNEXPECTED; 1307 } 1308 1309 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1310 &link->mst_stream_alloc_table); 1311 1312 if (mst_mode) { 1313 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1314 stream->ctx, 1315 stream); 1316 } 1317 1318 dm_helpers_dp_mst_send_payload_allocation( 1319 stream->ctx, 1320 stream, 1321 false); 1322 1323 return DC_OK; 1324 } 1325 1326 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1327 { 1328 struct dc_stream_state *stream = pipe_ctx->stream; 1329 struct dc_link *link = stream->link; 1330 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1331 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1332 int i; 1333 bool mst_mode = (link->type == dc_connection_mst_branch); 1334 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1335 const struct dc_link_settings empty_link_settings = {0}; 1336 DC_LOGGER_INIT(link->ctx->logger); 1337 1338 if (link->dc->debug.temp_mst_deallocation_sequence) 1339 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1340 1341 /* deallocate_mst_payload is called before disable link. When mode or 1342 * disable/enable monitor, new stream is created which is not in link 1343 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1344 * should not done. For new mode set, map_resources will get engine 1345 * for new stream, so stream_enc->id should be validated until here. 1346 */ 1347 1348 /* slot X.Y */ 1349 if (link_hwss->ext.set_throttled_vcp_size) 1350 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1351 if (link_hwss->ext.set_hblank_min_symbol_width) 1352 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1353 &empty_link_settings, 1354 avg_time_slots_per_mtp); 1355 1356 if (mst_mode) { 1357 /* when link is in mst mode, reply on mst manager to remove 1358 * payload 1359 */ 1360 if (dm_helpers_dp_mst_write_payload_allocation_table( 1361 stream->ctx, 1362 stream, 1363 &proposed_table, 1364 false)) 1365 update_mst_stream_alloc_table( 1366 link, 1367 pipe_ctx->stream_res.stream_enc, 1368 pipe_ctx->stream_res.hpo_dp_stream_enc, 1369 &proposed_table); 1370 else 1371 DC_LOG_WARNING("Failed to update" 1372 "MST allocation table for" 1373 "pipe idx:%d\n", 1374 pipe_ctx->pipe_idx); 1375 } else { 1376 /* when link is no longer in mst mode (mst hub unplugged), 1377 * remove payload with default dc logic 1378 */ 1379 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1380 pipe_ctx->stream_res.hpo_dp_stream_enc); 1381 } 1382 1383 DC_LOG_MST("%s" 1384 "stream_count: %d: ", 1385 __func__, 1386 link->mst_stream_alloc_table.stream_count); 1387 1388 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1389 DC_LOG_MST("stream_enc[%d]: %p " 1390 "stream[%d].hpo_dp_stream_enc: %p " 1391 "stream[%d].vcp_id: %d " 1392 "stream[%d].slot_count: %d\n", 1393 i, 1394 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1395 i, 1396 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1397 i, 1398 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1399 i, 1400 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1401 } 1402 1403 /* update mst stream allocation table hardware state */ 1404 if (link_hwss->ext.update_stream_allocation_table == NULL || 1405 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1406 DC_LOG_DEBUG("Unknown encoding format\n"); 1407 return DC_ERROR_UNEXPECTED; 1408 } 1409 1410 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1411 &link->mst_stream_alloc_table); 1412 1413 if (mst_mode) { 1414 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1415 stream->ctx, 1416 stream); 1417 1418 dm_helpers_dp_mst_send_payload_allocation( 1419 stream->ctx, 1420 stream, 1421 false); 1422 } 1423 1424 return DC_OK; 1425 } 1426 1427 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1428 * because stream_encoder is not exposed to dm 1429 */ 1430 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1431 { 1432 struct dc_stream_state *stream = pipe_ctx->stream; 1433 struct dc_link *link = stream->link; 1434 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1435 struct fixed31_32 avg_time_slots_per_mtp; 1436 struct fixed31_32 pbn; 1437 struct fixed31_32 pbn_per_slot; 1438 int i; 1439 enum act_return_status ret; 1440 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1441 DC_LOGGER_INIT(link->ctx->logger); 1442 1443 /* enable_link_dp_mst already check link->enabled_stream_count 1444 * and stream is in link->stream[]. This is called during set mode, 1445 * stream_enc is available. 1446 */ 1447 1448 /* get calculate VC payload for stream: stream_alloc */ 1449 if (dm_helpers_dp_mst_write_payload_allocation_table( 1450 stream->ctx, 1451 stream, 1452 &proposed_table, 1453 true)) 1454 update_mst_stream_alloc_table( 1455 link, 1456 pipe_ctx->stream_res.stream_enc, 1457 pipe_ctx->stream_res.hpo_dp_stream_enc, 1458 &proposed_table); 1459 else 1460 DC_LOG_WARNING("Failed to update" 1461 "MST allocation table for" 1462 "pipe idx:%d\n", 1463 pipe_ctx->pipe_idx); 1464 1465 DC_LOG_MST("%s " 1466 "stream_count: %d: \n ", 1467 __func__, 1468 link->mst_stream_alloc_table.stream_count); 1469 1470 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1471 DC_LOG_MST("stream_enc[%d]: %p " 1472 "stream[%d].hpo_dp_stream_enc: %p " 1473 "stream[%d].vcp_id: %d " 1474 "stream[%d].slot_count: %d\n", 1475 i, 1476 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1477 i, 1478 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1479 i, 1480 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1481 i, 1482 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1483 } 1484 1485 ASSERT(proposed_table.stream_count > 0); 1486 1487 /* program DP source TX for payload */ 1488 if (link_hwss->ext.update_stream_allocation_table == NULL || 1489 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1490 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1491 return DC_ERROR_UNEXPECTED; 1492 } 1493 1494 link_hwss->ext.update_stream_allocation_table(link, 1495 &pipe_ctx->link_res, 1496 &link->mst_stream_alloc_table); 1497 1498 /* send down message */ 1499 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1500 stream->ctx, 1501 stream); 1502 1503 if (ret != ACT_LINK_LOST) { 1504 dm_helpers_dp_mst_send_payload_allocation( 1505 stream->ctx, 1506 stream, 1507 true); 1508 } 1509 1510 /* slot X.Y for only current stream */ 1511 pbn_per_slot = get_pbn_per_slot(stream); 1512 if (pbn_per_slot.value == 0) { 1513 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1514 return DC_UNSUPPORTED_VALUE; 1515 } 1516 pbn = get_pbn_from_timing(pipe_ctx); 1517 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1518 1519 log_vcp_x_y(link, avg_time_slots_per_mtp); 1520 1521 if (link_hwss->ext.set_throttled_vcp_size) 1522 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1523 if (link_hwss->ext.set_hblank_min_symbol_width) 1524 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1525 &link->cur_link_settings, 1526 avg_time_slots_per_mtp); 1527 1528 return DC_OK; 1529 } 1530 1531 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1532 const struct dc_stream_state *stream, 1533 const struct dc_link *link) 1534 { 1535 struct fixed31_32 link_bw_effective = 1536 dc_fixpt_from_int( 1537 dc_link_bandwidth_kbps(link, &link->cur_link_settings)); 1538 struct fixed31_32 timeslot_bw_effective = 1539 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1540 struct fixed31_32 timing_bw = 1541 dc_fixpt_from_int( 1542 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1543 struct fixed31_32 avg_time_slots_per_mtp = 1544 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1545 1546 return avg_time_slots_per_mtp; 1547 } 1548 1549 1550 static bool write_128b_132b_sst_payload_allocation_table( 1551 const struct dc_stream_state *stream, 1552 struct dc_link *link, 1553 struct link_mst_stream_allocation_table *proposed_table, 1554 bool allocate) 1555 { 1556 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1557 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1558 bool result = false; 1559 uint8_t req_slot_count = 0; 1560 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1561 union payload_table_update_status update_status = { 0 }; 1562 const uint32_t max_retries = 30; 1563 uint32_t retries = 0; 1564 DC_LOGGER_INIT(link->ctx->logger); 1565 1566 if (allocate) { 1567 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1568 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1569 /// Validation should filter out modes that exceed link BW 1570 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1571 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1572 return false; 1573 } else { 1574 /// Leave req_slot_count = 0 if allocate is false. 1575 } 1576 1577 proposed_table->stream_count = 1; /// Always 1 stream for SST 1578 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1579 proposed_table->stream_allocations[0].vcp_id = vc_id; 1580 1581 if (link->aux_access_disabled) 1582 return true; 1583 1584 /// Write DPCD 2C0 = 1 to start updating 1585 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1586 core_link_write_dpcd( 1587 link, 1588 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1589 &update_status.raw, 1590 1); 1591 1592 /// Program the changes in DPCD 1C0 - 1C2 1593 ASSERT(vc_id == 1); 1594 core_link_write_dpcd( 1595 link, 1596 DP_PAYLOAD_ALLOCATE_SET, 1597 &vc_id, 1598 1); 1599 1600 ASSERT(start_time_slot == 0); 1601 core_link_write_dpcd( 1602 link, 1603 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1604 &start_time_slot, 1605 1); 1606 1607 core_link_write_dpcd( 1608 link, 1609 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1610 &req_slot_count, 1611 1); 1612 1613 /// Poll till DPCD 2C0 read 1 1614 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1615 1616 while (retries < max_retries) { 1617 if (core_link_read_dpcd( 1618 link, 1619 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1620 &update_status.raw, 1621 1) == DC_OK) { 1622 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1623 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1624 result = true; 1625 break; 1626 } 1627 } else { 1628 union dpcd_rev dpcdRev; 1629 1630 if (core_link_read_dpcd( 1631 link, 1632 DP_DPCD_REV, 1633 &dpcdRev.raw, 1634 1) != DC_OK) { 1635 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1636 "of sink while polling payload table " 1637 "updated status bit."); 1638 break; 1639 } 1640 } 1641 retries++; 1642 fsleep(5000); 1643 } 1644 1645 if (!result && retries == max_retries) { 1646 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1647 "continue on. Something is wrong with the branch."); 1648 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1649 } 1650 1651 return result; 1652 } 1653 1654 /* 1655 * Payload allocation/deallocation for SST introduced in DP2.0 1656 */ 1657 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1658 bool allocate) 1659 { 1660 struct dc_stream_state *stream = pipe_ctx->stream; 1661 struct dc_link *link = stream->link; 1662 struct link_mst_stream_allocation_table proposed_table = {0}; 1663 struct fixed31_32 avg_time_slots_per_mtp; 1664 const struct dc_link_settings empty_link_settings = {0}; 1665 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1666 DC_LOGGER_INIT(link->ctx->logger); 1667 1668 /* slot X.Y for SST payload deallocate */ 1669 if (!allocate) { 1670 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1671 1672 log_vcp_x_y(link, avg_time_slots_per_mtp); 1673 1674 if (link_hwss->ext.set_throttled_vcp_size) 1675 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1676 avg_time_slots_per_mtp); 1677 if (link_hwss->ext.set_hblank_min_symbol_width) 1678 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1679 &empty_link_settings, 1680 avg_time_slots_per_mtp); 1681 } 1682 1683 /* calculate VC payload and update branch with new payload allocation table*/ 1684 if (!write_128b_132b_sst_payload_allocation_table( 1685 stream, 1686 link, 1687 &proposed_table, 1688 allocate)) { 1689 DC_LOG_ERROR("SST Update Payload: Failed to update " 1690 "allocation table for " 1691 "pipe idx: %d\n", 1692 pipe_ctx->pipe_idx); 1693 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1694 } 1695 1696 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1697 1698 ASSERT(proposed_table.stream_count == 1); 1699 1700 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1701 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1702 "vcp_id: %d " 1703 "slot_count: %d\n", 1704 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1705 proposed_table.stream_allocations[0].vcp_id, 1706 proposed_table.stream_allocations[0].slot_count); 1707 1708 /* program DP source TX for payload */ 1709 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1710 &proposed_table); 1711 1712 /* poll for ACT handled */ 1713 if (!poll_for_allocation_change_trigger(link)) { 1714 // Failures will result in blackscreen and errors logged 1715 BREAK_TO_DEBUGGER(); 1716 } 1717 1718 /* slot X.Y for SST payload allocate */ 1719 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1720 DP_128b_132b_ENCODING) { 1721 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1722 1723 log_vcp_x_y(link, avg_time_slots_per_mtp); 1724 1725 if (link_hwss->ext.set_throttled_vcp_size) 1726 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1727 avg_time_slots_per_mtp); 1728 if (link_hwss->ext.set_hblank_min_symbol_width) 1729 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1730 &link->cur_link_settings, 1731 avg_time_slots_per_mtp); 1732 } 1733 1734 /* Always return DC_OK. 1735 * If part of sequence fails, log failure(s) and show blackscreen 1736 */ 1737 return DC_OK; 1738 } 1739 1740 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1741 { 1742 struct dc_stream_state *stream = pipe_ctx->stream; 1743 struct dc_link *link = stream->link; 1744 struct fixed31_32 avg_time_slots_per_mtp; 1745 struct fixed31_32 pbn; 1746 struct fixed31_32 pbn_per_slot; 1747 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1748 uint8_t i; 1749 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1750 DC_LOGGER_INIT(link->ctx->logger); 1751 1752 /* decrease throttled vcp size */ 1753 pbn_per_slot = get_pbn_per_slot(stream); 1754 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1755 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1756 1757 if (link_hwss->ext.set_throttled_vcp_size) 1758 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1759 if (link_hwss->ext.set_hblank_min_symbol_width) 1760 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1761 &link->cur_link_settings, 1762 avg_time_slots_per_mtp); 1763 1764 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1765 dm_helpers_dp_mst_send_payload_allocation( 1766 stream->ctx, 1767 stream, 1768 true); 1769 1770 /* notify immediate branch device table update */ 1771 if (dm_helpers_dp_mst_write_payload_allocation_table( 1772 stream->ctx, 1773 stream, 1774 &proposed_table, 1775 true)) { 1776 /* update mst stream allocation table software state */ 1777 update_mst_stream_alloc_table( 1778 link, 1779 pipe_ctx->stream_res.stream_enc, 1780 pipe_ctx->stream_res.hpo_dp_stream_enc, 1781 &proposed_table); 1782 } else { 1783 DC_LOG_WARNING("Failed to update" 1784 "MST allocation table for" 1785 "pipe idx:%d\n", 1786 pipe_ctx->pipe_idx); 1787 } 1788 1789 DC_LOG_MST("%s " 1790 "stream_count: %d: \n ", 1791 __func__, 1792 link->mst_stream_alloc_table.stream_count); 1793 1794 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1795 DC_LOG_MST("stream_enc[%d]: %p " 1796 "stream[%d].hpo_dp_stream_enc: %p " 1797 "stream[%d].vcp_id: %d " 1798 "stream[%d].slot_count: %d\n", 1799 i, 1800 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1801 i, 1802 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1803 i, 1804 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1805 i, 1806 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1807 } 1808 1809 ASSERT(proposed_table.stream_count > 0); 1810 1811 /* update mst stream allocation table hardware state */ 1812 if (link_hwss->ext.update_stream_allocation_table == NULL || 1813 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1814 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1815 return DC_ERROR_UNEXPECTED; 1816 } 1817 1818 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1819 &link->mst_stream_alloc_table); 1820 1821 /* poll for immediate branch device ACT handled */ 1822 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1823 stream->ctx, 1824 stream); 1825 1826 return DC_OK; 1827 } 1828 1829 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1830 { 1831 struct dc_stream_state *stream = pipe_ctx->stream; 1832 struct dc_link *link = stream->link; 1833 struct fixed31_32 avg_time_slots_per_mtp; 1834 struct fixed31_32 pbn; 1835 struct fixed31_32 pbn_per_slot; 1836 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1837 uint8_t i; 1838 enum act_return_status ret; 1839 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1840 DC_LOGGER_INIT(link->ctx->logger); 1841 1842 /* notify immediate branch device table update */ 1843 if (dm_helpers_dp_mst_write_payload_allocation_table( 1844 stream->ctx, 1845 stream, 1846 &proposed_table, 1847 true)) { 1848 /* update mst stream allocation table software state */ 1849 update_mst_stream_alloc_table( 1850 link, 1851 pipe_ctx->stream_res.stream_enc, 1852 pipe_ctx->stream_res.hpo_dp_stream_enc, 1853 &proposed_table); 1854 } 1855 1856 DC_LOG_MST("%s " 1857 "stream_count: %d: \n ", 1858 __func__, 1859 link->mst_stream_alloc_table.stream_count); 1860 1861 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1862 DC_LOG_MST("stream_enc[%d]: %p " 1863 "stream[%d].hpo_dp_stream_enc: %p " 1864 "stream[%d].vcp_id: %d " 1865 "stream[%d].slot_count: %d\n", 1866 i, 1867 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1868 i, 1869 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1870 i, 1871 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1872 i, 1873 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1874 } 1875 1876 ASSERT(proposed_table.stream_count > 0); 1877 1878 /* update mst stream allocation table hardware state */ 1879 if (link_hwss->ext.update_stream_allocation_table == NULL || 1880 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1881 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1882 return DC_ERROR_UNEXPECTED; 1883 } 1884 1885 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1886 &link->mst_stream_alloc_table); 1887 1888 /* poll for immediate branch device ACT handled */ 1889 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1890 stream->ctx, 1891 stream); 1892 1893 if (ret != ACT_LINK_LOST) { 1894 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1895 dm_helpers_dp_mst_send_payload_allocation( 1896 stream->ctx, 1897 stream, 1898 true); 1899 } 1900 1901 /* increase throttled vcp size */ 1902 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1903 pbn_per_slot = get_pbn_per_slot(stream); 1904 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1905 1906 if (link_hwss->ext.set_throttled_vcp_size) 1907 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1908 if (link_hwss->ext.set_hblank_min_symbol_width) 1909 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1910 &link->cur_link_settings, 1911 avg_time_slots_per_mtp); 1912 1913 return DC_OK; 1914 } 1915 1916 static void disable_link_dp(struct dc_link *link, 1917 const struct link_resource *link_res, 1918 enum signal_type signal) 1919 { 1920 struct dc_link_settings link_settings = link->cur_link_settings; 1921 1922 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1923 link->mst_stream_alloc_table.stream_count > 0) 1924 /* disable MST link only when last vc payload is deallocated */ 1925 return; 1926 1927 dp_disable_link_phy(link, link_res, signal); 1928 1929 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1930 /* set the sink to SST mode after disabling the link */ 1931 enable_mst_on_sink(link, false); 1932 1933 if (link_dp_get_encoding_format(&link_settings) == 1934 DP_8b_10b_ENCODING) { 1935 dp_set_fec_enable(link, false); 1936 dp_set_fec_ready(link, link_res, false); 1937 } 1938 } 1939 1940 static void disable_link(struct dc_link *link, 1941 const struct link_resource *link_res, 1942 enum signal_type signal) 1943 { 1944 if (dc_is_dp_signal(signal)) { 1945 disable_link_dp(link, link_res, signal); 1946 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1947 link->dc->hwss.disable_link_output(link, link_res, signal); 1948 } 1949 1950 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1951 /* MST disable link only when no stream use the link */ 1952 if (link->mst_stream_alloc_table.stream_count <= 0) 1953 link->link_status.link_active = false; 1954 } else { 1955 link->link_status.link_active = false; 1956 } 1957 } 1958 1959 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1960 { 1961 struct dc_stream_state *stream = pipe_ctx->stream; 1962 struct dc_link *link = stream->link; 1963 enum dc_color_depth display_color_depth; 1964 enum engine_id eng_id; 1965 struct ext_hdmi_settings settings = {0}; 1966 bool is_over_340mhz = false; 1967 bool is_vga_mode = (stream->timing.h_addressable == 640) 1968 && (stream->timing.v_addressable == 480); 1969 struct dc *dc = pipe_ctx->stream->ctx->dc; 1970 1971 if (stream->phy_pix_clk == 0) 1972 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1973 if (stream->phy_pix_clk > 340000) 1974 is_over_340mhz = true; 1975 1976 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1977 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1978 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1979 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1980 /* DP159, Retimer settings */ 1981 eng_id = pipe_ctx->stream_res.stream_enc->id; 1982 1983 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1984 write_i2c_retimer_setting(pipe_ctx, 1985 is_vga_mode, is_over_340mhz, &settings); 1986 } else { 1987 write_i2c_default_retimer_setting(pipe_ctx, 1988 is_vga_mode, is_over_340mhz); 1989 } 1990 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1991 /* PI3EQX1204, Redriver settings */ 1992 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1993 } 1994 } 1995 1996 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1997 write_scdc_data( 1998 stream->link->ddc, 1999 stream->phy_pix_clk, 2000 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2001 2002 memset(&stream->link->cur_link_settings, 0, 2003 sizeof(struct dc_link_settings)); 2004 2005 display_color_depth = stream->timing.display_color_depth; 2006 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2007 display_color_depth = COLOR_DEPTH_888; 2008 2009 dc->hwss.enable_tmds_link_output( 2010 link, 2011 &pipe_ctx->link_res, 2012 pipe_ctx->stream->signal, 2013 pipe_ctx->clock_source->id, 2014 display_color_depth, 2015 stream->phy_pix_clk); 2016 2017 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2018 read_scdc_data(link->ddc); 2019 } 2020 2021 static enum dc_status enable_link_dp(struct dc_state *state, 2022 struct pipe_ctx *pipe_ctx) 2023 { 2024 struct dc_stream_state *stream = pipe_ctx->stream; 2025 enum dc_status status; 2026 bool skip_video_pattern; 2027 struct dc_link *link = stream->link; 2028 const struct dc_link_settings *link_settings = 2029 &pipe_ctx->link_config.dp_link_settings; 2030 bool fec_enable; 2031 int i; 2032 bool apply_seamless_boot_optimization = false; 2033 uint32_t bl_oled_enable_delay = 50; // in ms 2034 uint32_t post_oui_delay = 30; // 30ms 2035 /* Reduce link bandwidth between failed link training attempts. */ 2036 bool do_fallback = false; 2037 2038 // check for seamless boot 2039 for (i = 0; i < state->stream_count; i++) { 2040 if (state->streams[i]->apply_seamless_boot_optimization) { 2041 apply_seamless_boot_optimization = true; 2042 break; 2043 } 2044 } 2045 2046 /* 2047 * If the link is DP-over-USB4 do the following: 2048 * - Train with fallback when enabling DPIA link. Conventional links are 2049 * trained with fallback during sink detection. 2050 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2051 * in case stream needs more or less bw from what has been allocated 2052 * earlier at plug time. 2053 */ 2054 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2055 do_fallback = true; 2056 } 2057 2058 /* 2059 * Temporary w/a to get DP2.0 link rates to work with SST. 2060 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2061 */ 2062 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2063 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2064 link->dc->debug.set_mst_en_for_sst) { 2065 enable_mst_on_sink(link, true); 2066 } 2067 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2068 /*in case it is not on*/ 2069 if (!link->dc->config.edp_no_power_sequencing) 2070 link->dc->hwss.edp_power_control(link, true); 2071 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2072 } 2073 2074 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2075 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2076 } else { 2077 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2078 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2079 if (state->clk_mgr && !apply_seamless_boot_optimization) 2080 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2081 state, false); 2082 } 2083 2084 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2085 dpcd_set_source_specific_data(link); 2086 if (link->dpcd_sink_ext_caps.raw != 0) { 2087 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2088 msleep(post_oui_delay); 2089 } 2090 2091 // similarly, mode switch can cause loss of cable ID 2092 dpcd_write_cable_id_to_dprx(link); 2093 2094 skip_video_pattern = true; 2095 2096 if (link_settings->link_rate == LINK_RATE_LOW) 2097 skip_video_pattern = false; 2098 2099 if (perform_link_training_with_retries(link_settings, 2100 skip_video_pattern, 2101 LINK_TRAINING_ATTEMPTS, 2102 pipe_ctx, 2103 pipe_ctx->stream->signal, 2104 do_fallback)) { 2105 status = DC_OK; 2106 } else { 2107 status = DC_FAIL_DP_LINK_TRAINING; 2108 } 2109 2110 if (link->preferred_training_settings.fec_enable) 2111 fec_enable = *link->preferred_training_settings.fec_enable; 2112 else 2113 fec_enable = true; 2114 2115 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2116 dp_set_fec_enable(link, fec_enable); 2117 2118 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2119 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2120 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2121 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2122 set_default_brightness_aux(link); // TODO: use cached if known 2123 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2124 msleep(bl_oled_enable_delay); 2125 link_backlight_enable_aux(link, true); 2126 } 2127 2128 return status; 2129 } 2130 2131 static enum dc_status enable_link_edp( 2132 struct dc_state *state, 2133 struct pipe_ctx *pipe_ctx) 2134 { 2135 return enable_link_dp(state, pipe_ctx); 2136 } 2137 2138 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2139 { 2140 struct dc_stream_state *stream = pipe_ctx->stream; 2141 struct dc_link *link = stream->link; 2142 struct dc *dc = stream->ctx->dc; 2143 2144 if (stream->phy_pix_clk == 0) 2145 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2146 2147 memset(&stream->link->cur_link_settings, 0, 2148 sizeof(struct dc_link_settings)); 2149 dc->hwss.enable_lvds_link_output( 2150 link, 2151 &pipe_ctx->link_res, 2152 pipe_ctx->clock_source->id, 2153 stream->phy_pix_clk); 2154 2155 } 2156 2157 static enum dc_status enable_link_dp_mst( 2158 struct dc_state *state, 2159 struct pipe_ctx *pipe_ctx) 2160 { 2161 struct dc_link *link = pipe_ctx->stream->link; 2162 2163 /* sink signal type after MST branch is MST. Multiple MST sinks 2164 * share one link. Link DP PHY is enable or training only once. 2165 */ 2166 if (link->link_status.link_active) 2167 return DC_OK; 2168 2169 /* clear payload table */ 2170 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2171 2172 /* to make sure the pending down rep can be processed 2173 * before enabling the link 2174 */ 2175 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2176 2177 /* set the sink to MST mode before enabling the link */ 2178 enable_mst_on_sink(link, true); 2179 2180 return enable_link_dp(state, pipe_ctx); 2181 } 2182 2183 static enum dc_status enable_link( 2184 struct dc_state *state, 2185 struct pipe_ctx *pipe_ctx) 2186 { 2187 enum dc_status status = DC_ERROR_UNEXPECTED; 2188 struct dc_stream_state *stream = pipe_ctx->stream; 2189 struct dc_link *link = stream->link; 2190 2191 /* There's some scenarios where driver is unloaded with display 2192 * still enabled. When driver is reloaded, it may cause a display 2193 * to not light up if there is a mismatch between old and new 2194 * link settings. Need to call disable first before enabling at 2195 * new link settings. 2196 */ 2197 if (link->link_status.link_active) { 2198 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2199 } 2200 2201 switch (pipe_ctx->stream->signal) { 2202 case SIGNAL_TYPE_DISPLAY_PORT: 2203 status = enable_link_dp(state, pipe_ctx); 2204 break; 2205 case SIGNAL_TYPE_EDP: 2206 status = enable_link_edp(state, pipe_ctx); 2207 break; 2208 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2209 status = enable_link_dp_mst(state, pipe_ctx); 2210 msleep(200); 2211 break; 2212 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2213 case SIGNAL_TYPE_DVI_DUAL_LINK: 2214 case SIGNAL_TYPE_HDMI_TYPE_A: 2215 enable_link_hdmi(pipe_ctx); 2216 status = DC_OK; 2217 break; 2218 case SIGNAL_TYPE_LVDS: 2219 enable_link_lvds(pipe_ctx); 2220 status = DC_OK; 2221 break; 2222 case SIGNAL_TYPE_VIRTUAL: 2223 status = DC_OK; 2224 break; 2225 default: 2226 break; 2227 } 2228 2229 if (status == DC_OK) { 2230 pipe_ctx->stream->link->link_status.link_active = true; 2231 } 2232 2233 return status; 2234 } 2235 2236 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2237 { 2238 struct dc *dc = pipe_ctx->stream->ctx->dc; 2239 struct dc_stream_state *stream = pipe_ctx->stream; 2240 struct dc_link *link = stream->sink->link; 2241 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2242 2243 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2244 2245 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2246 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2247 2248 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2249 2250 if (pipe_ctx->stream->sink) { 2251 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2252 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2253 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2254 pipe_ctx->stream->sink->edid_caps.display_name, 2255 pipe_ctx->stream->signal); 2256 } 2257 } 2258 2259 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2260 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2261 return; 2262 2263 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2264 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2265 set_avmute(pipe_ctx, true); 2266 } 2267 2268 dc->hwss.disable_audio_stream(pipe_ctx); 2269 2270 update_psp_stream_config(pipe_ctx, true); 2271 dc->hwss.blank_stream(pipe_ctx); 2272 2273 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2274 deallocate_mst_payload(pipe_ctx); 2275 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2276 link_is_dp_128b_132b_signal(pipe_ctx)) 2277 update_sst_payload(pipe_ctx, false); 2278 2279 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2280 struct ext_hdmi_settings settings = {0}; 2281 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2282 2283 unsigned short masked_chip_caps = link->chip_caps & 2284 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2285 //Need to inform that sink is going to use legacy HDMI mode. 2286 write_scdc_data( 2287 link->ddc, 2288 165000,//vbios only handles 165Mhz. 2289 false); 2290 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2291 /* DP159, Retimer settings */ 2292 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2293 write_i2c_retimer_setting(pipe_ctx, 2294 false, false, &settings); 2295 else 2296 write_i2c_default_retimer_setting(pipe_ctx, 2297 false, false); 2298 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2299 /* PI3EQX1204, Redriver settings */ 2300 write_i2c_redriver_setting(pipe_ctx, false); 2301 } 2302 } 2303 2304 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2305 !link_is_dp_128b_132b_signal(pipe_ctx)) { 2306 2307 /* In DP1.x SST mode, our encoder will go to TPS1 2308 * when link is on but stream is off. 2309 * Disabling link before stream will avoid exposing TPS1 pattern 2310 * during the disable sequence as it will confuse some receivers 2311 * state machine. 2312 * In DP2 or MST mode, our encoder will stay video active 2313 */ 2314 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2315 dc->hwss.disable_stream(pipe_ctx); 2316 } else { 2317 dc->hwss.disable_stream(pipe_ctx); 2318 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2319 } 2320 2321 if (pipe_ctx->stream->timing.flags.DSC) { 2322 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2323 link_set_dsc_enable(pipe_ctx, false); 2324 } 2325 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2326 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2327 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2328 } 2329 2330 if (vpg && vpg->funcs->vpg_powerdown) 2331 vpg->funcs->vpg_powerdown(vpg); 2332 } 2333 2334 void link_set_dpms_on( 2335 struct dc_state *state, 2336 struct pipe_ctx *pipe_ctx) 2337 { 2338 struct dc *dc = pipe_ctx->stream->ctx->dc; 2339 struct dc_stream_state *stream = pipe_ctx->stream; 2340 struct dc_link *link = stream->sink->link; 2341 enum dc_status status; 2342 struct link_encoder *link_enc; 2343 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2344 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2345 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2346 2347 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2348 2349 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2350 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2351 2352 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2353 2354 if (pipe_ctx->stream->sink) { 2355 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2356 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2357 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2358 pipe_ctx->stream->sink->edid_caps.display_name, 2359 pipe_ctx->stream->signal); 2360 } 2361 } 2362 2363 if (!IS_DIAG_DC(dc->ctx->dce_environment) && 2364 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2365 return; 2366 2367 link_enc = link_enc_cfg_get_link_enc(link); 2368 ASSERT(link_enc); 2369 2370 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2371 && !link_is_dp_128b_132b_signal(pipe_ctx)) { 2372 if (link_enc) 2373 link_enc->funcs->setup( 2374 link_enc, 2375 pipe_ctx->stream->signal); 2376 } 2377 2378 pipe_ctx->stream->link->link_state_valid = true; 2379 2380 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2381 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2382 otg_out_dest = OUT_MUX_HPO_DP; 2383 else 2384 otg_out_dest = OUT_MUX_DIO; 2385 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2386 } 2387 2388 link_hwss->setup_stream_attribute(pipe_ctx); 2389 2390 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2391 bool apply_edp_fast_boot_optimization = 2392 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2393 2394 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2395 2396 // Enable VPG before building infoframe 2397 if (vpg && vpg->funcs->vpg_poweron) 2398 vpg->funcs->vpg_poweron(vpg); 2399 2400 resource_build_info_frame(pipe_ctx); 2401 dc->hwss.update_info_frame(pipe_ctx); 2402 2403 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2404 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2405 2406 /* Do not touch link on seamless boot optimization. */ 2407 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2408 pipe_ctx->stream->dpms_off = false; 2409 2410 /* Still enable stream features & audio on seamless boot for DP external displays */ 2411 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2412 enable_stream_features(pipe_ctx); 2413 dc->hwss.enable_audio_stream(pipe_ctx); 2414 } 2415 2416 update_psp_stream_config(pipe_ctx, false); 2417 return; 2418 } 2419 2420 /* eDP lit up by bios already, no need to enable again. */ 2421 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2422 apply_edp_fast_boot_optimization && 2423 !pipe_ctx->stream->timing.flags.DSC && 2424 !pipe_ctx->next_odm_pipe) { 2425 pipe_ctx->stream->dpms_off = false; 2426 update_psp_stream_config(pipe_ctx, false); 2427 return; 2428 } 2429 2430 if (pipe_ctx->stream->dpms_off) 2431 return; 2432 2433 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2434 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2435 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2436 * will be automatically set at a later time when the video is enabled 2437 * (DP_VID_STREAM_EN = 1). 2438 */ 2439 if (pipe_ctx->stream->timing.flags.DSC) { 2440 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2441 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2442 link_set_dsc_enable(pipe_ctx, true); 2443 2444 } 2445 2446 status = enable_link(state, pipe_ctx); 2447 2448 if (status != DC_OK) { 2449 DC_LOG_WARNING("enabling link %u failed: %d\n", 2450 pipe_ctx->stream->link->link_index, 2451 status); 2452 2453 /* Abort stream enable *unless* the failure was due to 2454 * DP link training - some DP monitors will recover and 2455 * show the stream anyway. But MST displays can't proceed 2456 * without link training. 2457 */ 2458 if (status != DC_FAIL_DP_LINK_TRAINING || 2459 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2460 if (false == stream->link->link_status.link_active) 2461 disable_link(stream->link, &pipe_ctx->link_res, 2462 pipe_ctx->stream->signal); 2463 BREAK_TO_DEBUGGER(); 2464 return; 2465 } 2466 } 2467 2468 /* turn off otg test pattern if enable */ 2469 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2470 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2471 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2472 COLOR_DEPTH_UNDEFINED); 2473 2474 /* This second call is needed to reconfigure the DIG 2475 * as a workaround for the incorrect value being applied 2476 * from transmitter control. 2477 */ 2478 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2479 link_is_dp_128b_132b_signal(pipe_ctx))) 2480 if (link_enc) 2481 link_enc->funcs->setup( 2482 link_enc, 2483 pipe_ctx->stream->signal); 2484 2485 dc->hwss.enable_stream(pipe_ctx); 2486 2487 /* Set DPS PPS SDP (AKA "info frames") */ 2488 if (pipe_ctx->stream->timing.flags.DSC) { 2489 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2490 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2491 dp_set_dsc_on_rx(pipe_ctx, true); 2492 link_set_dsc_pps_packet(pipe_ctx, true, true); 2493 } 2494 } 2495 2496 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2497 allocate_mst_payload(pipe_ctx); 2498 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2499 link_is_dp_128b_132b_signal(pipe_ctx)) 2500 update_sst_payload(pipe_ctx, true); 2501 2502 dc->hwss.unblank_stream(pipe_ctx, 2503 &pipe_ctx->stream->link->cur_link_settings); 2504 2505 if (stream->sink_patches.delay_ignore_msa > 0) 2506 msleep(stream->sink_patches.delay_ignore_msa); 2507 2508 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2509 enable_stream_features(pipe_ctx); 2510 update_psp_stream_config(pipe_ctx, false); 2511 2512 dc->hwss.enable_audio_stream(pipe_ctx); 2513 2514 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 2515 if (link_is_dp_128b_132b_signal(pipe_ctx)) 2516 dp_fpga_hpo_enable_link_and_stream(state, pipe_ctx); 2517 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2518 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2519 link_set_dsc_enable(pipe_ctx, true); 2520 } 2521 2522 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2523 set_avmute(pipe_ctx, false); 2524 } 2525 } 2526