1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_fpga.h" 42 #include "accessories/link_dp_trace.h" 43 #include "protocols/link_dpcd.h" 44 #include "protocols/link_ddc.h" 45 #include "protocols/link_hpd.h" 46 #include "protocols/link_dp_phy.h" 47 #include "protocols/link_dp_capability.h" 48 #include "protocols/link_dp_training.h" 49 #include "protocols/link_edp_panel_control.h" 50 #include "protocols/link_dp_dpia_bw.h" 51 52 #include "dm_helpers.h" 53 #include "link_enc_cfg.h" 54 #include "resource.h" 55 #include "dsc.h" 56 #include "dccg.h" 57 #include "clk_mgr.h" 58 #include "atomfirmware.h" 59 #define DC_LOGGER_INIT(logger) 60 61 #define LINK_INFO(...) \ 62 DC_LOG_HW_HOTPLUG( \ 63 __VA_ARGS__) 64 65 #define RETIMER_REDRIVER_INFO(...) \ 66 DC_LOG_RETIMER_REDRIVER( \ 67 __VA_ARGS__) 68 #include "dc/dcn30/dcn30_vpg.h" 69 70 #define MAX_MTP_SLOT_COUNT 64 71 #define LINK_TRAINING_ATTEMPTS 4 72 #define PEAK_FACTOR_X1000 1006 73 74 void link_blank_all_dp_displays(struct dc *dc) 75 { 76 unsigned int i; 77 uint8_t dpcd_power_state = '\0'; 78 enum dc_status status = DC_ERROR_UNEXPECTED; 79 80 for (i = 0; i < dc->link_count; i++) { 81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 83 continue; 84 85 /* DP 2.0 spec requires that we read LTTPR caps first */ 86 dp_retrieve_lttpr_cap(dc->links[i]); 87 /* if any of the displays are lit up turn them off */ 88 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 89 &dpcd_power_state, sizeof(dpcd_power_state)); 90 91 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 92 link_blank_dp_stream(dc->links[i], true); 93 } 94 95 } 96 97 void link_blank_all_edp_displays(struct dc *dc) 98 { 99 unsigned int i; 100 uint8_t dpcd_power_state = '\0'; 101 enum dc_status status = DC_ERROR_UNEXPECTED; 102 103 for (i = 0; i < dc->link_count; i++) { 104 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 105 (!dc->links[i]->edp_sink_present)) 106 continue; 107 108 /* if any of the displays are lit up turn them off */ 109 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 110 &dpcd_power_state, sizeof(dpcd_power_state)); 111 112 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 113 link_blank_dp_stream(dc->links[i], true); 114 } 115 } 116 117 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 118 { 119 unsigned int j; 120 struct dc *dc = link->ctx->dc; 121 enum signal_type signal = link->connector_signal; 122 123 if ((signal == SIGNAL_TYPE_EDP) || 124 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 125 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 126 link->link_enc->funcs->get_dig_frontend && 127 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 128 unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 129 130 if (fe != ENGINE_ID_UNKNOWN) 131 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 132 if (fe == dc->res_pool->stream_enc[j]->id) { 133 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 134 dc->res_pool->stream_enc[j]); 135 break; 136 } 137 } 138 } 139 140 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 141 dpcd_write_rx_power_ctrl(link, false); 142 } 143 } 144 145 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 146 { 147 struct pipe_ctx *pipes[MAX_PIPES]; 148 struct dc_state *state = link->dc->current_state; 149 uint8_t count; 150 int i; 151 struct dc_stream_update stream_update; 152 bool dpms_off = true; 153 struct link_resource link_res = {0}; 154 155 memset(&stream_update, 0, sizeof(stream_update)); 156 stream_update.dpms_off = &dpms_off; 157 158 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 159 160 for (i = 0; i < count; i++) { 161 stream_update.stream = pipes[i]->stream; 162 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 163 pipes[i]->stream, &stream_update, 164 state); 165 } 166 167 /* link can be also enabled by vbios. In this case it is not recorded 168 * in pipe_ctx. Disable link phy here to make sure it is completely off 169 */ 170 dp_disable_link_phy(link, &link_res, link->connector_signal); 171 } 172 173 void link_resume(struct dc_link *link) 174 { 175 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 176 program_hpd_filter(link); 177 } 178 179 /* This function returns true if the pipe is used to feed video signal directly 180 * to the link. 181 */ 182 static bool is_master_pipe_for_link(const struct dc_link *link, 183 const struct pipe_ctx *pipe) 184 { 185 return (pipe->stream && 186 pipe->stream->link && 187 pipe->stream->link == link && 188 pipe->top_pipe == NULL && 189 pipe->prev_odm_pipe == NULL); 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = NULL; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 776 * i.e. after dp_enable_dsc_on_rx() had been called 777 */ 778 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 779 { 780 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 781 struct dc_stream_state *stream = pipe_ctx->stream; 782 struct pipe_ctx *odm_pipe; 783 int opp_cnt = 1; 784 DC_LOGGER_INIT(dsc->ctx->logger); 785 786 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 787 opp_cnt++; 788 789 if (enable) { 790 struct dsc_config dsc_cfg; 791 struct dsc_optc_config dsc_optc_cfg; 792 enum optc_dsc_mode optc_dsc_mode; 793 794 /* Enable DSC hw block */ 795 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 796 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 797 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 798 dsc_cfg.color_depth = stream->timing.display_color_depth; 799 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 800 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 801 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 802 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 803 804 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 805 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 806 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 807 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 808 809 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 810 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 811 } 812 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 813 dsc_cfg.pic_width *= opp_cnt; 814 815 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 816 817 /* Enable DSC in encoder */ 818 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 819 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 820 dsc_optc_config_log(dsc, &dsc_optc_cfg); 821 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 822 optc_dsc_mode, 823 dsc_optc_cfg.bytes_per_pixel, 824 dsc_optc_cfg.slice_width); 825 826 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 827 } 828 829 /* Enable DSC in OPTC */ 830 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 831 dsc_optc_config_log(dsc, &dsc_optc_cfg); 832 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 833 optc_dsc_mode, 834 dsc_optc_cfg.bytes_per_pixel, 835 dsc_optc_cfg.slice_width); 836 } else { 837 /* disable DSC in OPTC */ 838 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 839 pipe_ctx->stream_res.tg, 840 OPTC_DSC_DISABLED, 0, 0); 841 842 /* disable DSC in stream encoder */ 843 if (dc_is_dp_signal(stream->signal)) { 844 if (dp_is_128b_132b_signal(pipe_ctx)) 845 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 846 pipe_ctx->stream_res.hpo_dp_stream_enc, 847 false, 848 NULL, 849 true); 850 else { 851 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 852 pipe_ctx->stream_res.stream_enc, 853 OPTC_DSC_DISABLED, 0, 0); 854 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 855 pipe_ctx->stream_res.stream_enc, false, NULL, true); 856 } 857 } 858 859 /* disable DSC block */ 860 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 861 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 862 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 863 } 864 } 865 866 /* 867 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 868 * hence PPS info packet update need to use frame update instead of immediate update. 869 * Added parameter immediate_update for this purpose. 870 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 871 * which is the only place where a "false" would be passed in for param immediate_update. 872 * 873 * immediate_update is only applicable when DSC is enabled. 874 */ 875 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 876 { 877 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 878 struct dc_stream_state *stream = pipe_ctx->stream; 879 DC_LOGGER_INIT(dsc->ctx->logger); 880 881 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) 882 return false; 883 884 if (enable) { 885 struct dsc_config dsc_cfg; 886 uint8_t dsc_packed_pps[128]; 887 888 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 889 memset(dsc_packed_pps, 0, 128); 890 891 /* Enable DSC hw block */ 892 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 893 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 894 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 895 dsc_cfg.color_depth = stream->timing.display_color_depth; 896 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 897 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 898 899 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 900 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 901 if (dc_is_dp_signal(stream->signal)) { 902 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 903 if (dp_is_128b_132b_signal(pipe_ctx)) 904 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 905 pipe_ctx->stream_res.hpo_dp_stream_enc, 906 true, 907 &dsc_packed_pps[0], 908 immediate_update); 909 else 910 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 911 pipe_ctx->stream_res.stream_enc, 912 true, 913 &dsc_packed_pps[0], 914 immediate_update); 915 } 916 } else { 917 /* disable DSC PPS in stream encoder */ 918 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 919 if (dc_is_dp_signal(stream->signal)) { 920 if (dp_is_128b_132b_signal(pipe_ctx)) 921 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 922 pipe_ctx->stream_res.hpo_dp_stream_enc, 923 false, 924 NULL, 925 true); 926 else 927 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 928 pipe_ctx->stream_res.stream_enc, false, NULL, true); 929 } 930 } 931 932 return true; 933 } 934 935 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 936 { 937 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 938 bool result = false; 939 940 if (!pipe_ctx->stream->timing.flags.DSC) 941 goto out; 942 if (!dsc) 943 goto out; 944 945 if (enable) { 946 { 947 link_set_dsc_on_stream(pipe_ctx, true); 948 result = true; 949 } 950 } else { 951 dp_set_dsc_on_rx(pipe_ctx, false); 952 link_set_dsc_on_stream(pipe_ctx, false); 953 result = true; 954 } 955 out: 956 return result; 957 } 958 959 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 960 { 961 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 962 963 if (!pipe_ctx->stream->timing.flags.DSC) 964 return false; 965 if (!dsc) 966 return false; 967 968 link_set_dsc_on_stream(pipe_ctx, true); 969 link_set_dsc_pps_packet(pipe_ctx, true, false); 970 return true; 971 } 972 973 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 974 { 975 struct dc_stream_state *stream = pipe_ctx->stream; 976 977 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 978 struct dc_link *link = stream->link; 979 union down_spread_ctrl old_downspread; 980 union down_spread_ctrl new_downspread; 981 982 memset(&old_downspread, 0, sizeof(old_downspread)); 983 984 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 985 &old_downspread.raw, sizeof(old_downspread)); 986 987 new_downspread.raw = old_downspread.raw; 988 989 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 990 (stream->ignore_msa_timing_param) ? 1 : 0; 991 992 if (new_downspread.raw != old_downspread.raw) { 993 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 994 &new_downspread.raw, sizeof(new_downspread)); 995 } 996 997 } else { 998 dm_helpers_mst_enable_stream_features(stream); 999 } 1000 } 1001 1002 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1003 { 1004 const uint32_t VCP_Y_PRECISION = 1000; 1005 uint64_t vcp_x, vcp_y; 1006 DC_LOGGER_INIT(link->ctx->logger); 1007 1008 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1009 avg_time_slots_per_mtp = dc_fixpt_add( 1010 avg_time_slots_per_mtp, 1011 dc_fixpt_from_fraction( 1012 1, 1013 2*VCP_Y_PRECISION)); 1014 1015 vcp_x = dc_fixpt_floor( 1016 avg_time_slots_per_mtp); 1017 vcp_y = dc_fixpt_floor( 1018 dc_fixpt_mul_int( 1019 dc_fixpt_sub_int( 1020 avg_time_slots_per_mtp, 1021 dc_fixpt_floor( 1022 avg_time_slots_per_mtp)), 1023 VCP_Y_PRECISION)); 1024 1025 1026 if (link->type == dc_connection_mst_branch) 1027 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1028 "X: %llu " 1029 "Y: %llu/%d", 1030 vcp_x, 1031 vcp_y, 1032 VCP_Y_PRECISION); 1033 else 1034 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1035 "X: %llu " 1036 "Y: %llu/%d", 1037 vcp_x, 1038 vcp_y, 1039 VCP_Y_PRECISION); 1040 } 1041 1042 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1043 { 1044 struct fixed31_32 mbytes_per_sec; 1045 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1046 &stream->link->cur_link_settings); 1047 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1048 1049 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1050 1051 return dc_fixpt_div_int(mbytes_per_sec, 54); 1052 } 1053 1054 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1055 { 1056 struct fixed31_32 peak_kbps; 1057 uint32_t numerator = 0; 1058 uint32_t denominator = 1; 1059 1060 /* 1061 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 1062 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1063 * common multiplier to render an integer PBN for all link rate/lane 1064 * counts combinations 1065 * calculate 1066 * peak_kbps *= (1006/1000) 1067 * peak_kbps *= (64/54) 1068 * peak_kbps *= 8 convert to bytes 1069 */ 1070 1071 numerator = 64 * PEAK_FACTOR_X1000; 1072 denominator = 54 * 8 * 1000 * 1000; 1073 kbps *= numerator; 1074 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1075 1076 return peak_kbps; 1077 } 1078 1079 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1080 { 1081 uint64_t kbps; 1082 1083 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 1084 return get_pbn_from_bw_in_kbps(kbps); 1085 } 1086 1087 1088 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1089 static void get_lane_status( 1090 struct dc_link *link, 1091 uint32_t lane_count, 1092 union lane_status *status, 1093 union lane_align_status_updated *status_updated) 1094 { 1095 unsigned int lane; 1096 uint8_t dpcd_buf[3] = {0}; 1097 1098 if (status == NULL || status_updated == NULL) { 1099 return; 1100 } 1101 1102 core_link_read_dpcd( 1103 link, 1104 DP_LANE0_1_STATUS, 1105 dpcd_buf, 1106 sizeof(dpcd_buf)); 1107 1108 for (lane = 0; lane < lane_count; lane++) { 1109 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1110 } 1111 1112 status_updated->raw = dpcd_buf[2]; 1113 } 1114 1115 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1116 { 1117 /* 1118 * wait for ACT handled 1119 */ 1120 int i; 1121 const int act_retries = 30; 1122 enum act_return_status result = ACT_FAILED; 1123 union payload_table_update_status update_status = {0}; 1124 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1125 union lane_align_status_updated lane_status_updated; 1126 DC_LOGGER_INIT(link->ctx->logger); 1127 1128 if (link->aux_access_disabled) 1129 return true; 1130 for (i = 0; i < act_retries; i++) { 1131 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1132 1133 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1134 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1135 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1136 !dp_is_interlane_aligned(lane_status_updated)) { 1137 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1138 "polling for ACT handled."); 1139 result = ACT_LINK_LOST; 1140 break; 1141 } 1142 core_link_read_dpcd( 1143 link, 1144 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1145 &update_status.raw, 1146 1); 1147 1148 if (update_status.bits.ACT_HANDLED == 1) { 1149 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1150 result = ACT_SUCCESS; 1151 break; 1152 } 1153 1154 fsleep(5000); 1155 } 1156 1157 if (result == ACT_FAILED) { 1158 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1159 "continue on. Something is wrong with the branch."); 1160 } 1161 1162 return (result == ACT_SUCCESS); 1163 } 1164 1165 static void update_mst_stream_alloc_table( 1166 struct dc_link *link, 1167 struct stream_encoder *stream_enc, 1168 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1169 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1170 { 1171 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1172 struct link_mst_stream_allocation *dc_alloc; 1173 1174 int i; 1175 int j; 1176 1177 /* if DRM proposed_table has more than one new payload */ 1178 ASSERT(proposed_table->stream_count - 1179 link->mst_stream_alloc_table.stream_count < 2); 1180 1181 /* copy proposed_table to link, add stream encoder */ 1182 for (i = 0; i < proposed_table->stream_count; i++) { 1183 1184 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1185 dc_alloc = 1186 &link->mst_stream_alloc_table.stream_allocations[j]; 1187 1188 if (dc_alloc->vcp_id == 1189 proposed_table->stream_allocations[i].vcp_id) { 1190 1191 work_table[i] = *dc_alloc; 1192 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1193 break; /* exit j loop */ 1194 } 1195 } 1196 1197 /* new vcp_id */ 1198 if (j == link->mst_stream_alloc_table.stream_count) { 1199 work_table[i].vcp_id = 1200 proposed_table->stream_allocations[i].vcp_id; 1201 work_table[i].slot_count = 1202 proposed_table->stream_allocations[i].slot_count; 1203 work_table[i].stream_enc = stream_enc; 1204 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1205 } 1206 } 1207 1208 /* update link->mst_stream_alloc_table with work_table */ 1209 link->mst_stream_alloc_table.stream_count = 1210 proposed_table->stream_count; 1211 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1212 link->mst_stream_alloc_table.stream_allocations[i] = 1213 work_table[i]; 1214 } 1215 1216 static void remove_stream_from_alloc_table( 1217 struct dc_link *link, 1218 struct stream_encoder *dio_stream_enc, 1219 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1220 { 1221 int i = 0; 1222 struct link_mst_stream_allocation_table *table = 1223 &link->mst_stream_alloc_table; 1224 1225 if (hpo_dp_stream_enc) { 1226 for (; i < table->stream_count; i++) 1227 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1228 break; 1229 } else { 1230 for (; i < table->stream_count; i++) 1231 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1232 break; 1233 } 1234 1235 if (i < table->stream_count) { 1236 i++; 1237 for (; i < table->stream_count; i++) 1238 table->stream_allocations[i-1] = table->stream_allocations[i]; 1239 memset(&table->stream_allocations[table->stream_count-1], 0, 1240 sizeof(struct link_mst_stream_allocation)); 1241 table->stream_count--; 1242 } 1243 } 1244 1245 static enum dc_status deallocate_mst_payload_with_temp_drm_wa( 1246 struct pipe_ctx *pipe_ctx) 1247 { 1248 struct dc_stream_state *stream = pipe_ctx->stream; 1249 struct dc_link *link = stream->link; 1250 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1251 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1252 int i; 1253 bool mst_mode = (link->type == dc_connection_mst_branch); 1254 /* adjust for drm changes*/ 1255 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1256 const struct dc_link_settings empty_link_settings = {0}; 1257 DC_LOGGER_INIT(link->ctx->logger); 1258 1259 if (link_hwss->ext.set_throttled_vcp_size) 1260 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1261 if (link_hwss->ext.set_hblank_min_symbol_width) 1262 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1263 &empty_link_settings, 1264 avg_time_slots_per_mtp); 1265 1266 if (dm_helpers_dp_mst_write_payload_allocation_table( 1267 stream->ctx, 1268 stream, 1269 &proposed_table, 1270 false)) 1271 update_mst_stream_alloc_table( 1272 link, 1273 pipe_ctx->stream_res.stream_enc, 1274 pipe_ctx->stream_res.hpo_dp_stream_enc, 1275 &proposed_table); 1276 else 1277 DC_LOG_WARNING("Failed to update" 1278 "MST allocation table for" 1279 "pipe idx:%d\n", 1280 pipe_ctx->pipe_idx); 1281 1282 DC_LOG_MST("%s" 1283 "stream_count: %d: ", 1284 __func__, 1285 link->mst_stream_alloc_table.stream_count); 1286 1287 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1288 DC_LOG_MST("stream_enc[%d]: %p " 1289 "stream[%d].hpo_dp_stream_enc: %p " 1290 "stream[%d].vcp_id: %d " 1291 "stream[%d].slot_count: %d\n", 1292 i, 1293 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1294 i, 1295 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1296 i, 1297 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1298 i, 1299 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1300 } 1301 1302 if (link_hwss->ext.update_stream_allocation_table == NULL || 1303 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1304 DC_LOG_DEBUG("Unknown encoding format\n"); 1305 return DC_ERROR_UNEXPECTED; 1306 } 1307 1308 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1309 &link->mst_stream_alloc_table); 1310 1311 if (mst_mode) { 1312 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1313 stream->ctx, 1314 stream); 1315 } 1316 1317 dm_helpers_dp_mst_send_payload_allocation( 1318 stream->ctx, 1319 stream, 1320 false); 1321 1322 return DC_OK; 1323 } 1324 1325 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1326 { 1327 struct dc_stream_state *stream = pipe_ctx->stream; 1328 struct dc_link *link = stream->link; 1329 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1330 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1331 int i; 1332 bool mst_mode = (link->type == dc_connection_mst_branch); 1333 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1334 const struct dc_link_settings empty_link_settings = {0}; 1335 DC_LOGGER_INIT(link->ctx->logger); 1336 1337 if (link->dc->debug.temp_mst_deallocation_sequence) 1338 return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); 1339 1340 /* deallocate_mst_payload is called before disable link. When mode or 1341 * disable/enable monitor, new stream is created which is not in link 1342 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1343 * should not done. For new mode set, map_resources will get engine 1344 * for new stream, so stream_enc->id should be validated until here. 1345 */ 1346 1347 /* slot X.Y */ 1348 if (link_hwss->ext.set_throttled_vcp_size) 1349 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1350 if (link_hwss->ext.set_hblank_min_symbol_width) 1351 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1352 &empty_link_settings, 1353 avg_time_slots_per_mtp); 1354 1355 if (mst_mode) { 1356 /* when link is in mst mode, reply on mst manager to remove 1357 * payload 1358 */ 1359 if (dm_helpers_dp_mst_write_payload_allocation_table( 1360 stream->ctx, 1361 stream, 1362 &proposed_table, 1363 false)) 1364 update_mst_stream_alloc_table( 1365 link, 1366 pipe_ctx->stream_res.stream_enc, 1367 pipe_ctx->stream_res.hpo_dp_stream_enc, 1368 &proposed_table); 1369 else 1370 DC_LOG_WARNING("Failed to update" 1371 "MST allocation table for" 1372 "pipe idx:%d\n", 1373 pipe_ctx->pipe_idx); 1374 } else { 1375 /* when link is no longer in mst mode (mst hub unplugged), 1376 * remove payload with default dc logic 1377 */ 1378 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1379 pipe_ctx->stream_res.hpo_dp_stream_enc); 1380 } 1381 1382 DC_LOG_MST("%s" 1383 "stream_count: %d: ", 1384 __func__, 1385 link->mst_stream_alloc_table.stream_count); 1386 1387 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1388 DC_LOG_MST("stream_enc[%d]: %p " 1389 "stream[%d].hpo_dp_stream_enc: %p " 1390 "stream[%d].vcp_id: %d " 1391 "stream[%d].slot_count: %d\n", 1392 i, 1393 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1394 i, 1395 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1396 i, 1397 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1398 i, 1399 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1400 } 1401 1402 /* update mst stream allocation table hardware state */ 1403 if (link_hwss->ext.update_stream_allocation_table == NULL || 1404 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1405 DC_LOG_DEBUG("Unknown encoding format\n"); 1406 return DC_ERROR_UNEXPECTED; 1407 } 1408 1409 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1410 &link->mst_stream_alloc_table); 1411 1412 if (mst_mode) { 1413 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1414 stream->ctx, 1415 stream); 1416 1417 dm_helpers_dp_mst_send_payload_allocation( 1418 stream->ctx, 1419 stream, 1420 false); 1421 } 1422 1423 return DC_OK; 1424 } 1425 1426 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1427 * because stream_encoder is not exposed to dm 1428 */ 1429 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1430 { 1431 struct dc_stream_state *stream = pipe_ctx->stream; 1432 struct dc_link *link = stream->link; 1433 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1434 struct fixed31_32 avg_time_slots_per_mtp; 1435 struct fixed31_32 pbn; 1436 struct fixed31_32 pbn_per_slot; 1437 int i; 1438 enum act_return_status ret; 1439 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1440 DC_LOGGER_INIT(link->ctx->logger); 1441 1442 /* enable_link_dp_mst already check link->enabled_stream_count 1443 * and stream is in link->stream[]. This is called during set mode, 1444 * stream_enc is available. 1445 */ 1446 1447 /* get calculate VC payload for stream: stream_alloc */ 1448 if (dm_helpers_dp_mst_write_payload_allocation_table( 1449 stream->ctx, 1450 stream, 1451 &proposed_table, 1452 true)) 1453 update_mst_stream_alloc_table( 1454 link, 1455 pipe_ctx->stream_res.stream_enc, 1456 pipe_ctx->stream_res.hpo_dp_stream_enc, 1457 &proposed_table); 1458 else 1459 DC_LOG_WARNING("Failed to update" 1460 "MST allocation table for" 1461 "pipe idx:%d\n", 1462 pipe_ctx->pipe_idx); 1463 1464 DC_LOG_MST("%s " 1465 "stream_count: %d: \n ", 1466 __func__, 1467 link->mst_stream_alloc_table.stream_count); 1468 1469 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1470 DC_LOG_MST("stream_enc[%d]: %p " 1471 "stream[%d].hpo_dp_stream_enc: %p " 1472 "stream[%d].vcp_id: %d " 1473 "stream[%d].slot_count: %d\n", 1474 i, 1475 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1476 i, 1477 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1478 i, 1479 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1480 i, 1481 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1482 } 1483 1484 ASSERT(proposed_table.stream_count > 0); 1485 1486 /* program DP source TX for payload */ 1487 if (link_hwss->ext.update_stream_allocation_table == NULL || 1488 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1489 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1490 return DC_ERROR_UNEXPECTED; 1491 } 1492 1493 link_hwss->ext.update_stream_allocation_table(link, 1494 &pipe_ctx->link_res, 1495 &link->mst_stream_alloc_table); 1496 1497 /* send down message */ 1498 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1499 stream->ctx, 1500 stream); 1501 1502 if (ret != ACT_LINK_LOST) { 1503 dm_helpers_dp_mst_send_payload_allocation( 1504 stream->ctx, 1505 stream, 1506 true); 1507 } 1508 1509 /* slot X.Y for only current stream */ 1510 pbn_per_slot = get_pbn_per_slot(stream); 1511 if (pbn_per_slot.value == 0) { 1512 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1513 return DC_UNSUPPORTED_VALUE; 1514 } 1515 pbn = get_pbn_from_timing(pipe_ctx); 1516 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1517 1518 log_vcp_x_y(link, avg_time_slots_per_mtp); 1519 1520 if (link_hwss->ext.set_throttled_vcp_size) 1521 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1522 if (link_hwss->ext.set_hblank_min_symbol_width) 1523 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1524 &link->cur_link_settings, 1525 avg_time_slots_per_mtp); 1526 1527 return DC_OK; 1528 } 1529 1530 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1531 const struct dc_stream_state *stream, 1532 const struct dc_link *link) 1533 { 1534 struct fixed31_32 link_bw_effective = 1535 dc_fixpt_from_int( 1536 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1537 struct fixed31_32 timeslot_bw_effective = 1538 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1539 struct fixed31_32 timing_bw = 1540 dc_fixpt_from_int( 1541 dc_bandwidth_in_kbps_from_timing(&stream->timing)); 1542 struct fixed31_32 avg_time_slots_per_mtp = 1543 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1544 1545 return avg_time_slots_per_mtp; 1546 } 1547 1548 1549 static bool write_128b_132b_sst_payload_allocation_table( 1550 const struct dc_stream_state *stream, 1551 struct dc_link *link, 1552 struct link_mst_stream_allocation_table *proposed_table, 1553 bool allocate) 1554 { 1555 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1556 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1557 bool result = false; 1558 uint8_t req_slot_count = 0; 1559 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1560 union payload_table_update_status update_status = { 0 }; 1561 const uint32_t max_retries = 30; 1562 uint32_t retries = 0; 1563 DC_LOGGER_INIT(link->ctx->logger); 1564 1565 if (allocate) { 1566 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1567 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1568 /// Validation should filter out modes that exceed link BW 1569 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1570 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1571 return false; 1572 } else { 1573 /// Leave req_slot_count = 0 if allocate is false. 1574 } 1575 1576 proposed_table->stream_count = 1; /// Always 1 stream for SST 1577 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1578 proposed_table->stream_allocations[0].vcp_id = vc_id; 1579 1580 if (link->aux_access_disabled) 1581 return true; 1582 1583 /// Write DPCD 2C0 = 1 to start updating 1584 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1585 core_link_write_dpcd( 1586 link, 1587 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1588 &update_status.raw, 1589 1); 1590 1591 /// Program the changes in DPCD 1C0 - 1C2 1592 ASSERT(vc_id == 1); 1593 core_link_write_dpcd( 1594 link, 1595 DP_PAYLOAD_ALLOCATE_SET, 1596 &vc_id, 1597 1); 1598 1599 ASSERT(start_time_slot == 0); 1600 core_link_write_dpcd( 1601 link, 1602 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1603 &start_time_slot, 1604 1); 1605 1606 core_link_write_dpcd( 1607 link, 1608 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1609 &req_slot_count, 1610 1); 1611 1612 /// Poll till DPCD 2C0 read 1 1613 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1614 1615 while (retries < max_retries) { 1616 if (core_link_read_dpcd( 1617 link, 1618 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1619 &update_status.raw, 1620 1) == DC_OK) { 1621 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1622 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1623 result = true; 1624 break; 1625 } 1626 } else { 1627 union dpcd_rev dpcdRev; 1628 1629 if (core_link_read_dpcd( 1630 link, 1631 DP_DPCD_REV, 1632 &dpcdRev.raw, 1633 1) != DC_OK) { 1634 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1635 "of sink while polling payload table " 1636 "updated status bit."); 1637 break; 1638 } 1639 } 1640 retries++; 1641 fsleep(5000); 1642 } 1643 1644 if (!result && retries == max_retries) { 1645 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1646 "continue on. Something is wrong with the branch."); 1647 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1648 } 1649 1650 return result; 1651 } 1652 1653 /* 1654 * Payload allocation/deallocation for SST introduced in DP2.0 1655 */ 1656 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1657 bool allocate) 1658 { 1659 struct dc_stream_state *stream = pipe_ctx->stream; 1660 struct dc_link *link = stream->link; 1661 struct link_mst_stream_allocation_table proposed_table = {0}; 1662 struct fixed31_32 avg_time_slots_per_mtp; 1663 const struct dc_link_settings empty_link_settings = {0}; 1664 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1665 DC_LOGGER_INIT(link->ctx->logger); 1666 1667 /* slot X.Y for SST payload deallocate */ 1668 if (!allocate) { 1669 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1670 1671 log_vcp_x_y(link, avg_time_slots_per_mtp); 1672 1673 if (link_hwss->ext.set_throttled_vcp_size) 1674 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1675 avg_time_slots_per_mtp); 1676 if (link_hwss->ext.set_hblank_min_symbol_width) 1677 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1678 &empty_link_settings, 1679 avg_time_slots_per_mtp); 1680 } 1681 1682 /* calculate VC payload and update branch with new payload allocation table*/ 1683 if (!write_128b_132b_sst_payload_allocation_table( 1684 stream, 1685 link, 1686 &proposed_table, 1687 allocate)) { 1688 DC_LOG_ERROR("SST Update Payload: Failed to update " 1689 "allocation table for " 1690 "pipe idx: %d\n", 1691 pipe_ctx->pipe_idx); 1692 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1693 } 1694 1695 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1696 1697 ASSERT(proposed_table.stream_count == 1); 1698 1699 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1700 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1701 "vcp_id: %d " 1702 "slot_count: %d\n", 1703 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1704 proposed_table.stream_allocations[0].vcp_id, 1705 proposed_table.stream_allocations[0].slot_count); 1706 1707 /* program DP source TX for payload */ 1708 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1709 &proposed_table); 1710 1711 /* poll for ACT handled */ 1712 if (!poll_for_allocation_change_trigger(link)) { 1713 // Failures will result in blackscreen and errors logged 1714 BREAK_TO_DEBUGGER(); 1715 } 1716 1717 /* slot X.Y for SST payload allocate */ 1718 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1719 DP_128b_132b_ENCODING) { 1720 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1721 1722 log_vcp_x_y(link, avg_time_slots_per_mtp); 1723 1724 if (link_hwss->ext.set_throttled_vcp_size) 1725 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1726 avg_time_slots_per_mtp); 1727 if (link_hwss->ext.set_hblank_min_symbol_width) 1728 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1729 &link->cur_link_settings, 1730 avg_time_slots_per_mtp); 1731 } 1732 1733 /* Always return DC_OK. 1734 * If part of sequence fails, log failure(s) and show blackscreen 1735 */ 1736 return DC_OK; 1737 } 1738 1739 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1740 { 1741 struct dc_stream_state *stream = pipe_ctx->stream; 1742 struct dc_link *link = stream->link; 1743 struct fixed31_32 avg_time_slots_per_mtp; 1744 struct fixed31_32 pbn; 1745 struct fixed31_32 pbn_per_slot; 1746 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1747 uint8_t i; 1748 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1749 DC_LOGGER_INIT(link->ctx->logger); 1750 1751 /* decrease throttled vcp size */ 1752 pbn_per_slot = get_pbn_per_slot(stream); 1753 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1754 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1755 1756 if (link_hwss->ext.set_throttled_vcp_size) 1757 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1758 if (link_hwss->ext.set_hblank_min_symbol_width) 1759 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1760 &link->cur_link_settings, 1761 avg_time_slots_per_mtp); 1762 1763 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1764 dm_helpers_dp_mst_send_payload_allocation( 1765 stream->ctx, 1766 stream, 1767 true); 1768 1769 /* notify immediate branch device table update */ 1770 if (dm_helpers_dp_mst_write_payload_allocation_table( 1771 stream->ctx, 1772 stream, 1773 &proposed_table, 1774 true)) { 1775 /* update mst stream allocation table software state */ 1776 update_mst_stream_alloc_table( 1777 link, 1778 pipe_ctx->stream_res.stream_enc, 1779 pipe_ctx->stream_res.hpo_dp_stream_enc, 1780 &proposed_table); 1781 } else { 1782 DC_LOG_WARNING("Failed to update" 1783 "MST allocation table for" 1784 "pipe idx:%d\n", 1785 pipe_ctx->pipe_idx); 1786 } 1787 1788 DC_LOG_MST("%s " 1789 "stream_count: %d: \n ", 1790 __func__, 1791 link->mst_stream_alloc_table.stream_count); 1792 1793 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1794 DC_LOG_MST("stream_enc[%d]: %p " 1795 "stream[%d].hpo_dp_stream_enc: %p " 1796 "stream[%d].vcp_id: %d " 1797 "stream[%d].slot_count: %d\n", 1798 i, 1799 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1800 i, 1801 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1802 i, 1803 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1804 i, 1805 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1806 } 1807 1808 ASSERT(proposed_table.stream_count > 0); 1809 1810 /* update mst stream allocation table hardware state */ 1811 if (link_hwss->ext.update_stream_allocation_table == NULL || 1812 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1813 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1814 return DC_ERROR_UNEXPECTED; 1815 } 1816 1817 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1818 &link->mst_stream_alloc_table); 1819 1820 /* poll for immediate branch device ACT handled */ 1821 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1822 stream->ctx, 1823 stream); 1824 1825 return DC_OK; 1826 } 1827 1828 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1829 { 1830 struct dc_stream_state *stream = pipe_ctx->stream; 1831 struct dc_link *link = stream->link; 1832 struct fixed31_32 avg_time_slots_per_mtp; 1833 struct fixed31_32 pbn; 1834 struct fixed31_32 pbn_per_slot; 1835 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1836 uint8_t i; 1837 enum act_return_status ret; 1838 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1839 DC_LOGGER_INIT(link->ctx->logger); 1840 1841 /* notify immediate branch device table update */ 1842 if (dm_helpers_dp_mst_write_payload_allocation_table( 1843 stream->ctx, 1844 stream, 1845 &proposed_table, 1846 true)) { 1847 /* update mst stream allocation table software state */ 1848 update_mst_stream_alloc_table( 1849 link, 1850 pipe_ctx->stream_res.stream_enc, 1851 pipe_ctx->stream_res.hpo_dp_stream_enc, 1852 &proposed_table); 1853 } 1854 1855 DC_LOG_MST("%s " 1856 "stream_count: %d: \n ", 1857 __func__, 1858 link->mst_stream_alloc_table.stream_count); 1859 1860 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1861 DC_LOG_MST("stream_enc[%d]: %p " 1862 "stream[%d].hpo_dp_stream_enc: %p " 1863 "stream[%d].vcp_id: %d " 1864 "stream[%d].slot_count: %d\n", 1865 i, 1866 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1867 i, 1868 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1869 i, 1870 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1871 i, 1872 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1873 } 1874 1875 ASSERT(proposed_table.stream_count > 0); 1876 1877 /* update mst stream allocation table hardware state */ 1878 if (link_hwss->ext.update_stream_allocation_table == NULL || 1879 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1880 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1881 return DC_ERROR_UNEXPECTED; 1882 } 1883 1884 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1885 &link->mst_stream_alloc_table); 1886 1887 /* poll for immediate branch device ACT handled */ 1888 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1889 stream->ctx, 1890 stream); 1891 1892 if (ret != ACT_LINK_LOST) { 1893 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1894 dm_helpers_dp_mst_send_payload_allocation( 1895 stream->ctx, 1896 stream, 1897 true); 1898 } 1899 1900 /* increase throttled vcp size */ 1901 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1902 pbn_per_slot = get_pbn_per_slot(stream); 1903 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1904 1905 if (link_hwss->ext.set_throttled_vcp_size) 1906 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1907 if (link_hwss->ext.set_hblank_min_symbol_width) 1908 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1909 &link->cur_link_settings, 1910 avg_time_slots_per_mtp); 1911 1912 return DC_OK; 1913 } 1914 1915 static void disable_link_dp(struct dc_link *link, 1916 const struct link_resource *link_res, 1917 enum signal_type signal) 1918 { 1919 struct dc_link_settings link_settings = link->cur_link_settings; 1920 1921 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1922 link->mst_stream_alloc_table.stream_count > 0) 1923 /* disable MST link only when last vc payload is deallocated */ 1924 return; 1925 1926 dp_disable_link_phy(link, link_res, signal); 1927 1928 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1929 if (!link->dc->config.edp_no_power_sequencing) 1930 link->dc->hwss.edp_power_control(link, false); 1931 } 1932 1933 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1934 /* set the sink to SST mode after disabling the link */ 1935 enable_mst_on_sink(link, false); 1936 1937 if (link_dp_get_encoding_format(&link_settings) == 1938 DP_8b_10b_ENCODING) { 1939 dp_set_fec_enable(link, false); 1940 dp_set_fec_ready(link, link_res, false); 1941 } 1942 } 1943 1944 static void disable_link(struct dc_link *link, 1945 const struct link_resource *link_res, 1946 enum signal_type signal) 1947 { 1948 if (dc_is_dp_signal(signal)) { 1949 disable_link_dp(link, link_res, signal); 1950 } else if (signal != SIGNAL_TYPE_VIRTUAL) { 1951 link->dc->hwss.disable_link_output(link, link_res, signal); 1952 } 1953 1954 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1955 /* MST disable link only when no stream use the link */ 1956 if (link->mst_stream_alloc_table.stream_count <= 0) 1957 link->link_status.link_active = false; 1958 } else { 1959 link->link_status.link_active = false; 1960 } 1961 } 1962 1963 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1964 { 1965 struct dc_stream_state *stream = pipe_ctx->stream; 1966 struct dc_link *link = stream->link; 1967 enum dc_color_depth display_color_depth; 1968 enum engine_id eng_id; 1969 struct ext_hdmi_settings settings = {0}; 1970 bool is_over_340mhz = false; 1971 bool is_vga_mode = (stream->timing.h_addressable == 640) 1972 && (stream->timing.v_addressable == 480); 1973 struct dc *dc = pipe_ctx->stream->ctx->dc; 1974 1975 if (stream->phy_pix_clk == 0) 1976 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1977 if (stream->phy_pix_clk > 340000) 1978 is_over_340mhz = true; 1979 1980 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1981 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1982 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1983 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1984 /* DP159, Retimer settings */ 1985 eng_id = pipe_ctx->stream_res.stream_enc->id; 1986 1987 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1988 write_i2c_retimer_setting(pipe_ctx, 1989 is_vga_mode, is_over_340mhz, &settings); 1990 } else { 1991 write_i2c_default_retimer_setting(pipe_ctx, 1992 is_vga_mode, is_over_340mhz); 1993 } 1994 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1995 /* PI3EQX1204, Redriver settings */ 1996 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1997 } 1998 } 1999 2000 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2001 write_scdc_data( 2002 stream->link->ddc, 2003 stream->phy_pix_clk, 2004 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2005 2006 memset(&stream->link->cur_link_settings, 0, 2007 sizeof(struct dc_link_settings)); 2008 2009 display_color_depth = stream->timing.display_color_depth; 2010 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2011 display_color_depth = COLOR_DEPTH_888; 2012 2013 dc->hwss.enable_tmds_link_output( 2014 link, 2015 &pipe_ctx->link_res, 2016 pipe_ctx->stream->signal, 2017 pipe_ctx->clock_source->id, 2018 display_color_depth, 2019 stream->phy_pix_clk); 2020 2021 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2022 read_scdc_data(link->ddc); 2023 } 2024 2025 static enum dc_status enable_link_dp(struct dc_state *state, 2026 struct pipe_ctx *pipe_ctx) 2027 { 2028 struct dc_stream_state *stream = pipe_ctx->stream; 2029 enum dc_status status; 2030 bool skip_video_pattern; 2031 struct dc_link *link = stream->link; 2032 const struct dc_link_settings *link_settings = 2033 &pipe_ctx->link_config.dp_link_settings; 2034 bool fec_enable; 2035 int i; 2036 bool apply_seamless_boot_optimization = false; 2037 uint32_t bl_oled_enable_delay = 50; // in ms 2038 uint32_t post_oui_delay = 30; // 30ms 2039 /* Reduce link bandwidth between failed link training attempts. */ 2040 bool do_fallback = false; 2041 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2042 2043 // Increase retry count if attempting DP1.x on FIXED_VS link 2044 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2045 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2046 lt_attempts = 10; 2047 2048 // check for seamless boot 2049 for (i = 0; i < state->stream_count; i++) { 2050 if (state->streams[i]->apply_seamless_boot_optimization) { 2051 apply_seamless_boot_optimization = true; 2052 break; 2053 } 2054 } 2055 2056 /* 2057 * If the link is DP-over-USB4 do the following: 2058 * - Train with fallback when enabling DPIA link. Conventional links are 2059 * trained with fallback during sink detection. 2060 * - Allocate only what the stream needs for bw in Gbps. Inform the CM 2061 * in case stream needs more or less bw from what has been allocated 2062 * earlier at plug time. 2063 */ 2064 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2065 do_fallback = true; 2066 } 2067 2068 /* 2069 * Temporary w/a to get DP2.0 link rates to work with SST. 2070 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2071 */ 2072 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2073 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2074 link->dc->debug.set_mst_en_for_sst) { 2075 enable_mst_on_sink(link, true); 2076 } 2077 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2078 /*in case it is not on*/ 2079 if (!link->dc->config.edp_no_power_sequencing) 2080 link->dc->hwss.edp_power_control(link, true); 2081 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2082 } 2083 2084 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2085 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2086 } else { 2087 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2088 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2089 if (state->clk_mgr && !apply_seamless_boot_optimization) 2090 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2091 state, false); 2092 } 2093 2094 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2095 dpcd_set_source_specific_data(link); 2096 if (link->dpcd_sink_ext_caps.raw != 0) { 2097 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2098 msleep(post_oui_delay); 2099 } 2100 2101 // similarly, mode switch can cause loss of cable ID 2102 dpcd_write_cable_id_to_dprx(link); 2103 2104 skip_video_pattern = true; 2105 2106 if (link_settings->link_rate == LINK_RATE_LOW) 2107 skip_video_pattern = false; 2108 2109 if (perform_link_training_with_retries(link_settings, 2110 skip_video_pattern, 2111 lt_attempts, 2112 pipe_ctx, 2113 pipe_ctx->stream->signal, 2114 do_fallback)) { 2115 status = DC_OK; 2116 } else { 2117 status = DC_FAIL_DP_LINK_TRAINING; 2118 } 2119 2120 if (link->preferred_training_settings.fec_enable) 2121 fec_enable = *link->preferred_training_settings.fec_enable; 2122 else 2123 fec_enable = true; 2124 2125 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2126 dp_set_fec_enable(link, fec_enable); 2127 2128 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2129 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2130 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2131 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2132 set_default_brightness_aux(link); // TODO: use cached if known 2133 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2134 msleep(bl_oled_enable_delay); 2135 edp_backlight_enable_aux(link, true); 2136 } 2137 2138 return status; 2139 } 2140 2141 static enum dc_status enable_link_edp( 2142 struct dc_state *state, 2143 struct pipe_ctx *pipe_ctx) 2144 { 2145 return enable_link_dp(state, pipe_ctx); 2146 } 2147 2148 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2149 { 2150 struct dc_stream_state *stream = pipe_ctx->stream; 2151 struct dc_link *link = stream->link; 2152 struct dc *dc = stream->ctx->dc; 2153 2154 if (stream->phy_pix_clk == 0) 2155 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2156 2157 memset(&stream->link->cur_link_settings, 0, 2158 sizeof(struct dc_link_settings)); 2159 dc->hwss.enable_lvds_link_output( 2160 link, 2161 &pipe_ctx->link_res, 2162 pipe_ctx->clock_source->id, 2163 stream->phy_pix_clk); 2164 2165 } 2166 2167 static enum dc_status enable_link_dp_mst( 2168 struct dc_state *state, 2169 struct pipe_ctx *pipe_ctx) 2170 { 2171 struct dc_link *link = pipe_ctx->stream->link; 2172 unsigned char mstm_cntl; 2173 2174 /* sink signal type after MST branch is MST. Multiple MST sinks 2175 * share one link. Link DP PHY is enable or training only once. 2176 */ 2177 if (link->link_status.link_active) 2178 return DC_OK; 2179 2180 /* clear payload table */ 2181 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2182 if (mstm_cntl & DP_MST_EN) 2183 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2184 2185 /* to make sure the pending down rep can be processed 2186 * before enabling the link 2187 */ 2188 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2189 2190 /* set the sink to MST mode before enabling the link */ 2191 enable_mst_on_sink(link, true); 2192 2193 return enable_link_dp(state, pipe_ctx); 2194 } 2195 2196 static enum dc_status enable_link( 2197 struct dc_state *state, 2198 struct pipe_ctx *pipe_ctx) 2199 { 2200 enum dc_status status = DC_ERROR_UNEXPECTED; 2201 struct dc_stream_state *stream = pipe_ctx->stream; 2202 struct dc_link *link = stream->link; 2203 2204 /* There's some scenarios where driver is unloaded with display 2205 * still enabled. When driver is reloaded, it may cause a display 2206 * to not light up if there is a mismatch between old and new 2207 * link settings. Need to call disable first before enabling at 2208 * new link settings. 2209 */ 2210 if (link->link_status.link_active && !stream->skip_edp_power_down) 2211 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2212 2213 switch (pipe_ctx->stream->signal) { 2214 case SIGNAL_TYPE_DISPLAY_PORT: 2215 status = enable_link_dp(state, pipe_ctx); 2216 break; 2217 case SIGNAL_TYPE_EDP: 2218 status = enable_link_edp(state, pipe_ctx); 2219 break; 2220 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2221 status = enable_link_dp_mst(state, pipe_ctx); 2222 msleep(200); 2223 break; 2224 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2225 case SIGNAL_TYPE_DVI_DUAL_LINK: 2226 case SIGNAL_TYPE_HDMI_TYPE_A: 2227 enable_link_hdmi(pipe_ctx); 2228 status = DC_OK; 2229 break; 2230 case SIGNAL_TYPE_LVDS: 2231 enable_link_lvds(pipe_ctx); 2232 status = DC_OK; 2233 break; 2234 case SIGNAL_TYPE_VIRTUAL: 2235 status = DC_OK; 2236 break; 2237 default: 2238 break; 2239 } 2240 2241 if (status == DC_OK) { 2242 pipe_ctx->stream->link->link_status.link_active = true; 2243 } 2244 2245 return status; 2246 } 2247 2248 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2249 { 2250 struct dc *dc = pipe_ctx->stream->ctx->dc; 2251 struct dc_stream_state *stream = pipe_ctx->stream; 2252 struct dc_link *link = stream->sink->link; 2253 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2254 2255 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2256 2257 if (dp_is_128b_132b_signal(pipe_ctx)) 2258 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2259 2260 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2261 2262 if (pipe_ctx->stream->sink) { 2263 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2264 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2265 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2266 pipe_ctx->stream->sink->edid_caps.display_name, 2267 pipe_ctx->stream->signal); 2268 } 2269 } 2270 2271 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2272 return; 2273 2274 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2275 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2276 set_avmute(pipe_ctx, true); 2277 } 2278 2279 dc->hwss.disable_audio_stream(pipe_ctx); 2280 2281 update_psp_stream_config(pipe_ctx, true); 2282 dc->hwss.blank_stream(pipe_ctx); 2283 2284 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2285 deallocate_mst_payload(pipe_ctx); 2286 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2287 dp_is_128b_132b_signal(pipe_ctx)) 2288 update_sst_payload(pipe_ctx, false); 2289 2290 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2291 struct ext_hdmi_settings settings = {0}; 2292 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2293 2294 unsigned short masked_chip_caps = link->chip_caps & 2295 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2296 //Need to inform that sink is going to use legacy HDMI mode. 2297 write_scdc_data( 2298 link->ddc, 2299 165000,//vbios only handles 165Mhz. 2300 false); 2301 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2302 /* DP159, Retimer settings */ 2303 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2304 write_i2c_retimer_setting(pipe_ctx, 2305 false, false, &settings); 2306 else 2307 write_i2c_default_retimer_setting(pipe_ctx, 2308 false, false); 2309 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2310 /* PI3EQX1204, Redriver settings */ 2311 write_i2c_redriver_setting(pipe_ctx, false); 2312 } 2313 } 2314 2315 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2316 !dp_is_128b_132b_signal(pipe_ctx)) { 2317 2318 /* In DP1.x SST mode, our encoder will go to TPS1 2319 * when link is on but stream is off. 2320 * Disabling link before stream will avoid exposing TPS1 pattern 2321 * during the disable sequence as it will confuse some receivers 2322 * state machine. 2323 * In DP2 or MST mode, our encoder will stay video active 2324 */ 2325 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2326 dc->hwss.disable_stream(pipe_ctx); 2327 } else { 2328 dc->hwss.disable_stream(pipe_ctx); 2329 if (!pipe_ctx->stream->skip_edp_power_down) { 2330 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2331 } 2332 } 2333 2334 if (pipe_ctx->stream->timing.flags.DSC) { 2335 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2336 link_set_dsc_enable(pipe_ctx, false); 2337 } 2338 if (dp_is_128b_132b_signal(pipe_ctx)) { 2339 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2340 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2341 } 2342 2343 if (vpg && vpg->funcs->vpg_powerdown) 2344 vpg->funcs->vpg_powerdown(vpg); 2345 } 2346 2347 void link_set_dpms_on( 2348 struct dc_state *state, 2349 struct pipe_ctx *pipe_ctx) 2350 { 2351 struct dc *dc = pipe_ctx->stream->ctx->dc; 2352 struct dc_stream_state *stream = pipe_ctx->stream; 2353 struct dc_link *link = stream->sink->link; 2354 enum dc_status status; 2355 struct link_encoder *link_enc; 2356 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2357 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2358 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2359 bool apply_edp_fast_boot_optimization = 2360 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2361 2362 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2363 2364 if (dp_is_128b_132b_signal(pipe_ctx)) 2365 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2366 2367 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2368 2369 if (pipe_ctx->stream->sink) { 2370 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2371 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2372 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2373 pipe_ctx->stream->sink->edid_caps.display_name, 2374 pipe_ctx->stream->signal); 2375 } 2376 } 2377 2378 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2379 return; 2380 2381 link_enc = link_enc_cfg_get_link_enc(link); 2382 ASSERT(link_enc); 2383 2384 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2385 && !dp_is_128b_132b_signal(pipe_ctx)) { 2386 if (link_enc) 2387 link_enc->funcs->setup( 2388 link_enc, 2389 pipe_ctx->stream->signal); 2390 } 2391 2392 pipe_ctx->stream->link->link_state_valid = true; 2393 2394 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2395 if (dp_is_128b_132b_signal(pipe_ctx)) 2396 otg_out_dest = OUT_MUX_HPO_DP; 2397 else 2398 otg_out_dest = OUT_MUX_DIO; 2399 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2400 } 2401 2402 link_hwss->setup_stream_attribute(pipe_ctx); 2403 2404 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2405 2406 // Enable VPG before building infoframe 2407 if (vpg && vpg->funcs->vpg_poweron) 2408 vpg->funcs->vpg_poweron(vpg); 2409 2410 resource_build_info_frame(pipe_ctx); 2411 dc->hwss.update_info_frame(pipe_ctx); 2412 2413 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2414 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2415 2416 /* Do not touch link on seamless boot optimization. */ 2417 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2418 pipe_ctx->stream->dpms_off = false; 2419 2420 /* Still enable stream features & audio on seamless boot for DP external displays */ 2421 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2422 enable_stream_features(pipe_ctx); 2423 dc->hwss.enable_audio_stream(pipe_ctx); 2424 } 2425 2426 update_psp_stream_config(pipe_ctx, false); 2427 return; 2428 } 2429 2430 /* eDP lit up by bios already, no need to enable again. */ 2431 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2432 apply_edp_fast_boot_optimization && 2433 !pipe_ctx->stream->timing.flags.DSC && 2434 !pipe_ctx->next_odm_pipe) { 2435 pipe_ctx->stream->dpms_off = false; 2436 update_psp_stream_config(pipe_ctx, false); 2437 return; 2438 } 2439 2440 if (pipe_ctx->stream->dpms_off) 2441 return; 2442 2443 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2444 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2445 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2446 * will be automatically set at a later time when the video is enabled 2447 * (DP_VID_STREAM_EN = 1). 2448 */ 2449 if (pipe_ctx->stream->timing.flags.DSC) { 2450 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2451 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2452 link_set_dsc_enable(pipe_ctx, true); 2453 2454 } 2455 2456 status = enable_link(state, pipe_ctx); 2457 2458 if (status != DC_OK) { 2459 DC_LOG_WARNING("enabling link %u failed: %d\n", 2460 pipe_ctx->stream->link->link_index, 2461 status); 2462 2463 /* Abort stream enable *unless* the failure was due to 2464 * DP link training - some DP monitors will recover and 2465 * show the stream anyway. But MST displays can't proceed 2466 * without link training. 2467 */ 2468 if (status != DC_FAIL_DP_LINK_TRAINING || 2469 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2470 if (false == stream->link->link_status.link_active) 2471 disable_link(stream->link, &pipe_ctx->link_res, 2472 pipe_ctx->stream->signal); 2473 BREAK_TO_DEBUGGER(); 2474 return; 2475 } 2476 } 2477 2478 /* turn off otg test pattern if enable */ 2479 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2480 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2481 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2482 COLOR_DEPTH_UNDEFINED); 2483 2484 /* This second call is needed to reconfigure the DIG 2485 * as a workaround for the incorrect value being applied 2486 * from transmitter control. 2487 */ 2488 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2489 dp_is_128b_132b_signal(pipe_ctx))) { 2490 if (link_enc) 2491 link_enc->funcs->setup( 2492 link_enc, 2493 pipe_ctx->stream->signal); 2494 } 2495 2496 dc->hwss.enable_stream(pipe_ctx); 2497 2498 /* Set DPS PPS SDP (AKA "info frames") */ 2499 if (pipe_ctx->stream->timing.flags.DSC) { 2500 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2501 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2502 dp_set_dsc_on_rx(pipe_ctx, true); 2503 link_set_dsc_pps_packet(pipe_ctx, true, true); 2504 } 2505 } 2506 2507 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2508 allocate_mst_payload(pipe_ctx); 2509 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2510 dp_is_128b_132b_signal(pipe_ctx)) 2511 update_sst_payload(pipe_ctx, true); 2512 2513 dc->hwss.unblank_stream(pipe_ctx, 2514 &pipe_ctx->stream->link->cur_link_settings); 2515 2516 if (stream->sink_patches.delay_ignore_msa > 0) 2517 msleep(stream->sink_patches.delay_ignore_msa); 2518 2519 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2520 enable_stream_features(pipe_ctx); 2521 update_psp_stream_config(pipe_ctx, false); 2522 2523 dc->hwss.enable_audio_stream(pipe_ctx); 2524 2525 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2526 set_avmute(pipe_ctx, false); 2527 } 2528 } 2529