1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file manages link detection states and receiver states by using various 28 * link protocols. It also provides helper functions to interpret certain 29 * capabilities or status based on the states it manages or retrieve them 30 * directly from connected receivers. 31 */ 32 33 #include "link_dpms.h" 34 #include "link_detection.h" 35 #include "link_hwss.h" 36 #include "protocols/link_edp_panel_control.h" 37 #include "protocols/link_ddc.h" 38 #include "protocols/link_hpd.h" 39 #include "protocols/link_dpcd.h" 40 #include "protocols/link_dp_capability.h" 41 #include "protocols/link_dp_dpia.h" 42 #include "protocols/link_dp_phy.h" 43 #include "protocols/link_dp_training.h" 44 #include "accessories/link_dp_trace.h" 45 46 #include "link_enc_cfg.h" 47 #include "dm_helpers.h" 48 #include "clk_mgr.h" 49 50 #define DC_LOGGER_INIT(logger) 51 52 #define LINK_INFO(...) \ 53 DC_LOG_HW_HOTPLUG( \ 54 __VA_ARGS__) 55 /* 56 * Some receivers fail to train on first try and are good 57 * on subsequent tries. 2 retries should be plenty. If we 58 * don't have a successful training then we don't expect to 59 * ever get one. 60 */ 61 #define LINK_TRAINING_MAX_VERIFY_RETRY 2 62 63 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u"; 64 65 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR"; 66 67 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) 68 { 69 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 70 71 switch (sink_signal) { 72 case SIGNAL_TYPE_DVI_SINGLE_LINK: 73 case SIGNAL_TYPE_DVI_DUAL_LINK: 74 case SIGNAL_TYPE_HDMI_TYPE_A: 75 case SIGNAL_TYPE_LVDS: 76 case SIGNAL_TYPE_RGB: 77 transaction_type = DDC_TRANSACTION_TYPE_I2C; 78 break; 79 80 case SIGNAL_TYPE_DISPLAY_PORT: 81 case SIGNAL_TYPE_EDP: 82 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 83 break; 84 85 case SIGNAL_TYPE_DISPLAY_PORT_MST: 86 /* MST does not use I2COverAux, but there is the 87 * SPECIAL use case for "immediate dwnstrm device 88 * access" (EPR#370830). 89 */ 90 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 91 break; 92 93 default: 94 break; 95 } 96 97 return transaction_type; 98 } 99 100 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, 101 struct graphics_object_id downstream) 102 { 103 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 104 switch (downstream.id) { 105 case CONNECTOR_ID_SINGLE_LINK_DVII: 106 switch (encoder.id) { 107 case ENCODER_ID_INTERNAL_DAC1: 108 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 109 case ENCODER_ID_INTERNAL_DAC2: 110 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 111 return SIGNAL_TYPE_RGB; 112 default: 113 return SIGNAL_TYPE_DVI_SINGLE_LINK; 114 } 115 break; 116 case CONNECTOR_ID_DUAL_LINK_DVII: 117 { 118 switch (encoder.id) { 119 case ENCODER_ID_INTERNAL_DAC1: 120 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 121 case ENCODER_ID_INTERNAL_DAC2: 122 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 123 return SIGNAL_TYPE_RGB; 124 default: 125 return SIGNAL_TYPE_DVI_DUAL_LINK; 126 } 127 } 128 break; 129 case CONNECTOR_ID_SINGLE_LINK_DVID: 130 return SIGNAL_TYPE_DVI_SINGLE_LINK; 131 case CONNECTOR_ID_DUAL_LINK_DVID: 132 return SIGNAL_TYPE_DVI_DUAL_LINK; 133 case CONNECTOR_ID_VGA: 134 return SIGNAL_TYPE_RGB; 135 case CONNECTOR_ID_HDMI_TYPE_A: 136 return SIGNAL_TYPE_HDMI_TYPE_A; 137 case CONNECTOR_ID_LVDS: 138 return SIGNAL_TYPE_LVDS; 139 case CONNECTOR_ID_DISPLAY_PORT: 140 case CONNECTOR_ID_USBC: 141 return SIGNAL_TYPE_DISPLAY_PORT; 142 case CONNECTOR_ID_EDP: 143 return SIGNAL_TYPE_EDP; 144 default: 145 return SIGNAL_TYPE_NONE; 146 } 147 } else if (downstream.type == OBJECT_TYPE_ENCODER) { 148 switch (downstream.id) { 149 case ENCODER_ID_EXTERNAL_NUTMEG: 150 case ENCODER_ID_EXTERNAL_TRAVIS: 151 return SIGNAL_TYPE_DISPLAY_PORT; 152 default: 153 return SIGNAL_TYPE_NONE; 154 } 155 } 156 157 return SIGNAL_TYPE_NONE; 158 } 159 160 /* 161 * @brief 162 * Detect output sink type 163 */ 164 static enum signal_type link_detect_sink_signal_type(struct dc_link *link, 165 enum dc_detect_reason reason) 166 { 167 enum signal_type result; 168 struct graphics_object_id enc_id; 169 170 if (link->is_dig_mapping_flexible) 171 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; 172 else 173 enc_id = link->link_enc->id; 174 result = get_basic_signal_type(enc_id, link->link_id); 175 176 /* Use basic signal type for link without physical connector. */ 177 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 178 return result; 179 180 /* Internal digital encoder will detect only dongles 181 * that require digital signal 182 */ 183 184 /* Detection mechanism is different 185 * for different native connectors. 186 * LVDS connector supports only LVDS signal; 187 * PCIE is a bus slot, the actual connector needs to be detected first; 188 * eDP connector supports only eDP signal; 189 * HDMI should check straps for audio 190 */ 191 192 /* PCIE detects the actual connector on add-on board */ 193 if (link->link_id.id == CONNECTOR_ID_PCIE) { 194 /* ZAZTODO implement PCIE add-on card detection */ 195 } 196 197 switch (link->link_id.id) { 198 case CONNECTOR_ID_HDMI_TYPE_A: { 199 /* check audio support: 200 * if native HDMI is not supported, switch to DVI 201 */ 202 struct audio_support *aud_support = 203 &link->dc->res_pool->audio_support; 204 205 if (!aud_support->hdmi_audio_native) 206 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) 207 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 208 } 209 break; 210 case CONNECTOR_ID_DISPLAY_PORT: 211 case CONNECTOR_ID_USBC: { 212 /* DP HPD short pulse. Passive DP dongle will not 213 * have short pulse 214 */ 215 if (reason != DETECT_REASON_HPDRX) { 216 /* Check whether DP signal detected: if not - 217 * we assume signal is DVI; it could be corrected 218 * to HDMI after dongle detection 219 */ 220 if (!dm_helpers_is_dp_sink_present(link)) 221 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 222 } 223 } 224 break; 225 default: 226 break; 227 } 228 229 return result; 230 } 231 232 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type, 233 struct audio_support *audio_support) 234 { 235 enum signal_type signal = SIGNAL_TYPE_NONE; 236 237 switch (dongle_type) { 238 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 239 if (audio_support->hdmi_audio_on_dongle) 240 signal = SIGNAL_TYPE_HDMI_TYPE_A; 241 else 242 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 243 break; 244 case DISPLAY_DONGLE_DP_DVI_DONGLE: 245 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 246 break; 247 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 248 if (audio_support->hdmi_audio_native) 249 signal = SIGNAL_TYPE_HDMI_TYPE_A; 250 else 251 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 252 break; 253 default: 254 signal = SIGNAL_TYPE_NONE; 255 break; 256 } 257 258 return signal; 259 } 260 261 static void read_scdc_caps(struct ddc_service *ddc_service, 262 struct dc_sink *sink) 263 { 264 uint8_t slave_address = HDMI_SCDC_ADDRESS; 265 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; 266 267 link_query_ddc_data(ddc_service, slave_address, &offset, 268 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, 269 sizeof(sink->scdc_caps.manufacturer_OUI.byte)); 270 271 offset = HDMI_SCDC_DEVICE_ID; 272 273 link_query_ddc_data(ddc_service, slave_address, &offset, 274 sizeof(offset), &(sink->scdc_caps.device_id.byte), 275 sizeof(sink->scdc_caps.device_id.byte)); 276 } 277 278 static bool i2c_read( 279 struct ddc_service *ddc, 280 uint32_t address, 281 uint8_t *buffer, 282 uint32_t len) 283 { 284 uint8_t offs_data = 0; 285 struct i2c_payload payloads[2] = { 286 { 287 .write = true, 288 .address = address, 289 .length = 1, 290 .data = &offs_data }, 291 { 292 .write = false, 293 .address = address, 294 .length = len, 295 .data = buffer } }; 296 297 struct i2c_command command = { 298 .payloads = payloads, 299 .number_of_payloads = 2, 300 .engine = DDC_I2C_COMMAND_ENGINE, 301 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 302 303 return dm_helpers_submit_i2c( 304 ddc->ctx, 305 ddc->link, 306 &command); 307 } 308 309 enum { 310 DP_SINK_CAP_SIZE = 311 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 312 }; 313 314 static void query_dp_dual_mode_adaptor( 315 struct ddc_service *ddc, 316 struct display_sink_capability *sink_cap) 317 { 318 uint8_t i; 319 bool is_valid_hdmi_signature; 320 enum display_dongle_type *dongle = &sink_cap->dongle_type; 321 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 322 bool is_type2_dongle = false; 323 int retry_count = 2; 324 struct dp_hdmi_dongle_signature_data *dongle_signature; 325 326 /* Assume we have no valid DP passive dongle connected */ 327 *dongle = DISPLAY_DONGLE_NONE; 328 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 329 330 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 331 if (!i2c_read( 332 ddc, 333 DP_HDMI_DONGLE_ADDRESS, 334 type2_dongle_buf, 335 sizeof(type2_dongle_buf))) { 336 /* Passive HDMI dongles can sometimes fail here without retrying*/ 337 while (retry_count > 0) { 338 if (i2c_read(ddc, 339 DP_HDMI_DONGLE_ADDRESS, 340 type2_dongle_buf, 341 sizeof(type2_dongle_buf))) 342 break; 343 retry_count--; 344 } 345 if (retry_count == 0) { 346 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 347 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 348 349 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), 350 "DP-DVI passive dongle %dMhz: ", 351 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 352 return; 353 } 354 } 355 356 /* Check if Type 2 dongle.*/ 357 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 358 is_type2_dongle = true; 359 360 dongle_signature = 361 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 362 363 is_valid_hdmi_signature = true; 364 365 /* Check EOT */ 366 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 367 is_valid_hdmi_signature = false; 368 } 369 370 /* Check signature */ 371 for (i = 0; i < sizeof(dongle_signature->id); ++i) { 372 /* If its not the right signature, 373 * skip mismatch in subversion byte.*/ 374 if (dongle_signature->id[i] != 375 dp_hdmi_dongle_signature_str[i] && i != 3) { 376 377 if (is_type2_dongle) { 378 is_valid_hdmi_signature = false; 379 break; 380 } 381 382 } 383 } 384 385 if (is_type2_dongle) { 386 uint32_t max_tmds_clk = 387 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 388 389 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 390 391 if (0 == max_tmds_clk || 392 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 393 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 394 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 395 396 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 397 sizeof(type2_dongle_buf), 398 "DP-DVI passive dongle %dMhz: ", 399 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 400 } else { 401 if (is_valid_hdmi_signature == true) { 402 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 403 404 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 405 sizeof(type2_dongle_buf), 406 "Type 2 DP-HDMI passive dongle %dMhz: ", 407 max_tmds_clk); 408 } else { 409 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 410 411 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 412 sizeof(type2_dongle_buf), 413 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 414 max_tmds_clk); 415 416 } 417 418 /* Multiply by 1000 to convert to kHz. */ 419 sink_cap->max_hdmi_pixel_clock = 420 max_tmds_clk * 1000; 421 } 422 sink_cap->is_dongle_type_one = false; 423 424 } else { 425 if (is_valid_hdmi_signature == true) { 426 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 427 428 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 429 sizeof(type2_dongle_buf), 430 "Type 1 DP-HDMI passive dongle %dMhz: ", 431 sink_cap->max_hdmi_pixel_clock / 1000); 432 } else { 433 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 434 435 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 436 sizeof(type2_dongle_buf), 437 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 438 sink_cap->max_hdmi_pixel_clock / 1000); 439 } 440 sink_cap->is_dongle_type_one = true; 441 } 442 443 return; 444 } 445 446 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 447 struct display_sink_capability *sink_cap, 448 struct audio_support *audio_support) 449 { 450 query_dp_dual_mode_adaptor(ddc, sink_cap); 451 452 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 453 audio_support); 454 } 455 456 static void link_disconnect_sink(struct dc_link *link) 457 { 458 if (link->local_sink) { 459 dc_sink_release(link->local_sink); 460 link->local_sink = NULL; 461 } 462 463 link->dpcd_sink_count = 0; 464 //link->dpcd_caps.dpcd_rev.raw = 0; 465 } 466 467 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 468 { 469 dc_sink_release(link->local_sink); 470 link->local_sink = prev_sink; 471 } 472 473 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) 474 { 475 struct hdcp_protection_message msg22; 476 struct hdcp_protection_message msg14; 477 478 memset(&msg22, 0, sizeof(struct hdcp_protection_message)); 479 memset(&msg14, 0, sizeof(struct hdcp_protection_message)); 480 memset(link->hdcp_caps.rx_caps.raw, 0, 481 sizeof(link->hdcp_caps.rx_caps.raw)); 482 483 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 484 link->ddc->transaction_type == 485 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) || 486 link->connector_signal == SIGNAL_TYPE_EDP) { 487 msg22.data = link->hdcp_caps.rx_caps.raw; 488 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw); 489 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS; 490 } else { 491 msg22.data = &link->hdcp_caps.rx_caps.fields.version; 492 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version); 493 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION; 494 } 495 msg22.version = HDCP_VERSION_22; 496 msg22.link = HDCP_LINK_PRIMARY; 497 msg22.max_retries = 5; 498 dc_process_hdcp_msg(signal, link, &msg22); 499 500 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 501 msg14.data = &link->hdcp_caps.bcaps.raw; 502 msg14.length = sizeof(link->hdcp_caps.bcaps.raw); 503 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; 504 msg14.version = HDCP_VERSION_14; 505 msg14.link = HDCP_LINK_PRIMARY; 506 msg14.max_retries = 5; 507 508 dc_process_hdcp_msg(signal, link, &msg14); 509 } 510 511 } 512 static void read_current_link_settings_on_detect(struct dc_link *link) 513 { 514 union lane_count_set lane_count_set = {0}; 515 uint8_t link_bw_set; 516 uint8_t link_rate_set; 517 uint32_t read_dpcd_retry_cnt = 10; 518 enum dc_status status = DC_ERROR_UNEXPECTED; 519 int i; 520 union max_down_spread max_down_spread = {0}; 521 522 // Read DPCD 00101h to find out the number of lanes currently set 523 for (i = 0; i < read_dpcd_retry_cnt; i++) { 524 status = core_link_read_dpcd(link, 525 DP_LANE_COUNT_SET, 526 &lane_count_set.raw, 527 sizeof(lane_count_set)); 528 /* First DPCD read after VDD ON can fail if the particular board 529 * does not have HPD pin wired correctly. So if DPCD read fails, 530 * which it should never happen, retry a few times. Target worst 531 * case scenario of 80 ms. 532 */ 533 if (status == DC_OK) { 534 link->cur_link_settings.lane_count = 535 lane_count_set.bits.LANE_COUNT_SET; 536 break; 537 } 538 539 msleep(8); 540 } 541 542 // Read DPCD 00100h to find if standard link rates are set 543 core_link_read_dpcd(link, DP_LINK_BW_SET, 544 &link_bw_set, sizeof(link_bw_set)); 545 546 if (link_bw_set == 0) { 547 if (link->connector_signal == SIGNAL_TYPE_EDP) { 548 /* If standard link rates are not being used, 549 * Read DPCD 00115h to find the edp link rate set used 550 */ 551 core_link_read_dpcd(link, DP_LINK_RATE_SET, 552 &link_rate_set, sizeof(link_rate_set)); 553 554 // edp_supported_link_rates_count = 0 for DP 555 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 556 link->cur_link_settings.link_rate = 557 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 558 link->cur_link_settings.link_rate_set = link_rate_set; 559 link->cur_link_settings.use_link_rate_set = true; 560 } 561 } else { 562 // Link Rate not found. Seamless boot may not work. 563 ASSERT(false); 564 } 565 } else { 566 link->cur_link_settings.link_rate = link_bw_set; 567 link->cur_link_settings.use_link_rate_set = false; 568 } 569 // Read DPCD 00003h to find the max down spread. 570 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 571 &max_down_spread.raw, sizeof(max_down_spread)); 572 link->cur_link_settings.link_spread = 573 max_down_spread.bits.MAX_DOWN_SPREAD ? 574 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 575 } 576 577 static bool detect_dp(struct dc_link *link, 578 struct display_sink_capability *sink_caps, 579 enum dc_detect_reason reason) 580 { 581 struct audio_support *audio_support = &link->dc->res_pool->audio_support; 582 583 sink_caps->signal = link_detect_sink_signal_type(link, reason); 584 sink_caps->transaction_type = 585 get_ddc_transaction_type(sink_caps->signal); 586 587 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 588 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 589 if (!detect_dp_sink_caps(link)) 590 return false; 591 592 if (is_dp_branch_device(link)) 593 /* DP SST branch */ 594 link->type = dc_connection_sst_branch; 595 } else { 596 /* DP passive dongles */ 597 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 598 sink_caps, 599 audio_support); 600 link->dpcd_caps.dongle_type = sink_caps->dongle_type; 601 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one; 602 link->dpcd_caps.dpcd_rev.raw = 0; 603 } 604 605 return true; 606 } 607 608 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 609 { 610 if (old_edid->length != new_edid->length) 611 return false; 612 613 if (new_edid->length == 0) 614 return false; 615 616 return (memcmp(old_edid->raw_edid, 617 new_edid->raw_edid, new_edid->length) == 0); 618 } 619 620 static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 621 { 622 623 /** 624 * something is terribly wrong if time out is > 200ms. (5Hz) 625 * 500 microseconds * 400 tries us 200 ms 626 **/ 627 unsigned int sleep_time_in_microseconds = 500; 628 unsigned int tries_allowed = 400; 629 bool is_in_alt_mode; 630 unsigned long long enter_timestamp; 631 unsigned long long finish_timestamp; 632 unsigned long long time_taken_in_ns; 633 int tries_taken; 634 635 DC_LOGGER_INIT(link->ctx->logger); 636 637 /** 638 * this function will only exist if we are on dcn21 (is_in_alt_mode is a 639 * function pointer, so checking to see if it is equal to 0 is the same 640 * as checking to see if it is null 641 **/ 642 if (!link->link_enc->funcs->is_in_alt_mode) 643 return true; 644 645 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 646 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode); 647 648 if (is_in_alt_mode) 649 return true; 650 651 enter_timestamp = dm_get_timestamp(link->ctx); 652 653 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 654 udelay(sleep_time_in_microseconds); 655 /* ask the link if alt mode is enabled, if so return ok */ 656 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 657 finish_timestamp = dm_get_timestamp(link->ctx); 658 time_taken_in_ns = 659 dm_get_elapse_time_in_ns(link->ctx, 660 finish_timestamp, 661 enter_timestamp); 662 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", 663 div_u64(time_taken_in_ns, 1000000)); 664 return true; 665 } 666 } 667 finish_timestamp = dm_get_timestamp(link->ctx); 668 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 669 enter_timestamp); 670 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", 671 div_u64(time_taken_in_ns, 1000000)); 672 return false; 673 } 674 675 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 676 { 677 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock 678 * reports DSC support. 679 */ 680 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 681 link->type == dc_connection_mst_branch && 682 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 683 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 && 684 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 685 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) 686 link->wa_flags.dpia_mst_dsc_always_on = true; 687 } 688 689 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) 690 { 691 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */ 692 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 693 link->wa_flags.dpia_mst_dsc_always_on = false; 694 } 695 696 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) 697 { 698 DC_LOGGER_INIT(link->ctx->logger); 699 700 LINK_INFO("link=%d, mst branch is now Connected\n", 701 link->link_index); 702 703 link->type = dc_connection_mst_branch; 704 apply_dpia_mst_dsc_always_on_wa(link); 705 706 dm_helpers_dp_update_branch_info(link->ctx, link); 707 if (dm_helpers_dp_mst_start_top_mgr(link->ctx, 708 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) { 709 link_disconnect_sink(link); 710 } else { 711 link->type = dc_connection_sst_branch; 712 } 713 714 return link->type == dc_connection_mst_branch; 715 } 716 717 bool link_reset_cur_dp_mst_topology(struct dc_link *link) 718 { 719 DC_LOGGER_INIT(link->ctx->logger); 720 721 LINK_INFO("link=%d, mst branch is now Disconnected\n", 722 link->link_index); 723 724 revert_dpia_mst_dsc_always_on_wa(link); 725 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 726 } 727 728 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, 729 enum dc_detect_reason reason) 730 { 731 int i; 732 bool can_apply_seamless_boot = false; 733 734 for (i = 0; i < dc->current_state->stream_count; i++) { 735 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { 736 can_apply_seamless_boot = true; 737 break; 738 } 739 } 740 741 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT; 742 } 743 744 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc) 745 { 746 dc_z10_restore(dc); 747 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 748 } 749 750 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) 751 { 752 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 753 } 754 755 static void verify_link_capability_destructive(struct dc_link *link, 756 struct dc_sink *sink, 757 enum dc_detect_reason reason) 758 { 759 bool should_prepare_phy_clocks = 760 should_prepare_phy_clocks_for_link_verification(link->dc, reason); 761 762 if (should_prepare_phy_clocks) 763 prepare_phy_clocks_for_destructive_link_verification(link->dc); 764 765 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 766 struct dc_link_settings known_limit_link_setting = 767 dp_get_max_link_cap(link); 768 link_set_all_streams_dpms_off_for_link(link); 769 dp_verify_link_cap_with_retries( 770 link, &known_limit_link_setting, 771 LINK_TRAINING_MAX_VERIFY_RETRY); 772 } else { 773 ASSERT(0); 774 } 775 776 if (should_prepare_phy_clocks) 777 restore_phy_clocks_for_destructive_link_verification(link->dc); 778 } 779 780 static void verify_link_capability_non_destructive(struct dc_link *link) 781 { 782 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 783 if (dc_is_embedded_signal(link->local_sink->sink_signal) || 784 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 785 /* TODO - should we check link encoder's max link caps here? 786 * How do we know which link encoder to check from? 787 */ 788 link->verified_link_cap = link->reported_link_cap; 789 else 790 link->verified_link_cap = dp_get_max_link_cap(link); 791 } 792 } 793 794 static bool should_verify_link_capability_destructively(struct dc_link *link, 795 enum dc_detect_reason reason) 796 { 797 bool destrictive = false; 798 struct dc_link_settings max_link_cap; 799 bool is_link_enc_unavailable = link->link_enc && 800 link->dc->res_pool->funcs->link_encs_assign && 801 !link_enc_cfg_is_link_enc_avail( 802 link->ctx->dc, 803 link->link_enc->preferred_engine, 804 link); 805 806 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 807 max_link_cap = dp_get_max_link_cap(link); 808 destrictive = true; 809 810 if (link->dc->debug.skip_detection_link_training || 811 dc_is_embedded_signal(link->local_sink->sink_signal) || 812 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 813 destrictive = false; 814 } else if (link_dp_get_encoding_format(&max_link_cap) == 815 DP_8b_10b_ENCODING) { 816 if (link->dpcd_caps.is_mst_capable || 817 is_link_enc_unavailable) { 818 destrictive = false; 819 } 820 } 821 } 822 823 return destrictive; 824 } 825 826 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, 827 enum dc_detect_reason reason) 828 { 829 if (should_verify_link_capability_destructively(link, reason)) 830 verify_link_capability_destructive(link, sink, reason); 831 else 832 verify_link_capability_non_destructive(link); 833 } 834 835 /* 836 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 837 * 838 * link->local_sink is created or destroyed as needed. 839 * 840 * This does not create remote sinks. 841 */ 842 static bool detect_link_and_local_sink(struct dc_link *link, 843 enum dc_detect_reason reason) 844 { 845 struct dc_sink_init_data sink_init_data = { 0 }; 846 struct display_sink_capability sink_caps = { 0 }; 847 uint32_t i; 848 bool converter_disable_audio = false; 849 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 850 bool same_edid = false; 851 enum dc_edid_status edid_status; 852 struct dc_context *dc_ctx = link->ctx; 853 struct dc *dc = dc_ctx->dc; 854 struct dc_sink *sink = NULL; 855 struct dc_sink *prev_sink = NULL; 856 struct dpcd_caps prev_dpcd_caps; 857 enum dc_connection_type new_connection_type = dc_connection_none; 858 enum dc_connection_type pre_connection_type = link->type; 859 const uint32_t post_oui_delay = 30; // 30ms 860 861 DC_LOGGER_INIT(link->ctx->logger); 862 863 if (dc_is_virtual_signal(link->connector_signal)) 864 return false; 865 866 if (((link->connector_signal == SIGNAL_TYPE_LVDS || 867 link->connector_signal == SIGNAL_TYPE_EDP) && 868 (!link->dc->config.allow_edp_hotplug_detection)) && 869 link->local_sink) { 870 // need to re-write OUI and brightness in resume case 871 if (link->connector_signal == SIGNAL_TYPE_EDP && 872 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 873 dpcd_set_source_specific_data(link); 874 msleep(post_oui_delay); 875 set_default_brightness_aux(link); 876 //TODO: use cached 877 } 878 879 return true; 880 } 881 882 if (!link_detect_connection_type(link, &new_connection_type)) { 883 BREAK_TO_DEBUGGER(); 884 return false; 885 } 886 887 prev_sink = link->local_sink; 888 if (prev_sink) { 889 dc_sink_retain(prev_sink); 890 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 891 } 892 893 link_disconnect_sink(link); 894 if (new_connection_type != dc_connection_none) { 895 link->type = new_connection_type; 896 link->link_state_valid = false; 897 898 /* From Disconnected-to-Connected. */ 899 switch (link->connector_signal) { 900 case SIGNAL_TYPE_HDMI_TYPE_A: { 901 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 902 if (aud_support->hdmi_audio_native) 903 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 904 else 905 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 906 break; 907 } 908 909 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 910 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 911 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 912 break; 913 } 914 915 case SIGNAL_TYPE_DVI_DUAL_LINK: { 916 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 917 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 918 break; 919 } 920 921 case SIGNAL_TYPE_LVDS: { 922 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 923 sink_caps.signal = SIGNAL_TYPE_LVDS; 924 break; 925 } 926 927 case SIGNAL_TYPE_EDP: { 928 detect_edp_sink_caps(link); 929 read_current_link_settings_on_detect(link); 930 931 /* Disable power sequence on MIPI panel + converter 932 */ 933 if (dc->config.enable_mipi_converter_optimization && 934 dc_ctx->dce_version == DCN_VERSION_3_01 && 935 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && 936 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, 937 sizeof(link->dpcd_caps.branch_dev_name)) == 0) { 938 dc->config.edp_no_power_sequencing = true; 939 940 if (!link->dpcd_caps.set_power_state_capable_edp) 941 link->wa_flags.dp_keep_receiver_powered = true; 942 } 943 944 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 945 sink_caps.signal = SIGNAL_TYPE_EDP; 946 break; 947 } 948 949 case SIGNAL_TYPE_DISPLAY_PORT: { 950 951 /* wa HPD high coming too early*/ 952 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 953 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 954 955 /* if alt mode times out, return false */ 956 if (!wait_for_entering_dp_alt_mode(link)) 957 return false; 958 } 959 960 if (!detect_dp(link, &sink_caps, reason)) { 961 link->type = pre_connection_type; 962 963 if (prev_sink) 964 dc_sink_release(prev_sink); 965 return false; 966 } 967 968 /* Active SST downstream branch device unplug*/ 969 if (link->type == dc_connection_sst_branch && 970 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 971 if (prev_sink) 972 /* Downstream unplug */ 973 dc_sink_release(prev_sink); 974 return true; 975 } 976 977 /* disable audio for non DP to HDMI active sst converter */ 978 if (link->type == dc_connection_sst_branch && 979 is_dp_active_dongle(link) && 980 (link->dpcd_caps.dongle_type != 981 DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 982 converter_disable_audio = true; 983 984 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */ 985 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 986 link->reported_link_cap.link_rate > LINK_RATE_HIGH3) 987 link->reported_link_cap.link_rate = LINK_RATE_HIGH3; 988 break; 989 } 990 991 default: 992 DC_ERROR("Invalid connector type! signal:%d\n", 993 link->connector_signal); 994 if (prev_sink) 995 dc_sink_release(prev_sink); 996 return false; 997 } /* switch() */ 998 999 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 1000 link->dpcd_sink_count = 1001 link->dpcd_caps.sink_count.bits.SINK_COUNT; 1002 else 1003 link->dpcd_sink_count = 1; 1004 1005 set_ddc_transaction_type(link->ddc, 1006 sink_caps.transaction_type); 1007 1008 link->aux_mode = 1009 link_is_in_aux_transaction_mode(link->ddc); 1010 1011 sink_init_data.link = link; 1012 sink_init_data.sink_signal = sink_caps.signal; 1013 1014 sink = dc_sink_create(&sink_init_data); 1015 if (!sink) { 1016 DC_ERROR("Failed to create sink!\n"); 1017 if (prev_sink) 1018 dc_sink_release(prev_sink); 1019 return false; 1020 } 1021 1022 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 1023 sink->converter_disable_audio = converter_disable_audio; 1024 1025 /* dc_sink_create returns a new reference */ 1026 link->local_sink = sink; 1027 1028 edid_status = dm_helpers_read_local_edid(link->ctx, 1029 link, sink); 1030 1031 switch (edid_status) { 1032 case EDID_BAD_CHECKSUM: 1033 DC_LOG_ERROR("EDID checksum invalid.\n"); 1034 break; 1035 case EDID_PARTIAL_VALID: 1036 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1037 break; 1038 case EDID_NO_RESPONSE: 1039 DC_LOG_ERROR("No EDID read.\n"); 1040 /* 1041 * Abort detection for non-DP connectors if we have 1042 * no EDID 1043 * 1044 * DP needs to report as connected if HDP is high 1045 * even if we have no EDID in order to go to 1046 * fail-safe mode 1047 */ 1048 if (dc_is_hdmi_signal(link->connector_signal) || 1049 dc_is_dvi_signal(link->connector_signal)) { 1050 if (prev_sink) 1051 dc_sink_release(prev_sink); 1052 1053 return false; 1054 } 1055 1056 if (link->type == dc_connection_sst_branch && 1057 link->dpcd_caps.dongle_type == 1058 DISPLAY_DONGLE_DP_VGA_CONVERTER && 1059 reason == DETECT_REASON_HPDRX) { 1060 /* Abort detection for DP-VGA adapters when EDID 1061 * can't be read and detection reason is VGA-side 1062 * hotplug 1063 */ 1064 if (prev_sink) 1065 dc_sink_release(prev_sink); 1066 link_disconnect_sink(link); 1067 1068 return true; 1069 } 1070 1071 break; 1072 default: 1073 break; 1074 } 1075 1076 // Check if edid is the same 1077 if ((prev_sink) && 1078 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) 1079 same_edid = is_same_edid(&prev_sink->dc_edid, 1080 &sink->dc_edid); 1081 1082 if (sink->edid_caps.panel_patch.skip_scdc_overwrite) 1083 link->ctx->dc->debug.hdmi20_disable = true; 1084 1085 if (dc_is_hdmi_signal(link->connector_signal)) 1086 read_scdc_caps(link->ddc, link->local_sink); 1087 1088 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 1089 sink_caps.transaction_type == 1090 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 1091 /* 1092 * TODO debug why certain monitors don't like 1093 * two link trainings 1094 */ 1095 query_hdcp_capability(sink->sink_signal, link); 1096 } else { 1097 // If edid is the same, then discard new sink and revert back to original sink 1098 if (same_edid) { 1099 link_disconnect_remap(prev_sink, link); 1100 sink = prev_sink; 1101 prev_sink = NULL; 1102 } 1103 query_hdcp_capability(sink->sink_signal, link); 1104 } 1105 1106 /* HDMI-DVI Dongle */ 1107 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 1108 !sink->edid_caps.edid_hdmi) 1109 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1110 1111 if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) 1112 dp_trace_init(link); 1113 1114 /* Connectivity log: detection */ 1115 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 1116 CONN_DATA_DETECT(link, 1117 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1118 DC_EDID_BLOCK_SIZE, 1119 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1120 } 1121 1122 DC_LOG_DETECTION_EDID_PARSER("%s: " 1123 "manufacturer_id = %X, " 1124 "product_id = %X, " 1125 "serial_number = %X, " 1126 "manufacture_week = %d, " 1127 "manufacture_year = %d, " 1128 "display_name = %s, " 1129 "speaker_flag = %d, " 1130 "audio_mode_count = %d\n", 1131 __func__, 1132 sink->edid_caps.manufacturer_id, 1133 sink->edid_caps.product_id, 1134 sink->edid_caps.serial_number, 1135 sink->edid_caps.manufacture_week, 1136 sink->edid_caps.manufacture_year, 1137 sink->edid_caps.display_name, 1138 sink->edid_caps.speaker_flags, 1139 sink->edid_caps.audio_mode_count); 1140 1141 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1142 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1143 "format_code = %d, " 1144 "channel_count = %d, " 1145 "sample_rate = %d, " 1146 "sample_size = %d\n", 1147 __func__, 1148 i, 1149 sink->edid_caps.audio_modes[i].format_code, 1150 sink->edid_caps.audio_modes[i].channel_count, 1151 sink->edid_caps.audio_modes[i].sample_rate, 1152 sink->edid_caps.audio_modes[i].sample_size); 1153 } 1154 1155 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1156 // Init dc_panel_config by HW config 1157 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) 1158 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); 1159 // Pickup base DM settings 1160 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); 1161 // Override dc_panel_config if system has specific settings 1162 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); 1163 } 1164 1165 } else { 1166 /* From Connected-to-Disconnected. */ 1167 link->type = dc_connection_none; 1168 sink_caps.signal = SIGNAL_TYPE_NONE; 1169 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps)); 1170 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1171 * is not cleared. If we emulate a DP signal on this connection, it thinks 1172 * the dongle is still there and limits the number of modes we can emulate. 1173 * Clear dongle_max_pix_clk on disconnect to fix this 1174 */ 1175 link->dongle_max_pix_clk = 0; 1176 1177 dc_link_clear_dprx_states(link); 1178 dp_trace_reset(link); 1179 } 1180 1181 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", 1182 link->link_index, sink, 1183 (sink_caps.signal == 1184 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), 1185 prev_sink, same_edid); 1186 1187 if (prev_sink) 1188 dc_sink_release(prev_sink); 1189 1190 return true; 1191 } 1192 1193 /* 1194 * link_detect_connection_type() - Determine if there is a sink connected 1195 * 1196 * @type: Returned connection type 1197 * Does not detect downstream devices, such as MST sinks 1198 * or display connected through active dongles 1199 */ 1200 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) 1201 { 1202 uint32_t is_hpd_high = 0; 1203 1204 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 1205 *type = dc_connection_single; 1206 return true; 1207 } 1208 1209 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1210 /*in case it is not on*/ 1211 if (!link->dc->config.edp_no_power_sequencing) 1212 link->dc->hwss.edp_power_control(link, true); 1213 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1214 } 1215 1216 /* Link may not have physical HPD pin. */ 1217 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 1218 if (link->is_hpd_pending || !dpia_query_hpd_status(link)) 1219 *type = dc_connection_none; 1220 else 1221 *type = dc_connection_single; 1222 1223 return true; 1224 } 1225 1226 1227 if (!query_hpd_status(link, &is_hpd_high)) 1228 goto hpd_gpio_failure; 1229 1230 if (is_hpd_high) { 1231 *type = dc_connection_single; 1232 /* TODO: need to do the actual detection */ 1233 } else { 1234 *type = dc_connection_none; 1235 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1236 /* eDP is not connected, power down it */ 1237 if (!link->dc->config.edp_no_power_sequencing) 1238 link->dc->hwss.edp_power_control(link, false); 1239 } 1240 } 1241 1242 return true; 1243 1244 hpd_gpio_failure: 1245 return false; 1246 } 1247 1248 bool link_detect(struct dc_link *link, enum dc_detect_reason reason) 1249 { 1250 bool is_local_sink_detect_success; 1251 bool is_delegated_to_mst_top_mgr = false; 1252 enum dc_connection_type pre_link_type = link->type; 1253 1254 DC_LOGGER_INIT(link->ctx->logger); 1255 1256 is_local_sink_detect_success = detect_link_and_local_sink(link, reason); 1257 1258 if (is_local_sink_detect_success && link->local_sink) 1259 verify_link_capability(link, link->local_sink, reason); 1260 1261 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, 1262 link->link_index, is_local_sink_detect_success, pre_link_type, link->type); 1263 1264 if (is_local_sink_detect_success && link->local_sink && 1265 dc_is_dp_signal(link->local_sink->sink_signal) && 1266 link->dpcd_caps.is_mst_capable) 1267 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason); 1268 1269 if (is_local_sink_detect_success && 1270 pre_link_type == dc_connection_mst_branch && 1271 link->type != dc_connection_mst_branch) 1272 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link); 1273 1274 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr; 1275 } 1276 1277 void link_clear_dprx_states(struct dc_link *link) 1278 { 1279 memset(&link->dprx_states, 0, sizeof(link->dprx_states)); 1280 } 1281 1282 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) 1283 { 1284 bool ret = false; 1285 1286 switch (signal) { 1287 case SIGNAL_TYPE_DISPLAY_PORT: 1288 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1289 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; 1290 break; 1291 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1292 case SIGNAL_TYPE_DVI_DUAL_LINK: 1293 case SIGNAL_TYPE_HDMI_TYPE_A: 1294 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, 1295 * we can poll for bksv but some displays have an issue with this. Since its so rare 1296 * for a display to not be 1.4 capable, this assumtion is ok 1297 */ 1298 ret = true; 1299 break; 1300 default: 1301 break; 1302 } 1303 return ret; 1304 } 1305 1306 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) 1307 { 1308 bool ret = false; 1309 1310 switch (signal) { 1311 case SIGNAL_TYPE_DISPLAY_PORT: 1312 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1313 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && 1314 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable && 1315 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0; 1316 break; 1317 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1318 case SIGNAL_TYPE_DVI_DUAL_LINK: 1319 case SIGNAL_TYPE_HDMI_TYPE_A: 1320 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; 1321 break; 1322 default: 1323 break; 1324 } 1325 1326 return ret; 1327 } 1328 1329 const struct dc_link_status *link_get_status(const struct dc_link *link) 1330 { 1331 return &link->link_status; 1332 } 1333 1334 1335 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) 1336 { 1337 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { 1338 BREAK_TO_DEBUGGER(); 1339 return false; 1340 } 1341 1342 dc_sink_retain(sink); 1343 1344 dc_link->remote_sinks[dc_link->sink_count] = sink; 1345 dc_link->sink_count++; 1346 1347 return true; 1348 } 1349 1350 struct dc_sink *link_add_remote_sink( 1351 struct dc_link *link, 1352 const uint8_t *edid, 1353 int len, 1354 struct dc_sink_init_data *init_data) 1355 { 1356 struct dc_sink *dc_sink; 1357 enum dc_edid_status edid_status; 1358 1359 if (len > DC_MAX_EDID_BUFFER_SIZE) { 1360 dm_error("Max EDID buffer size breached!\n"); 1361 return NULL; 1362 } 1363 1364 if (!init_data) { 1365 BREAK_TO_DEBUGGER(); 1366 return NULL; 1367 } 1368 1369 if (!init_data->link) { 1370 BREAK_TO_DEBUGGER(); 1371 return NULL; 1372 } 1373 1374 dc_sink = dc_sink_create(init_data); 1375 1376 if (!dc_sink) 1377 return NULL; 1378 1379 memmove(dc_sink->dc_edid.raw_edid, edid, len); 1380 dc_sink->dc_edid.length = len; 1381 1382 if (!link_add_remote_sink_helper( 1383 link, 1384 dc_sink)) 1385 goto fail_add_sink; 1386 1387 edid_status = dm_helpers_parse_edid_caps( 1388 link, 1389 &dc_sink->dc_edid, 1390 &dc_sink->edid_caps); 1391 1392 /* 1393 * Treat device as no EDID device if EDID 1394 * parsing fails 1395 */ 1396 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { 1397 dc_sink->dc_edid.length = 0; 1398 dm_error("Bad EDID, status%d!\n", edid_status); 1399 } 1400 1401 return dc_sink; 1402 1403 fail_add_sink: 1404 dc_sink_release(dc_sink); 1405 return NULL; 1406 } 1407 1408 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) 1409 { 1410 int i; 1411 1412 if (!link->sink_count) { 1413 BREAK_TO_DEBUGGER(); 1414 return; 1415 } 1416 1417 for (i = 0; i < link->sink_count; i++) { 1418 if (link->remote_sinks[i] == sink) { 1419 dc_sink_release(sink); 1420 link->remote_sinks[i] = NULL; 1421 1422 /* shrink array to remove empty place */ 1423 while (i < link->sink_count - 1) { 1424 link->remote_sinks[i] = link->remote_sinks[i+1]; 1425 i++; 1426 } 1427 link->remote_sinks[i] = NULL; 1428 link->sink_count--; 1429 return; 1430 } 1431 } 1432 } 1433