1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "link_hwss_hpo_dp.h" 26 #include "dm_helpers.h" 27 #include "core_types.h" 28 #include "dccg.h" 29 #include "clk_mgr.h" 30 31 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 32 { 33 switch (link->link_enc->transmitter) { 34 case TRANSMITTER_UNIPHY_A: 35 return PHYD32CLKA; 36 case TRANSMITTER_UNIPHY_B: 37 return PHYD32CLKB; 38 case TRANSMITTER_UNIPHY_C: 39 return PHYD32CLKC; 40 case TRANSMITTER_UNIPHY_D: 41 return PHYD32CLKD; 42 case TRANSMITTER_UNIPHY_E: 43 return PHYD32CLKE; 44 default: 45 return PHYD32CLKA; 46 } 47 } 48 49 static void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, 50 struct fixed31_32 throttled_vcp_size) 51 { 52 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = 53 pipe_ctx->stream_res.hpo_dp_stream_enc; 54 struct hpo_dp_link_encoder *hpo_dp_link_encoder = 55 pipe_ctx->link_res.hpo_dp_link_enc; 56 57 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder, 58 hpo_dp_stream_encoder->inst, 59 throttled_vcp_size); 60 } 61 62 static void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, 63 const struct dc_link_settings *link_settings, 64 struct fixed31_32 throttled_vcp_size) 65 { 66 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = 67 pipe_ctx->stream_res.hpo_dp_stream_enc; 68 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 69 struct fixed31_32 h_blank_in_ms, time_slot_in_ms, mtp_cnt_per_h_blank; 70 uint32_t link_bw_in_kbps = 71 dc_link_bandwidth_kbps(pipe_ctx->stream->link, link_settings); 72 uint16_t hblank_min_symbol_width = 0; 73 74 if (link_bw_in_kbps > 0) { 75 h_blank_in_ms = dc_fixpt_div(dc_fixpt_from_int( 76 timing->h_total - timing->h_addressable), 77 dc_fixpt_from_fraction(timing->pix_clk_100hz, 10)); 78 time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps); 79 mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms, 80 dc_fixpt_mul_int(time_slot_in_ms, 64)); 81 hblank_min_symbol_width = dc_fixpt_floor( 82 dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size)); 83 } 84 85 hpo_dp_stream_encoder->funcs->set_hblank_min_symbol_width(hpo_dp_stream_encoder, 86 hblank_min_symbol_width); 87 } 88 89 static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) 90 { 91 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 92 struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc; 93 94 stream_enc->funcs->enable_stream(stream_enc); 95 stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst); 96 } 97 98 static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) 99 { 100 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 101 102 stream_enc->funcs->disable(stream_enc); 103 } 104 105 static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) 106 { 107 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 108 struct dc_stream_state *stream = pipe_ctx->stream; 109 struct dc_link *link = stream->link; 110 111 stream_enc->funcs->set_stream_attribute( 112 stream_enc, 113 &stream->timing, 114 stream->output_color_space, 115 stream->use_vsc_sdp_for_colorimetry, 116 stream->timing.flags.DSC, 117 false); 118 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR); 119 } 120 121 static void enable_hpo_dp_fpga_link_output(struct dc_link *link, 122 const struct link_resource *link_res, 123 enum signal_type signal, 124 enum clock_source_id clock_source, 125 const struct dc_link_settings *link_settings) 126 { 127 const struct dc *dc = link->dc; 128 enum phyd32clk_clock_source phyd32clk = get_phyd32clk_src(link); 129 int phyd32clk_freq_khz = link_settings->link_rate == LINK_RATE_UHBR10 ? 312500 : 130 link_settings->link_rate == LINK_RATE_UHBR13_5 ? 412875 : 131 link_settings->link_rate == LINK_RATE_UHBR20 ? 625000 : 0; 132 133 dm_set_phyd32clk(dc->ctx, phyd32clk_freq_khz); 134 dc->res_pool->dccg->funcs->set_physymclk( 135 dc->res_pool->dccg, 136 link->link_enc_hw_inst, 137 PHYSYMCLK_FORCE_SRC_PHYD32CLK, 138 true); 139 dc->res_pool->dccg->funcs->enable_symclk32_le( 140 dc->res_pool->dccg, 141 link_res->hpo_dp_link_enc->inst, 142 phyd32clk); 143 link_res->hpo_dp_link_enc->funcs->link_enable( 144 link_res->hpo_dp_link_enc, 145 link_settings->lane_count); 146 147 } 148 149 static void enable_hpo_dp_link_output(struct dc_link *link, 150 const struct link_resource *link_res, 151 enum signal_type signal, 152 enum clock_source_id clock_source, 153 const struct dc_link_settings *link_settings) 154 { 155 if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment)) 156 enable_hpo_dp_fpga_link_output(link, link_res, signal, 157 clock_source, link_settings); 158 else 159 link_res->hpo_dp_link_enc->funcs->enable_link_phy( 160 link_res->hpo_dp_link_enc, 161 link_settings, 162 link->link_enc->transmitter, 163 link->link_enc->hpd_source); 164 } 165 166 167 static void disable_hpo_dp_fpga_link_output(struct dc_link *link, 168 const struct link_resource *link_res, 169 enum signal_type signal) 170 { 171 const struct dc *dc = link->dc; 172 173 link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc); 174 dc->res_pool->dccg->funcs->disable_symclk32_le( 175 dc->res_pool->dccg, 176 link_res->hpo_dp_link_enc->inst); 177 dc->res_pool->dccg->funcs->set_physymclk( 178 dc->res_pool->dccg, 179 link->link_enc_hw_inst, 180 PHYSYMCLK_FORCE_SRC_SYMCLK, 181 false); 182 dm_set_phyd32clk(dc->ctx, 0); 183 } 184 185 static void disable_hpo_dp_link_output(struct dc_link *link, 186 const struct link_resource *link_res, 187 enum signal_type signal) 188 { 189 if (IS_FPGA_MAXIMUS_DC(link->dc->ctx->dce_environment)) { 190 disable_hpo_dp_fpga_link_output(link, link_res, signal); 191 } else { 192 link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc); 193 link_res->hpo_dp_link_enc->funcs->disable_link_phy( 194 link_res->hpo_dp_link_enc, signal); 195 } 196 } 197 198 static void set_hpo_dp_link_test_pattern(struct dc_link *link, 199 const struct link_resource *link_res, 200 struct encoder_set_dp_phy_pattern_param *tp_params) 201 { 202 link_res->hpo_dp_link_enc->funcs->set_link_test_pattern( 203 link_res->hpo_dp_link_enc, tp_params); 204 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); 205 } 206 207 static void set_hpo_dp_lane_settings(struct dc_link *link, 208 const struct link_resource *link_res, 209 const struct dc_link_settings *link_settings, 210 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 211 { 212 link_res->hpo_dp_link_enc->funcs->set_ffe( 213 link_res->hpo_dp_link_enc, 214 link_settings, 215 lane_settings[0].FFE_PRESET.raw); 216 } 217 218 static void update_hpo_dp_stream_allocation_table(struct dc_link *link, 219 const struct link_resource *link_res, 220 const struct link_mst_stream_allocation_table *table) 221 { 222 link_res->hpo_dp_link_enc->funcs->update_stream_allocation_table( 223 link_res->hpo_dp_link_enc, 224 table); 225 } 226 227 static void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx, 228 struct audio_output *audio_output, uint32_t audio_inst) 229 { 230 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 231 pipe_ctx->stream_res.hpo_dp_stream_enc, 232 audio_inst, 233 &pipe_ctx->stream->audio_info); 234 } 235 236 static void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx) 237 { 238 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( 239 pipe_ctx->stream_res.hpo_dp_stream_enc); 240 } 241 242 static void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx) 243 { 244 if (pipe_ctx->stream_res.audio) 245 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 246 pipe_ctx->stream_res.hpo_dp_stream_enc); 247 } 248 249 static const struct link_hwss hpo_dp_link_hwss = { 250 .setup_stream_encoder = setup_hpo_dp_stream_encoder, 251 .reset_stream_encoder = reset_hpo_dp_stream_encoder, 252 .setup_stream_attribute = setup_hpo_dp_stream_attribute, 253 .disable_link_output = disable_hpo_dp_link_output, 254 .setup_audio_output = setup_hpo_dp_audio_output, 255 .enable_audio_packet = enable_hpo_dp_audio_packet, 256 .disable_audio_packet = disable_hpo_dp_audio_packet, 257 .ext = { 258 .set_throttled_vcp_size = set_hpo_dp_throttled_vcp_size, 259 .set_hblank_min_symbol_width = set_hpo_dp_hblank_min_symbol_width, 260 .enable_dp_link_output = enable_hpo_dp_link_output, 261 .set_dp_link_test_pattern = set_hpo_dp_link_test_pattern, 262 .set_dp_lane_settings = set_hpo_dp_lane_settings, 263 .update_stream_allocation_table = update_hpo_dp_stream_allocation_table, 264 }, 265 }; 266 267 bool can_use_hpo_dp_link_hwss(const struct dc_link *link, 268 const struct link_resource *link_res) 269 { 270 return link_res->hpo_dp_link_enc != NULL; 271 } 272 273 const struct link_hwss *get_hpo_dp_link_hwss(void) 274 { 275 return &hpo_dp_link_hwss; 276 } 277 278