1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "link_fpga.h" 26 #include "link/link_dpms.h" 27 #include "dm_helpers.h" 28 #include "link_hwss.h" 29 #include "dccg.h" 30 #include "resource.h" 31 32 #define DC_LOGGER_INIT(logger) 33 34 void dp_fpga_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx) 35 { 36 struct dc *dc = pipe_ctx->stream->ctx->dc; 37 struct dc_stream_state *stream = pipe_ctx->stream; 38 struct link_mst_stream_allocation_table proposed_table = {0}; 39 struct fixed31_32 avg_time_slots_per_mtp; 40 uint8_t req_slot_count = 0; 41 uint8_t vc_id = 1; /// VC ID always 1 for SST 42 struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings; 43 const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res); 44 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 45 46 stream->link->cur_link_settings = link_settings; 47 48 if (link_hwss->ext.enable_dp_link_output) 49 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res, 50 stream->signal, pipe_ctx->clock_source->id, 51 &link_settings); 52 53 /* Enable DP_STREAM_ENC */ 54 dc->hwss.enable_stream(pipe_ctx); 55 56 /* Set DPS PPS SDP (AKA "info frames") */ 57 if (pipe_ctx->stream->timing.flags.DSC) { 58 link_set_dsc_pps_packet(pipe_ctx, true, true); 59 } 60 61 /* Allocate Payload */ 62 if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) { 63 // MST case 64 uint8_t i; 65 66 proposed_table.stream_count = state->stream_count; 67 for (i = 0; i < state->stream_count; i++) { 68 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link); 69 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 70 proposed_table.stream_allocations[i].slot_count = req_slot_count; 71 proposed_table.stream_allocations[i].vcp_id = i+1; 72 /* NOTE: This makes assumption that pipe_ctx index is same as stream index */ 73 proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc; 74 } 75 } else { 76 // SST case 77 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, stream->link); 78 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 79 proposed_table.stream_count = 1; /// Always 1 stream for SST 80 proposed_table.stream_allocations[0].slot_count = req_slot_count; 81 proposed_table.stream_allocations[0].vcp_id = vc_id; 82 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 83 } 84 85 link_hwss->ext.update_stream_allocation_table(stream->link, 86 &pipe_ctx->link_res, 87 &proposed_table); 88 89 if (link_hwss->ext.set_throttled_vcp_size) 90 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 91 92 dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings); 93 dc->hwss.enable_audio_stream(pipe_ctx); 94 } 95 96