1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "irq_service_dcn302.h" 29 30 #include "../dce110/irq_service_dce110.h" 31 32 #include "dimgrey_cavefish_ip_offset.h" 33 #include "dcn/dcn_3_0_0_offset.h" 34 #include "dcn/dcn_3_0_0_sh_mask.h" 35 36 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 37 38 static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id) 39 { 40 switch (src_id) { 41 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 42 return DC_IRQ_SOURCE_VBLANK1; 43 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 44 return DC_IRQ_SOURCE_VBLANK2; 45 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 46 return DC_IRQ_SOURCE_VBLANK3; 47 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 48 return DC_IRQ_SOURCE_VBLANK4; 49 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 50 return DC_IRQ_SOURCE_VBLANK5; 51 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 52 return DC_IRQ_SOURCE_VBLANK6; 53 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 54 return DC_IRQ_SOURCE_PFLIP1; 55 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 56 return DC_IRQ_SOURCE_PFLIP2; 57 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 58 return DC_IRQ_SOURCE_PFLIP3; 59 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 60 return DC_IRQ_SOURCE_PFLIP4; 61 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 62 return DC_IRQ_SOURCE_PFLIP5; 63 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 64 return DC_IRQ_SOURCE_PFLIP6; 65 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 66 return DC_IRQ_SOURCE_VUPDATE1; 67 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 68 return DC_IRQ_SOURCE_VUPDATE2; 69 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 70 return DC_IRQ_SOURCE_VUPDATE3; 71 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 72 return DC_IRQ_SOURCE_VUPDATE4; 73 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 74 return DC_IRQ_SOURCE_VUPDATE5; 75 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 76 return DC_IRQ_SOURCE_VUPDATE6; 77 78 case DCN_1_0__SRCID__DC_HPD1_INT: 79 /* generic src_id for all HPD and HPDRX interrupts */ 80 switch (ext_id) { 81 case DCN_1_0__CTXID__DC_HPD1_INT: 82 return DC_IRQ_SOURCE_HPD1; 83 case DCN_1_0__CTXID__DC_HPD2_INT: 84 return DC_IRQ_SOURCE_HPD2; 85 case DCN_1_0__CTXID__DC_HPD3_INT: 86 return DC_IRQ_SOURCE_HPD3; 87 case DCN_1_0__CTXID__DC_HPD4_INT: 88 return DC_IRQ_SOURCE_HPD4; 89 case DCN_1_0__CTXID__DC_HPD5_INT: 90 return DC_IRQ_SOURCE_HPD5; 91 case DCN_1_0__CTXID__DC_HPD6_INT: 92 return DC_IRQ_SOURCE_HPD6; 93 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 94 return DC_IRQ_SOURCE_HPD1RX; 95 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 96 return DC_IRQ_SOURCE_HPD2RX; 97 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 98 return DC_IRQ_SOURCE_HPD3RX; 99 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 100 return DC_IRQ_SOURCE_HPD4RX; 101 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 102 return DC_IRQ_SOURCE_HPD5RX; 103 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 104 return DC_IRQ_SOURCE_HPD6RX; 105 default: 106 return DC_IRQ_SOURCE_INVALID; 107 } 108 break; 109 110 default: 111 return DC_IRQ_SOURCE_INVALID; 112 } 113 } 114 115 static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info) 116 { 117 uint32_t addr = info->status_reg; 118 uint32_t value = dm_read_reg(irq_service->ctx, addr); 119 uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED); 120 121 dal_irq_service_ack_generic(irq_service, info); 122 123 value = dm_read_reg(irq_service->ctx, info->enable_reg); 124 125 set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); 126 127 dm_write_reg(irq_service->ctx, info->enable_reg, value); 128 129 return true; 130 } 131 132 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 133 .set = NULL, 134 .ack = hpd_ack 135 }; 136 137 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 138 .set = NULL, 139 .ack = NULL 140 }; 141 142 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 143 .set = NULL, 144 .ack = NULL 145 }; 146 147 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 148 .set = NULL, 149 .ack = NULL 150 }; 151 152 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 153 .set = NULL, 154 .ack = NULL 155 }; 156 157 #undef BASE_INNER 158 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 159 160 /* compile time expand base address. */ 161 #define BASE(seg) BASE_INNER(seg) 162 163 #define SRI(reg_name, block, id)\ 164 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 mm ## block ## id ## _ ## reg_name 166 167 168 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 169 .enable_reg = SRI(reg1, block, reg_num),\ 170 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 171 .enable_value = {\ 172 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 173 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 174 },\ 175 .ack_reg = SRI(reg2, block, reg_num),\ 176 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 177 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 178 179 180 181 #define hpd_int_entry(reg_num)\ 182 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 183 IRQ_REG_ENTRY(HPD, reg_num,\ 184 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 185 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 186 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 187 .funcs = &hpd_irq_info_funcs\ 188 } 189 190 #define hpd_rx_int_entry(reg_num)\ 191 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 192 IRQ_REG_ENTRY(HPD, reg_num,\ 193 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 194 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 195 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 196 .funcs = &hpd_rx_irq_info_funcs\ 197 } 198 #define pflip_int_entry(reg_num)\ 199 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 200 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 201 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 202 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 203 .funcs = &pflip_irq_info_funcs\ 204 } 205 206 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 207 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 208 */ 209 #define vupdate_no_lock_int_entry(reg_num)\ 210 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 211 IRQ_REG_ENTRY(OTG, reg_num,\ 212 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 213 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 214 .funcs = &vupdate_no_lock_irq_info_funcs\ 215 } 216 217 #define vblank_int_entry(reg_num)\ 218 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 219 IRQ_REG_ENTRY(OTG, reg_num,\ 220 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 221 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 222 .funcs = &vblank_irq_info_funcs\ 223 } 224 225 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs } 226 227 #define i2c_int_entry(reg_num) \ 228 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 229 230 #define dp_sink_int_entry(reg_num) \ 231 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 232 233 #define gpio_pad_int_entry(reg_num) \ 234 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 235 236 #define dc_underflow_int_entry(reg_num) \ 237 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 238 239 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 240 .set = dal_irq_service_dummy_set, 241 .ack = dal_irq_service_dummy_ack 242 }; 243 244 static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBER] = { 245 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 246 hpd_int_entry(0), 247 hpd_int_entry(1), 248 hpd_int_entry(2), 249 hpd_int_entry(3), 250 hpd_int_entry(4), 251 hpd_rx_int_entry(0), 252 hpd_rx_int_entry(1), 253 hpd_rx_int_entry(2), 254 hpd_rx_int_entry(3), 255 hpd_rx_int_entry(4), 256 i2c_int_entry(1), 257 i2c_int_entry(2), 258 i2c_int_entry(3), 259 i2c_int_entry(4), 260 i2c_int_entry(5), 261 dp_sink_int_entry(1), 262 dp_sink_int_entry(2), 263 dp_sink_int_entry(3), 264 dp_sink_int_entry(4), 265 dp_sink_int_entry(5), 266 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 267 pflip_int_entry(0), 268 pflip_int_entry(1), 269 pflip_int_entry(2), 270 pflip_int_entry(3), 271 pflip_int_entry(4), 272 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 273 gpio_pad_int_entry(0), 274 gpio_pad_int_entry(1), 275 gpio_pad_int_entry(2), 276 gpio_pad_int_entry(3), 277 gpio_pad_int_entry(4), 278 gpio_pad_int_entry(5), 279 gpio_pad_int_entry(6), 280 gpio_pad_int_entry(7), 281 gpio_pad_int_entry(8), 282 gpio_pad_int_entry(9), 283 gpio_pad_int_entry(10), 284 gpio_pad_int_entry(11), 285 gpio_pad_int_entry(12), 286 gpio_pad_int_entry(13), 287 gpio_pad_int_entry(14), 288 gpio_pad_int_entry(15), 289 gpio_pad_int_entry(16), 290 gpio_pad_int_entry(17), 291 gpio_pad_int_entry(18), 292 gpio_pad_int_entry(19), 293 gpio_pad_int_entry(20), 294 gpio_pad_int_entry(21), 295 gpio_pad_int_entry(22), 296 gpio_pad_int_entry(23), 297 gpio_pad_int_entry(24), 298 gpio_pad_int_entry(25), 299 gpio_pad_int_entry(26), 300 gpio_pad_int_entry(27), 301 gpio_pad_int_entry(28), 302 gpio_pad_int_entry(29), 303 gpio_pad_int_entry(30), 304 dc_underflow_int_entry(1), 305 dc_underflow_int_entry(2), 306 dc_underflow_int_entry(3), 307 dc_underflow_int_entry(4), 308 dc_underflow_int_entry(5), 309 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 310 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 311 vupdate_no_lock_int_entry(0), 312 vupdate_no_lock_int_entry(1), 313 vupdate_no_lock_int_entry(2), 314 vupdate_no_lock_int_entry(3), 315 vupdate_no_lock_int_entry(4), 316 vblank_int_entry(0), 317 vblank_int_entry(1), 318 vblank_int_entry(2), 319 vblank_int_entry(3), 320 vblank_int_entry(4), 321 }; 322 323 static const struct irq_service_funcs irq_service_funcs_dcn302 = { 324 .to_dal_irq_source = to_dal_irq_source_dcn302 325 }; 326 327 static void dcn302_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data) 328 { 329 dal_irq_service_construct(irq_service, init_data); 330 331 irq_service->info = irq_source_info_dcn302; 332 irq_service->funcs = &irq_service_funcs_dcn302; 333 } 334 335 struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data) 336 { 337 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL); 338 339 if (!irq_service) 340 return NULL; 341 342 dcn302_irq_construct(irq_service, init_data); 343 return irq_service; 344 } 345