1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #if defined(CONFIG_DRM_AMD_DC_DCN) 26 27 #include "dm_services.h" 28 29 #include "include/logger_interface.h" 30 31 #include "../dce110/irq_service_dce110.h" 32 33 34 #include "sienna_cichlid_ip_offset.h" 35 #include "dcn/dcn_3_0_0_offset.h" 36 #include "dcn/dcn_3_0_0_sh_mask.h" 37 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "dpcs/dpcs_3_0_0_offset.h" 41 #include "dpcs/dpcs_3_0_0_sh_mask.h" 42 43 #include "mmhub/mmhub_2_0_0_offset.h" 44 #include "mmhub/mmhub_2_0_0_sh_mask.h" 45 46 #include "irq_service_dcn30.h" 47 48 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 49 50 static enum dc_irq_source to_dal_irq_source_dcn30( 51 struct irq_service *irq_service, 52 uint32_t src_id, 53 uint32_t ext_id) 54 { 55 switch (src_id) { 56 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 57 return DC_IRQ_SOURCE_VBLANK1; 58 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 59 return DC_IRQ_SOURCE_VBLANK2; 60 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 61 return DC_IRQ_SOURCE_VBLANK3; 62 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 63 return DC_IRQ_SOURCE_VBLANK4; 64 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 65 return DC_IRQ_SOURCE_VBLANK5; 66 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 67 return DC_IRQ_SOURCE_VBLANK6; 68 case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT: 69 return DC_IRQ_SOURCE_DMCUB_OUTBOX0; 70 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: 71 return DC_IRQ_SOURCE_DC1_VLINE0; 72 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: 73 return DC_IRQ_SOURCE_DC2_VLINE0; 74 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: 75 return DC_IRQ_SOURCE_DC3_VLINE0; 76 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: 77 return DC_IRQ_SOURCE_DC4_VLINE0; 78 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: 79 return DC_IRQ_SOURCE_DC5_VLINE0; 80 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: 81 return DC_IRQ_SOURCE_DC6_VLINE0; 82 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 83 return DC_IRQ_SOURCE_PFLIP1; 84 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 85 return DC_IRQ_SOURCE_PFLIP2; 86 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 87 return DC_IRQ_SOURCE_PFLIP3; 88 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 89 return DC_IRQ_SOURCE_PFLIP4; 90 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 91 return DC_IRQ_SOURCE_PFLIP5; 92 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 93 return DC_IRQ_SOURCE_PFLIP6; 94 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 95 return DC_IRQ_SOURCE_VUPDATE1; 96 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 97 return DC_IRQ_SOURCE_VUPDATE2; 98 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 99 return DC_IRQ_SOURCE_VUPDATE3; 100 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 101 return DC_IRQ_SOURCE_VUPDATE4; 102 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 103 return DC_IRQ_SOURCE_VUPDATE5; 104 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 105 return DC_IRQ_SOURCE_VUPDATE6; 106 107 case DCN_1_0__SRCID__DC_HPD1_INT: 108 /* generic src_id for all HPD and HPDRX interrupts */ 109 switch (ext_id) { 110 case DCN_1_0__CTXID__DC_HPD1_INT: 111 return DC_IRQ_SOURCE_HPD1; 112 case DCN_1_0__CTXID__DC_HPD2_INT: 113 return DC_IRQ_SOURCE_HPD2; 114 case DCN_1_0__CTXID__DC_HPD3_INT: 115 return DC_IRQ_SOURCE_HPD3; 116 case DCN_1_0__CTXID__DC_HPD4_INT: 117 return DC_IRQ_SOURCE_HPD4; 118 case DCN_1_0__CTXID__DC_HPD5_INT: 119 return DC_IRQ_SOURCE_HPD5; 120 case DCN_1_0__CTXID__DC_HPD6_INT: 121 return DC_IRQ_SOURCE_HPD6; 122 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 123 return DC_IRQ_SOURCE_HPD1RX; 124 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 125 return DC_IRQ_SOURCE_HPD2RX; 126 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 127 return DC_IRQ_SOURCE_HPD3RX; 128 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 129 return DC_IRQ_SOURCE_HPD4RX; 130 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 131 return DC_IRQ_SOURCE_HPD5RX; 132 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 133 return DC_IRQ_SOURCE_HPD6RX; 134 default: 135 return DC_IRQ_SOURCE_INVALID; 136 } 137 break; 138 139 default: 140 return DC_IRQ_SOURCE_INVALID; 141 } 142 } 143 144 static bool hpd_ack( 145 struct irq_service *irq_service, 146 const struct irq_source_info *info) 147 { 148 uint32_t addr = info->status_reg; 149 uint32_t value = dm_read_reg(irq_service->ctx, addr); 150 uint32_t current_status = 151 get_reg_field_value( 152 value, 153 HPD0_DC_HPD_INT_STATUS, 154 DC_HPD_SENSE_DELAYED); 155 156 dal_irq_service_ack_generic(irq_service, info); 157 158 value = dm_read_reg(irq_service->ctx, info->enable_reg); 159 160 set_reg_field_value( 161 value, 162 current_status ? 0 : 1, 163 HPD0_DC_HPD_INT_CONTROL, 164 DC_HPD_INT_POLARITY); 165 166 dm_write_reg(irq_service->ctx, info->enable_reg, value); 167 168 return true; 169 } 170 171 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 172 .set = NULL, 173 .ack = hpd_ack 174 }; 175 176 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 177 .set = NULL, 178 .ack = NULL 179 }; 180 181 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 182 .set = NULL, 183 .ack = NULL 184 }; 185 186 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 187 .set = NULL, 188 .ack = NULL 189 }; 190 191 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 192 .set = NULL, 193 .ack = NULL 194 }; 195 196 static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = { 197 .set = NULL, 198 .ack = NULL 199 }; 200 201 static const struct irq_source_info_funcs vline0_irq_info_funcs = { 202 .set = NULL, 203 .ack = NULL 204 }; 205 206 #undef BASE_INNER 207 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 208 209 /* compile time expand base address. */ 210 #define BASE(seg) \ 211 BASE_INNER(seg) 212 213 214 #define SRI(reg_name, block, id)\ 215 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 216 mm ## block ## id ## _ ## reg_name 217 218 #define SRI_DMUB(reg_name)\ 219 BASE(mm ## reg_name ## _BASE_IDX) + \ 220 mm ## reg_name 221 222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 223 .enable_reg = SRI(reg1, block, reg_num),\ 224 .enable_mask = \ 225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 226 .enable_value = {\ 227 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 228 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 229 },\ 230 .ack_reg = SRI(reg2, block, reg_num),\ 231 .ack_mask = \ 232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 233 .ack_value = \ 234 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 235 236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 237 .enable_reg = SRI_DMUB(reg1),\ 238 .enable_mask = \ 239 reg1 ## __ ## mask1 ## _MASK,\ 240 .enable_value = {\ 241 reg1 ## __ ## mask1 ## _MASK,\ 242 ~reg1 ## __ ## mask1 ## _MASK \ 243 },\ 244 .ack_reg = SRI_DMUB(reg2),\ 245 .ack_mask = \ 246 reg2 ## __ ## mask2 ## _MASK,\ 247 .ack_value = \ 248 reg2 ## __ ## mask2 ## _MASK \ 249 250 #define hpd_int_entry(reg_num)\ 251 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 252 IRQ_REG_ENTRY(HPD, reg_num,\ 253 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 254 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 255 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 256 .funcs = &hpd_irq_info_funcs\ 257 } 258 259 #define hpd_rx_int_entry(reg_num)\ 260 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 261 IRQ_REG_ENTRY(HPD, reg_num,\ 262 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 263 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 264 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 265 .funcs = &hpd_rx_irq_info_funcs\ 266 } 267 #define pflip_int_entry(reg_num)\ 268 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 269 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 270 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 271 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 272 .funcs = &pflip_irq_info_funcs\ 273 } 274 275 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 276 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 277 */ 278 #define vupdate_no_lock_int_entry(reg_num)\ 279 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 280 IRQ_REG_ENTRY(OTG, reg_num,\ 281 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 282 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 283 .funcs = &vupdate_no_lock_irq_info_funcs\ 284 } 285 286 #define vblank_int_entry(reg_num)\ 287 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 288 IRQ_REG_ENTRY(OTG, reg_num,\ 289 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 290 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 291 .funcs = &vblank_irq_info_funcs\ 292 } 293 294 #define vline0_int_entry(reg_num)\ 295 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ 296 IRQ_REG_ENTRY(OTG, reg_num,\ 297 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ 298 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ 299 .funcs = &vline0_irq_info_funcs\ 300 } 301 302 #define dmub_trace_int_entry()\ 303 [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\ 304 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\ 305 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\ 306 .funcs = &dmub_trace_irq_info_funcs\ 307 } 308 309 #define dummy_irq_entry() \ 310 {\ 311 .funcs = &dummy_irq_info_funcs\ 312 } 313 314 #define i2c_int_entry(reg_num) \ 315 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 316 317 #define dp_sink_int_entry(reg_num) \ 318 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 319 320 #define gpio_pad_int_entry(reg_num) \ 321 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 322 323 #define dc_underflow_int_entry(reg_num) \ 324 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 325 326 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 327 .set = dal_irq_service_dummy_set, 328 .ack = dal_irq_service_dummy_ack 329 }; 330 331 static const struct irq_source_info 332 irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = { 333 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 334 hpd_int_entry(0), 335 hpd_int_entry(1), 336 hpd_int_entry(2), 337 hpd_int_entry(3), 338 hpd_int_entry(4), 339 hpd_int_entry(5), 340 hpd_rx_int_entry(0), 341 hpd_rx_int_entry(1), 342 hpd_rx_int_entry(2), 343 hpd_rx_int_entry(3), 344 hpd_rx_int_entry(4), 345 hpd_rx_int_entry(5), 346 i2c_int_entry(1), 347 i2c_int_entry(2), 348 i2c_int_entry(3), 349 i2c_int_entry(4), 350 i2c_int_entry(5), 351 i2c_int_entry(6), 352 dp_sink_int_entry(1), 353 dp_sink_int_entry(2), 354 dp_sink_int_entry(3), 355 dp_sink_int_entry(4), 356 dp_sink_int_entry(5), 357 dp_sink_int_entry(6), 358 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 359 pflip_int_entry(0), 360 pflip_int_entry(1), 361 pflip_int_entry(2), 362 pflip_int_entry(3), 363 pflip_int_entry(4), 364 pflip_int_entry(5), 365 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 366 gpio_pad_int_entry(0), 367 gpio_pad_int_entry(1), 368 gpio_pad_int_entry(2), 369 gpio_pad_int_entry(3), 370 gpio_pad_int_entry(4), 371 gpio_pad_int_entry(5), 372 gpio_pad_int_entry(6), 373 gpio_pad_int_entry(7), 374 gpio_pad_int_entry(8), 375 gpio_pad_int_entry(9), 376 gpio_pad_int_entry(10), 377 gpio_pad_int_entry(11), 378 gpio_pad_int_entry(12), 379 gpio_pad_int_entry(13), 380 gpio_pad_int_entry(14), 381 gpio_pad_int_entry(15), 382 gpio_pad_int_entry(16), 383 gpio_pad_int_entry(17), 384 gpio_pad_int_entry(18), 385 gpio_pad_int_entry(19), 386 gpio_pad_int_entry(20), 387 gpio_pad_int_entry(21), 388 gpio_pad_int_entry(22), 389 gpio_pad_int_entry(23), 390 gpio_pad_int_entry(24), 391 gpio_pad_int_entry(25), 392 gpio_pad_int_entry(26), 393 gpio_pad_int_entry(27), 394 gpio_pad_int_entry(28), 395 gpio_pad_int_entry(29), 396 gpio_pad_int_entry(30), 397 dc_underflow_int_entry(1), 398 dc_underflow_int_entry(2), 399 dc_underflow_int_entry(3), 400 dc_underflow_int_entry(4), 401 dc_underflow_int_entry(5), 402 dc_underflow_int_entry(6), 403 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 404 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 405 vupdate_no_lock_int_entry(0), 406 vupdate_no_lock_int_entry(1), 407 vupdate_no_lock_int_entry(2), 408 vupdate_no_lock_int_entry(3), 409 vupdate_no_lock_int_entry(4), 410 vupdate_no_lock_int_entry(5), 411 vblank_int_entry(0), 412 vblank_int_entry(1), 413 vblank_int_entry(2), 414 vblank_int_entry(3), 415 vblank_int_entry(4), 416 vblank_int_entry(5), 417 vline0_int_entry(0), 418 vline0_int_entry(1), 419 vline0_int_entry(2), 420 vline0_int_entry(3), 421 vline0_int_entry(4), 422 vline0_int_entry(5), 423 dmub_trace_int_entry(), 424 }; 425 426 static const struct irq_service_funcs irq_service_funcs_dcn30 = { 427 .to_dal_irq_source = to_dal_irq_source_dcn30 428 }; 429 430 static void dcn30_irq_construct( 431 struct irq_service *irq_service, 432 struct irq_service_init_data *init_data) 433 { 434 dal_irq_service_construct(irq_service, init_data); 435 436 irq_service->info = irq_source_info_dcn30; 437 irq_service->funcs = &irq_service_funcs_dcn30; 438 } 439 440 struct irq_service *dal_irq_service_dcn30_create( 441 struct irq_service_init_data *init_data) 442 { 443 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 444 GFP_KERNEL); 445 446 if (!irq_service) 447 return NULL; 448 449 dcn30_irq_construct(irq_service, init_data); 450 return irq_service; 451 } 452 453 #endif 454