1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #if defined(CONFIG_DRM_AMD_DC_DCN) 26 27 #include "dm_services.h" 28 29 #include "include/logger_interface.h" 30 31 #include "../dce110/irq_service_dce110.h" 32 33 34 #include "sienna_cichlid_ip_offset.h" 35 #include "dcn/dcn_3_0_0_offset.h" 36 #include "dcn/dcn_3_0_0_sh_mask.h" 37 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "dcn/dpcs_3_0_0_offset.h" 41 #include "dcn/dpcs_3_0_0_sh_mask.h" 42 43 #include "mmhub/mmhub_2_0_0_offset.h" 44 #include "mmhub/mmhub_2_0_0_sh_mask.h" 45 46 #include "irq_service_dcn30.h" 47 48 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 49 50 enum dc_irq_source to_dal_irq_source_dcn30( 51 struct irq_service *irq_service, 52 uint32_t src_id, 53 uint32_t ext_id) 54 { 55 switch (src_id) { 56 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 57 return DC_IRQ_SOURCE_VBLANK1; 58 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 59 return DC_IRQ_SOURCE_VBLANK2; 60 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 61 return DC_IRQ_SOURCE_VBLANK3; 62 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 63 return DC_IRQ_SOURCE_VBLANK4; 64 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 65 return DC_IRQ_SOURCE_VBLANK5; 66 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 67 return DC_IRQ_SOURCE_VBLANK6; 68 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 69 return DC_IRQ_SOURCE_PFLIP1; 70 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 71 return DC_IRQ_SOURCE_PFLIP2; 72 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 73 return DC_IRQ_SOURCE_PFLIP3; 74 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 75 return DC_IRQ_SOURCE_PFLIP4; 76 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 77 return DC_IRQ_SOURCE_PFLIP5; 78 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 79 return DC_IRQ_SOURCE_PFLIP6; 80 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 81 return DC_IRQ_SOURCE_VUPDATE1; 82 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 83 return DC_IRQ_SOURCE_VUPDATE2; 84 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 85 return DC_IRQ_SOURCE_VUPDATE3; 86 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 87 return DC_IRQ_SOURCE_VUPDATE4; 88 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 89 return DC_IRQ_SOURCE_VUPDATE5; 90 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 91 return DC_IRQ_SOURCE_VUPDATE6; 92 93 case DCN_1_0__SRCID__DC_HPD1_INT: 94 /* generic src_id for all HPD and HPDRX interrupts */ 95 switch (ext_id) { 96 case DCN_1_0__CTXID__DC_HPD1_INT: 97 return DC_IRQ_SOURCE_HPD1; 98 case DCN_1_0__CTXID__DC_HPD2_INT: 99 return DC_IRQ_SOURCE_HPD2; 100 case DCN_1_0__CTXID__DC_HPD3_INT: 101 return DC_IRQ_SOURCE_HPD3; 102 case DCN_1_0__CTXID__DC_HPD4_INT: 103 return DC_IRQ_SOURCE_HPD4; 104 case DCN_1_0__CTXID__DC_HPD5_INT: 105 return DC_IRQ_SOURCE_HPD5; 106 case DCN_1_0__CTXID__DC_HPD6_INT: 107 return DC_IRQ_SOURCE_HPD6; 108 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 109 return DC_IRQ_SOURCE_HPD1RX; 110 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 111 return DC_IRQ_SOURCE_HPD2RX; 112 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 113 return DC_IRQ_SOURCE_HPD3RX; 114 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 115 return DC_IRQ_SOURCE_HPD4RX; 116 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 117 return DC_IRQ_SOURCE_HPD5RX; 118 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 119 return DC_IRQ_SOURCE_HPD6RX; 120 default: 121 return DC_IRQ_SOURCE_INVALID; 122 } 123 break; 124 125 default: 126 return DC_IRQ_SOURCE_INVALID; 127 } 128 } 129 130 static bool hpd_ack( 131 struct irq_service *irq_service, 132 const struct irq_source_info *info) 133 { 134 uint32_t addr = info->status_reg; 135 uint32_t value = dm_read_reg(irq_service->ctx, addr); 136 uint32_t current_status = 137 get_reg_field_value( 138 value, 139 HPD0_DC_HPD_INT_STATUS, 140 DC_HPD_SENSE_DELAYED); 141 142 dal_irq_service_ack_generic(irq_service, info); 143 144 value = dm_read_reg(irq_service->ctx, info->enable_reg); 145 146 set_reg_field_value( 147 value, 148 current_status ? 0 : 1, 149 HPD0_DC_HPD_INT_CONTROL, 150 DC_HPD_INT_POLARITY); 151 152 dm_write_reg(irq_service->ctx, info->enable_reg, value); 153 154 return true; 155 } 156 157 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 158 .set = NULL, 159 .ack = hpd_ack 160 }; 161 162 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 163 .set = NULL, 164 .ack = NULL 165 }; 166 167 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 168 .set = NULL, 169 .ack = NULL 170 }; 171 172 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 173 .set = NULL, 174 .ack = NULL 175 }; 176 177 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 178 .set = NULL, 179 .ack = NULL 180 }; 181 182 #undef BASE_INNER 183 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 184 185 /* compile time expand base address. */ 186 #define BASE(seg) \ 187 BASE_INNER(seg) 188 189 190 #define SRI(reg_name, block, id)\ 191 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 192 mm ## block ## id ## _ ## reg_name 193 194 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 196 .enable_reg = SRI(reg1, block, reg_num),\ 197 .enable_mask = \ 198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 199 .enable_value = {\ 200 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 201 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 202 },\ 203 .ack_reg = SRI(reg2, block, reg_num),\ 204 .ack_mask = \ 205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 206 .ack_value = \ 207 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 208 209 210 211 #define hpd_int_entry(reg_num)\ 212 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 213 IRQ_REG_ENTRY(HPD, reg_num,\ 214 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 215 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 216 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 217 .funcs = &hpd_irq_info_funcs\ 218 } 219 220 #define hpd_rx_int_entry(reg_num)\ 221 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 222 IRQ_REG_ENTRY(HPD, reg_num,\ 223 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 224 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 225 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 226 .funcs = &hpd_rx_irq_info_funcs\ 227 } 228 #define pflip_int_entry(reg_num)\ 229 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 230 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 231 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 232 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 233 .funcs = &pflip_irq_info_funcs\ 234 } 235 236 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 237 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 238 */ 239 #define vupdate_no_lock_int_entry(reg_num)\ 240 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 241 IRQ_REG_ENTRY(OTG, reg_num,\ 242 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 243 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 244 .funcs = &vupdate_no_lock_irq_info_funcs\ 245 } 246 247 #define vblank_int_entry(reg_num)\ 248 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 249 IRQ_REG_ENTRY(OTG, reg_num,\ 250 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 251 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 252 .funcs = &vblank_irq_info_funcs\ 253 } 254 255 #define dummy_irq_entry() \ 256 {\ 257 .funcs = &dummy_irq_info_funcs\ 258 } 259 260 #define i2c_int_entry(reg_num) \ 261 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 262 263 #define dp_sink_int_entry(reg_num) \ 264 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 265 266 #define gpio_pad_int_entry(reg_num) \ 267 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 268 269 #define dc_underflow_int_entry(reg_num) \ 270 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 271 272 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 273 .set = dal_irq_service_dummy_set, 274 .ack = dal_irq_service_dummy_ack 275 }; 276 277 static const struct irq_source_info 278 irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = { 279 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 280 hpd_int_entry(0), 281 hpd_int_entry(1), 282 hpd_int_entry(2), 283 hpd_int_entry(3), 284 hpd_int_entry(4), 285 hpd_int_entry(5), 286 hpd_rx_int_entry(0), 287 hpd_rx_int_entry(1), 288 hpd_rx_int_entry(2), 289 hpd_rx_int_entry(3), 290 hpd_rx_int_entry(4), 291 hpd_rx_int_entry(5), 292 i2c_int_entry(1), 293 i2c_int_entry(2), 294 i2c_int_entry(3), 295 i2c_int_entry(4), 296 i2c_int_entry(5), 297 i2c_int_entry(6), 298 dp_sink_int_entry(1), 299 dp_sink_int_entry(2), 300 dp_sink_int_entry(3), 301 dp_sink_int_entry(4), 302 dp_sink_int_entry(5), 303 dp_sink_int_entry(6), 304 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 305 pflip_int_entry(0), 306 pflip_int_entry(1), 307 pflip_int_entry(2), 308 pflip_int_entry(3), 309 pflip_int_entry(4), 310 pflip_int_entry(5), 311 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 312 gpio_pad_int_entry(0), 313 gpio_pad_int_entry(1), 314 gpio_pad_int_entry(2), 315 gpio_pad_int_entry(3), 316 gpio_pad_int_entry(4), 317 gpio_pad_int_entry(5), 318 gpio_pad_int_entry(6), 319 gpio_pad_int_entry(7), 320 gpio_pad_int_entry(8), 321 gpio_pad_int_entry(9), 322 gpio_pad_int_entry(10), 323 gpio_pad_int_entry(11), 324 gpio_pad_int_entry(12), 325 gpio_pad_int_entry(13), 326 gpio_pad_int_entry(14), 327 gpio_pad_int_entry(15), 328 gpio_pad_int_entry(16), 329 gpio_pad_int_entry(17), 330 gpio_pad_int_entry(18), 331 gpio_pad_int_entry(19), 332 gpio_pad_int_entry(20), 333 gpio_pad_int_entry(21), 334 gpio_pad_int_entry(22), 335 gpio_pad_int_entry(23), 336 gpio_pad_int_entry(24), 337 gpio_pad_int_entry(25), 338 gpio_pad_int_entry(26), 339 gpio_pad_int_entry(27), 340 gpio_pad_int_entry(28), 341 gpio_pad_int_entry(29), 342 gpio_pad_int_entry(30), 343 dc_underflow_int_entry(1), 344 dc_underflow_int_entry(2), 345 dc_underflow_int_entry(3), 346 dc_underflow_int_entry(4), 347 dc_underflow_int_entry(5), 348 dc_underflow_int_entry(6), 349 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 350 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 351 vupdate_no_lock_int_entry(0), 352 vupdate_no_lock_int_entry(1), 353 vupdate_no_lock_int_entry(2), 354 vupdate_no_lock_int_entry(3), 355 vupdate_no_lock_int_entry(4), 356 vupdate_no_lock_int_entry(5), 357 vblank_int_entry(0), 358 vblank_int_entry(1), 359 vblank_int_entry(2), 360 vblank_int_entry(3), 361 vblank_int_entry(4), 362 vblank_int_entry(5), 363 }; 364 365 static const struct irq_service_funcs irq_service_funcs_dcn30 = { 366 .to_dal_irq_source = to_dal_irq_source_dcn30 367 }; 368 369 static void dcn30_irq_construct( 370 struct irq_service *irq_service, 371 struct irq_service_init_data *init_data) 372 { 373 dal_irq_service_construct(irq_service, init_data); 374 375 irq_service->info = irq_source_info_dcn30; 376 irq_service->funcs = &irq_service_funcs_dcn30; 377 } 378 379 struct irq_service *dal_irq_service_dcn30_create( 380 struct irq_service_init_data *init_data) 381 { 382 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 383 GFP_KERNEL); 384 385 if (!irq_service) 386 return NULL; 387 388 dcn30_irq_construct(irq_service, init_data); 389 return irq_service; 390 } 391 392 #endif 393