1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "include/logger_interface.h" 31 32 #include "../dce110/irq_service_dce110.h" 33 34 #include "dcn/dcn_2_1_0_offset.h" 35 #include "dcn/dcn_2_1_0_sh_mask.h" 36 #include "renoir_ip_offset.h" 37 38 39 #include "irq_service_dcn21.h" 40 41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 42 43 enum dc_irq_source to_dal_irq_source_dcn21( 44 struct irq_service *irq_service, 45 uint32_t src_id, 46 uint32_t ext_id) 47 { 48 switch (src_id) { 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 50 return DC_IRQ_SOURCE_VBLANK1; 51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 52 return DC_IRQ_SOURCE_VBLANK2; 53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 54 return DC_IRQ_SOURCE_VBLANK3; 55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 56 return DC_IRQ_SOURCE_VBLANK4; 57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 58 return DC_IRQ_SOURCE_VBLANK5; 59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 60 return DC_IRQ_SOURCE_VBLANK6; 61 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 62 return DC_IRQ_SOURCE_PFLIP1; 63 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 64 return DC_IRQ_SOURCE_PFLIP2; 65 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 66 return DC_IRQ_SOURCE_PFLIP3; 67 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 68 return DC_IRQ_SOURCE_PFLIP4; 69 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 70 return DC_IRQ_SOURCE_PFLIP5; 71 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 72 return DC_IRQ_SOURCE_PFLIP6; 73 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 74 return DC_IRQ_SOURCE_VUPDATE1; 75 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 76 return DC_IRQ_SOURCE_VUPDATE2; 77 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 78 return DC_IRQ_SOURCE_VUPDATE3; 79 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 80 return DC_IRQ_SOURCE_VUPDATE4; 81 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 82 return DC_IRQ_SOURCE_VUPDATE5; 83 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 84 return DC_IRQ_SOURCE_VUPDATE6; 85 86 case DCN_1_0__SRCID__DC_HPD1_INT: 87 /* generic src_id for all HPD and HPDRX interrupts */ 88 switch (ext_id) { 89 case DCN_1_0__CTXID__DC_HPD1_INT: 90 return DC_IRQ_SOURCE_HPD1; 91 case DCN_1_0__CTXID__DC_HPD2_INT: 92 return DC_IRQ_SOURCE_HPD2; 93 case DCN_1_0__CTXID__DC_HPD3_INT: 94 return DC_IRQ_SOURCE_HPD3; 95 case DCN_1_0__CTXID__DC_HPD4_INT: 96 return DC_IRQ_SOURCE_HPD4; 97 case DCN_1_0__CTXID__DC_HPD5_INT: 98 return DC_IRQ_SOURCE_HPD5; 99 case DCN_1_0__CTXID__DC_HPD6_INT: 100 return DC_IRQ_SOURCE_HPD6; 101 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 102 return DC_IRQ_SOURCE_HPD1RX; 103 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 104 return DC_IRQ_SOURCE_HPD2RX; 105 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 106 return DC_IRQ_SOURCE_HPD3RX; 107 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 108 return DC_IRQ_SOURCE_HPD4RX; 109 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 110 return DC_IRQ_SOURCE_HPD5RX; 111 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 112 return DC_IRQ_SOURCE_HPD6RX; 113 default: 114 return DC_IRQ_SOURCE_INVALID; 115 } 116 break; 117 118 default: 119 break; 120 } 121 return DC_IRQ_SOURCE_INVALID; 122 } 123 124 static bool hpd_ack( 125 struct irq_service *irq_service, 126 const struct irq_source_info *info) 127 { 128 uint32_t addr = info->status_reg; 129 uint32_t value = dm_read_reg(irq_service->ctx, addr); 130 uint32_t current_status = 131 get_reg_field_value( 132 value, 133 HPD0_DC_HPD_INT_STATUS, 134 DC_HPD_SENSE_DELAYED); 135 136 dal_irq_service_ack_generic(irq_service, info); 137 138 value = dm_read_reg(irq_service->ctx, info->enable_reg); 139 140 set_reg_field_value( 141 value, 142 current_status ? 0 : 1, 143 HPD0_DC_HPD_INT_CONTROL, 144 DC_HPD_INT_POLARITY); 145 146 dm_write_reg(irq_service->ctx, info->enable_reg, value); 147 148 return true; 149 } 150 151 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 152 .set = NULL, 153 .ack = hpd_ack 154 }; 155 156 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 157 .set = NULL, 158 .ack = NULL 159 }; 160 161 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 162 .set = NULL, 163 .ack = NULL 164 }; 165 166 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 167 .set = NULL, 168 .ack = NULL 169 }; 170 171 #undef BASE_INNER 172 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 173 174 /* compile time expand base address. */ 175 #define BASE(seg) \ 176 BASE_INNER(seg) 177 178 179 #define SRI(reg_name, block, id)\ 180 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 mm ## block ## id ## _ ## reg_name 182 183 184 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 185 .enable_reg = SRI(reg1, block, reg_num),\ 186 .enable_mask = \ 187 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 188 .enable_value = {\ 189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 190 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 191 },\ 192 .ack_reg = SRI(reg2, block, reg_num),\ 193 .ack_mask = \ 194 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 195 .ack_value = \ 196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 197 198 199 200 #define hpd_int_entry(reg_num)\ 201 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 202 IRQ_REG_ENTRY(HPD, reg_num,\ 203 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 204 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 205 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 206 .funcs = &hpd_irq_info_funcs\ 207 } 208 209 #define hpd_rx_int_entry(reg_num)\ 210 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 211 IRQ_REG_ENTRY(HPD, reg_num,\ 212 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 213 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 214 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 215 .funcs = &hpd_rx_irq_info_funcs\ 216 } 217 #define pflip_int_entry(reg_num)\ 218 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 219 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 220 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 221 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 222 .funcs = &pflip_irq_info_funcs\ 223 } 224 225 #define vupdate_int_entry(reg_num)\ 226 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 227 IRQ_REG_ENTRY(OTG, reg_num,\ 228 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ 229 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ 230 .funcs = &vblank_irq_info_funcs\ 231 } 232 233 #define vblank_int_entry(reg_num)\ 234 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 235 IRQ_REG_ENTRY(OTG, reg_num,\ 236 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 237 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 238 .funcs = &vblank_irq_info_funcs\ 239 } 240 241 #define dummy_irq_entry() \ 242 {\ 243 .funcs = &dummy_irq_info_funcs\ 244 } 245 246 #define i2c_int_entry(reg_num) \ 247 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 248 249 #define dp_sink_int_entry(reg_num) \ 250 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 251 252 #define gpio_pad_int_entry(reg_num) \ 253 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 254 255 #define dc_underflow_int_entry(reg_num) \ 256 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 257 258 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 259 .set = dal_irq_service_dummy_set, 260 .ack = dal_irq_service_dummy_ack 261 }; 262 263 static const struct irq_source_info 264 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = { 265 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 266 hpd_int_entry(0), 267 hpd_int_entry(1), 268 hpd_int_entry(2), 269 hpd_int_entry(3), 270 hpd_int_entry(4), 271 hpd_rx_int_entry(0), 272 hpd_rx_int_entry(1), 273 hpd_rx_int_entry(2), 274 hpd_rx_int_entry(3), 275 hpd_rx_int_entry(4), 276 i2c_int_entry(1), 277 i2c_int_entry(2), 278 i2c_int_entry(3), 279 i2c_int_entry(4), 280 i2c_int_entry(5), 281 i2c_int_entry(6), 282 dp_sink_int_entry(1), 283 dp_sink_int_entry(2), 284 dp_sink_int_entry(3), 285 dp_sink_int_entry(4), 286 dp_sink_int_entry(5), 287 dp_sink_int_entry(6), 288 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 289 pflip_int_entry(0), 290 pflip_int_entry(1), 291 pflip_int_entry(2), 292 pflip_int_entry(3), 293 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 294 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 295 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 296 gpio_pad_int_entry(0), 297 gpio_pad_int_entry(1), 298 gpio_pad_int_entry(2), 299 gpio_pad_int_entry(3), 300 gpio_pad_int_entry(4), 301 gpio_pad_int_entry(5), 302 gpio_pad_int_entry(6), 303 gpio_pad_int_entry(7), 304 gpio_pad_int_entry(8), 305 gpio_pad_int_entry(9), 306 gpio_pad_int_entry(10), 307 gpio_pad_int_entry(11), 308 gpio_pad_int_entry(12), 309 gpio_pad_int_entry(13), 310 gpio_pad_int_entry(14), 311 gpio_pad_int_entry(15), 312 gpio_pad_int_entry(16), 313 gpio_pad_int_entry(17), 314 gpio_pad_int_entry(18), 315 gpio_pad_int_entry(19), 316 gpio_pad_int_entry(20), 317 gpio_pad_int_entry(21), 318 gpio_pad_int_entry(22), 319 gpio_pad_int_entry(23), 320 gpio_pad_int_entry(24), 321 gpio_pad_int_entry(25), 322 gpio_pad_int_entry(26), 323 gpio_pad_int_entry(27), 324 gpio_pad_int_entry(28), 325 gpio_pad_int_entry(29), 326 gpio_pad_int_entry(30), 327 dc_underflow_int_entry(1), 328 dc_underflow_int_entry(2), 329 dc_underflow_int_entry(3), 330 dc_underflow_int_entry(4), 331 dc_underflow_int_entry(5), 332 dc_underflow_int_entry(6), 333 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 334 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 335 vupdate_int_entry(0), 336 vupdate_int_entry(1), 337 vupdate_int_entry(2), 338 vupdate_int_entry(3), 339 vupdate_int_entry(4), 340 vupdate_int_entry(5), 341 vblank_int_entry(0), 342 vblank_int_entry(1), 343 vblank_int_entry(2), 344 vblank_int_entry(3), 345 vblank_int_entry(4), 346 vblank_int_entry(5), 347 }; 348 349 static const struct irq_service_funcs irq_service_funcs_dcn21 = { 350 .to_dal_irq_source = to_dal_irq_source_dcn21 351 }; 352 353 static void dcn21_irq_construct( 354 struct irq_service *irq_service, 355 struct irq_service_init_data *init_data) 356 { 357 dal_irq_service_construct(irq_service, init_data); 358 359 irq_service->info = irq_source_info_dcn21; 360 irq_service->funcs = &irq_service_funcs_dcn21; 361 } 362 363 struct irq_service *dal_irq_service_dcn21_create( 364 struct irq_service_init_data *init_data) 365 { 366 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 367 GFP_KERNEL); 368 369 if (!irq_service) 370 return NULL; 371 372 dcn21_irq_construct(irq_service, init_data); 373 return irq_service; 374 } 375