1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "include/logger_interface.h" 31 32 #include "../dce110/irq_service_dce110.h" 33 34 #include "dcn/dcn_2_1_0_offset.h" 35 #include "dcn/dcn_2_1_0_sh_mask.h" 36 #include "renoir_ip_offset.h" 37 38 39 #include "irq_service_dcn21.h" 40 41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 42 43 enum dc_irq_source to_dal_irq_source_dcn21( 44 struct irq_service *irq_service, 45 uint32_t src_id, 46 uint32_t ext_id) 47 { 48 switch (src_id) { 49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 50 return DC_IRQ_SOURCE_VBLANK1; 51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 52 return DC_IRQ_SOURCE_VBLANK2; 53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 54 return DC_IRQ_SOURCE_VBLANK3; 55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 56 return DC_IRQ_SOURCE_VBLANK4; 57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 58 return DC_IRQ_SOURCE_VBLANK5; 59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 60 return DC_IRQ_SOURCE_VBLANK6; 61 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 62 return DC_IRQ_SOURCE_PFLIP1; 63 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 64 return DC_IRQ_SOURCE_PFLIP2; 65 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 66 return DC_IRQ_SOURCE_PFLIP3; 67 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 68 return DC_IRQ_SOURCE_PFLIP4; 69 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 70 return DC_IRQ_SOURCE_PFLIP5; 71 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 72 return DC_IRQ_SOURCE_PFLIP6; 73 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 74 return DC_IRQ_SOURCE_VUPDATE1; 75 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 76 return DC_IRQ_SOURCE_VUPDATE2; 77 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 78 return DC_IRQ_SOURCE_VUPDATE3; 79 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 80 return DC_IRQ_SOURCE_VUPDATE4; 81 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 82 return DC_IRQ_SOURCE_VUPDATE5; 83 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 84 return DC_IRQ_SOURCE_VUPDATE6; 85 86 case DCN_1_0__SRCID__DC_HPD1_INT: 87 /* generic src_id for all HPD and HPDRX interrupts */ 88 switch (ext_id) { 89 case DCN_1_0__CTXID__DC_HPD1_INT: 90 return DC_IRQ_SOURCE_HPD1; 91 case DCN_1_0__CTXID__DC_HPD2_INT: 92 return DC_IRQ_SOURCE_HPD2; 93 case DCN_1_0__CTXID__DC_HPD3_INT: 94 return DC_IRQ_SOURCE_HPD3; 95 case DCN_1_0__CTXID__DC_HPD4_INT: 96 return DC_IRQ_SOURCE_HPD4; 97 case DCN_1_0__CTXID__DC_HPD5_INT: 98 return DC_IRQ_SOURCE_HPD5; 99 case DCN_1_0__CTXID__DC_HPD6_INT: 100 return DC_IRQ_SOURCE_HPD6; 101 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 102 return DC_IRQ_SOURCE_HPD1RX; 103 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 104 return DC_IRQ_SOURCE_HPD2RX; 105 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 106 return DC_IRQ_SOURCE_HPD3RX; 107 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 108 return DC_IRQ_SOURCE_HPD4RX; 109 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 110 return DC_IRQ_SOURCE_HPD5RX; 111 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 112 return DC_IRQ_SOURCE_HPD6RX; 113 default: 114 return DC_IRQ_SOURCE_INVALID; 115 } 116 break; 117 118 default: 119 break; 120 } 121 return DC_IRQ_SOURCE_INVALID; 122 } 123 124 static bool hpd_ack( 125 struct irq_service *irq_service, 126 const struct irq_source_info *info) 127 { 128 uint32_t addr = info->status_reg; 129 uint32_t value = dm_read_reg(irq_service->ctx, addr); 130 uint32_t current_status = 131 get_reg_field_value( 132 value, 133 HPD0_DC_HPD_INT_STATUS, 134 DC_HPD_SENSE_DELAYED); 135 136 dal_irq_service_ack_generic(irq_service, info); 137 138 value = dm_read_reg(irq_service->ctx, info->enable_reg); 139 140 set_reg_field_value( 141 value, 142 current_status ? 0 : 1, 143 HPD0_DC_HPD_INT_CONTROL, 144 DC_HPD_INT_POLARITY); 145 146 dm_write_reg(irq_service->ctx, info->enable_reg, value); 147 148 return true; 149 } 150 151 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 152 .set = NULL, 153 .ack = hpd_ack 154 }; 155 156 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 157 .set = NULL, 158 .ack = NULL 159 }; 160 161 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 162 .set = NULL, 163 .ack = NULL 164 }; 165 166 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 167 .set = NULL, 168 .ack = NULL 169 }; 170 171 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 172 .set = NULL, 173 .ack = NULL 174 }; 175 176 #undef BASE_INNER 177 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 178 179 /* compile time expand base address. */ 180 #define BASE(seg) \ 181 BASE_INNER(seg) 182 183 184 #define SRI(reg_name, block, id)\ 185 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 186 mm ## block ## id ## _ ## reg_name 187 188 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 190 .enable_reg = SRI(reg1, block, reg_num),\ 191 .enable_mask = \ 192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 193 .enable_value = {\ 194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 196 },\ 197 .ack_reg = SRI(reg2, block, reg_num),\ 198 .ack_mask = \ 199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 200 .ack_value = \ 201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 202 203 204 205 #define hpd_int_entry(reg_num)\ 206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 207 IRQ_REG_ENTRY(HPD, reg_num,\ 208 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 209 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 211 .funcs = &hpd_irq_info_funcs\ 212 } 213 214 #define hpd_rx_int_entry(reg_num)\ 215 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 216 IRQ_REG_ENTRY(HPD, reg_num,\ 217 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 218 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 220 .funcs = &hpd_rx_irq_info_funcs\ 221 } 222 #define pflip_int_entry(reg_num)\ 223 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 225 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 226 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 227 .funcs = &pflip_irq_info_funcs\ 228 } 229 230 #define vupdate_int_entry(reg_num)\ 231 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 232 IRQ_REG_ENTRY(OTG, reg_num,\ 233 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ 234 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ 235 .funcs = &vblank_irq_info_funcs\ 236 } 237 238 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 239 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 240 */ 241 #define vupdate_no_lock_int_entry(reg_num)\ 242 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 243 IRQ_REG_ENTRY(OTG, reg_num,\ 244 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 245 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 246 .funcs = &vupdate_no_lock_irq_info_funcs\ 247 } 248 249 #define vblank_int_entry(reg_num)\ 250 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 251 IRQ_REG_ENTRY(OTG, reg_num,\ 252 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 253 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 254 .funcs = &vblank_irq_info_funcs\ 255 } 256 257 #define dummy_irq_entry() \ 258 {\ 259 .funcs = &dummy_irq_info_funcs\ 260 } 261 262 #define i2c_int_entry(reg_num) \ 263 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 264 265 #define dp_sink_int_entry(reg_num) \ 266 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 267 268 #define gpio_pad_int_entry(reg_num) \ 269 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 270 271 #define dc_underflow_int_entry(reg_num) \ 272 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 273 274 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 275 .set = dal_irq_service_dummy_set, 276 .ack = dal_irq_service_dummy_ack 277 }; 278 279 static const struct irq_source_info 280 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = { 281 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 282 hpd_int_entry(0), 283 hpd_int_entry(1), 284 hpd_int_entry(2), 285 hpd_int_entry(3), 286 hpd_int_entry(4), 287 hpd_rx_int_entry(0), 288 hpd_rx_int_entry(1), 289 hpd_rx_int_entry(2), 290 hpd_rx_int_entry(3), 291 hpd_rx_int_entry(4), 292 i2c_int_entry(1), 293 i2c_int_entry(2), 294 i2c_int_entry(3), 295 i2c_int_entry(4), 296 i2c_int_entry(5), 297 i2c_int_entry(6), 298 dp_sink_int_entry(1), 299 dp_sink_int_entry(2), 300 dp_sink_int_entry(3), 301 dp_sink_int_entry(4), 302 dp_sink_int_entry(5), 303 dp_sink_int_entry(6), 304 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 305 pflip_int_entry(0), 306 pflip_int_entry(1), 307 pflip_int_entry(2), 308 pflip_int_entry(3), 309 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 310 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 311 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 312 gpio_pad_int_entry(0), 313 gpio_pad_int_entry(1), 314 gpio_pad_int_entry(2), 315 gpio_pad_int_entry(3), 316 gpio_pad_int_entry(4), 317 gpio_pad_int_entry(5), 318 gpio_pad_int_entry(6), 319 gpio_pad_int_entry(7), 320 gpio_pad_int_entry(8), 321 gpio_pad_int_entry(9), 322 gpio_pad_int_entry(10), 323 gpio_pad_int_entry(11), 324 gpio_pad_int_entry(12), 325 gpio_pad_int_entry(13), 326 gpio_pad_int_entry(14), 327 gpio_pad_int_entry(15), 328 gpio_pad_int_entry(16), 329 gpio_pad_int_entry(17), 330 gpio_pad_int_entry(18), 331 gpio_pad_int_entry(19), 332 gpio_pad_int_entry(20), 333 gpio_pad_int_entry(21), 334 gpio_pad_int_entry(22), 335 gpio_pad_int_entry(23), 336 gpio_pad_int_entry(24), 337 gpio_pad_int_entry(25), 338 gpio_pad_int_entry(26), 339 gpio_pad_int_entry(27), 340 gpio_pad_int_entry(28), 341 gpio_pad_int_entry(29), 342 gpio_pad_int_entry(30), 343 dc_underflow_int_entry(1), 344 dc_underflow_int_entry(2), 345 dc_underflow_int_entry(3), 346 dc_underflow_int_entry(4), 347 dc_underflow_int_entry(5), 348 dc_underflow_int_entry(6), 349 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 350 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 351 vupdate_int_entry(0), 352 vupdate_int_entry(1), 353 vupdate_int_entry(2), 354 vupdate_int_entry(3), 355 vupdate_int_entry(4), 356 vupdate_int_entry(5), 357 vupdate_no_lock_int_entry(0), 358 vupdate_no_lock_int_entry(1), 359 vupdate_no_lock_int_entry(2), 360 vupdate_no_lock_int_entry(3), 361 vupdate_no_lock_int_entry(4), 362 vupdate_no_lock_int_entry(5), 363 vblank_int_entry(0), 364 vblank_int_entry(1), 365 vblank_int_entry(2), 366 vblank_int_entry(3), 367 vblank_int_entry(4), 368 vblank_int_entry(5), 369 }; 370 371 static const struct irq_service_funcs irq_service_funcs_dcn21 = { 372 .to_dal_irq_source = to_dal_irq_source_dcn21 373 }; 374 375 static void dcn21_irq_construct( 376 struct irq_service *irq_service, 377 struct irq_service_init_data *init_data) 378 { 379 dal_irq_service_construct(irq_service, init_data); 380 381 irq_service->info = irq_source_info_dcn21; 382 irq_service->funcs = &irq_service_funcs_dcn21; 383 } 384 385 struct irq_service *dal_irq_service_dcn21_create( 386 struct irq_service_init_data *init_data) 387 { 388 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 389 GFP_KERNEL); 390 391 if (!irq_service) 392 return NULL; 393 394 dcn21_irq_construct(irq_service, init_data); 395 return irq_service; 396 } 397