1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "include/logger_interface.h" 29 30 #include "../dce110/irq_service_dce110.h" 31 #include "irq_service_dcn201.h" 32 33 #include "dcn/dcn_2_0_3_offset.h" 34 #include "dcn/dcn_2_0_3_sh_mask.h" 35 36 #include "cyan_skillfish_ip_offset.h" 37 #include "soc15_hw_ip.h" 38 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 39 40 static enum dc_irq_source to_dal_irq_source_dcn201( 41 struct irq_service *irq_service, 42 uint32_t src_id, 43 uint32_t ext_id) 44 { 45 switch (src_id) { 46 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 47 return DC_IRQ_SOURCE_VBLANK1; 48 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 49 return DC_IRQ_SOURCE_VBLANK2; 50 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: 51 return DC_IRQ_SOURCE_DC1_VLINE0; 52 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: 53 return DC_IRQ_SOURCE_DC2_VLINE0; 54 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 55 return DC_IRQ_SOURCE_PFLIP1; 56 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 57 return DC_IRQ_SOURCE_PFLIP2; 58 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 59 return DC_IRQ_SOURCE_VUPDATE1; 60 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 61 return DC_IRQ_SOURCE_VUPDATE2; 62 case DCN_1_0__SRCID__DC_HPD1_INT: 63 /* generic src_id for all HPD and HPDRX interrupts */ 64 switch (ext_id) { 65 case DCN_1_0__CTXID__DC_HPD1_INT: 66 return DC_IRQ_SOURCE_HPD1; 67 case DCN_1_0__CTXID__DC_HPD2_INT: 68 return DC_IRQ_SOURCE_HPD2; 69 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 70 return DC_IRQ_SOURCE_HPD1RX; 71 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 72 return DC_IRQ_SOURCE_HPD2RX; 73 default: 74 return DC_IRQ_SOURCE_INVALID; 75 } 76 break; 77 78 default: 79 return DC_IRQ_SOURCE_INVALID; 80 } 81 } 82 83 static bool hpd_ack( 84 struct irq_service *irq_service, 85 const struct irq_source_info *info) 86 { 87 uint32_t addr = info->status_reg; 88 uint32_t value = dm_read_reg(irq_service->ctx, addr); 89 uint32_t current_status = 90 get_reg_field_value( 91 value, 92 HPD0_DC_HPD_INT_STATUS, 93 DC_HPD_SENSE_DELAYED); 94 95 dal_irq_service_ack_generic(irq_service, info); 96 97 value = dm_read_reg(irq_service->ctx, info->enable_reg); 98 99 set_reg_field_value( 100 value, 101 current_status ? 0 : 1, 102 HPD0_DC_HPD_INT_CONTROL, 103 DC_HPD_INT_POLARITY); 104 105 dm_write_reg(irq_service->ctx, info->enable_reg, value); 106 107 return true; 108 } 109 110 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 111 .set = NULL, 112 .ack = hpd_ack 113 }; 114 115 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 116 .set = NULL, 117 .ack = NULL 118 }; 119 120 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 121 .set = NULL, 122 .ack = NULL 123 }; 124 125 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 126 .set = NULL, 127 .ack = NULL 128 }; 129 130 static const struct irq_source_info_funcs vline0_irq_info_funcs = { 131 .set = NULL, 132 .ack = NULL 133 }; 134 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 135 .set = NULL, 136 .ack = NULL 137 }; 138 139 #undef BASE_INNER 140 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 141 142 #define BASE(seg) BASE_INNER(seg) 143 144 /* compile time expand base address. */ 145 #define BASE(seg) \ 146 BASE_INNER(seg) 147 148 #define SRI(reg_name, block, id)\ 149 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 150 mm ## block ## id ## _ ## reg_name 151 152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 153 .enable_reg = SRI(reg1, block, reg_num),\ 154 .enable_mask = \ 155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 156 .enable_value = {\ 157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 159 },\ 160 .ack_reg = SRI(reg2, block, reg_num),\ 161 .ack_mask = \ 162 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 163 .ack_value = \ 164 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 165 166 #define hpd_int_entry(reg_num)\ 167 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 168 IRQ_REG_ENTRY(HPD, reg_num,\ 169 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 170 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 171 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 172 .funcs = &hpd_irq_info_funcs\ 173 } 174 175 #define hpd_rx_int_entry(reg_num)\ 176 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 177 IRQ_REG_ENTRY(HPD, reg_num,\ 178 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 179 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 180 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 181 .funcs = &hpd_rx_irq_info_funcs\ 182 } 183 #define pflip_int_entry(reg_num)\ 184 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 185 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 186 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 187 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 188 .funcs = &pflip_irq_info_funcs\ 189 } 190 191 #define vupdate_int_entry(reg_num)\ 192 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 193 IRQ_REG_ENTRY(OTG, reg_num,\ 194 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\ 195 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\ 196 .funcs = &vblank_irq_info_funcs\ 197 } 198 199 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 200 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 201 */ 202 #define vupdate_no_lock_int_entry(reg_num)\ 203 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 204 IRQ_REG_ENTRY(OTG, reg_num,\ 205 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 206 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 207 .funcs = &vupdate_no_lock_irq_info_funcs\ 208 } 209 #define vblank_int_entry(reg_num)\ 210 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 211 IRQ_REG_ENTRY(OTG, reg_num,\ 212 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 213 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 214 .funcs = &vblank_irq_info_funcs\ 215 } 216 217 #define vline0_int_entry(reg_num)\ 218 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ 219 IRQ_REG_ENTRY(OTG, reg_num,\ 220 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ 221 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ 222 .funcs = &vline0_irq_info_funcs\ 223 } 224 225 #define dummy_irq_entry() \ 226 {\ 227 .funcs = &dummy_irq_info_funcs\ 228 } 229 230 #define i2c_int_entry(reg_num) \ 231 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 232 233 #define dp_sink_int_entry(reg_num) \ 234 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 235 236 #define gpio_pad_int_entry(reg_num) \ 237 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 238 239 #define dc_underflow_int_entry(reg_num) \ 240 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 241 242 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 243 .set = dal_irq_service_dummy_set, 244 .ack = dal_irq_service_dummy_ack 245 }; 246 247 static const struct irq_source_info 248 irq_source_info_dcn201[DAL_IRQ_SOURCES_NUMBER] = { 249 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 250 hpd_int_entry(0), 251 hpd_int_entry(1), 252 dummy_irq_entry(), 253 dummy_irq_entry(), 254 dummy_irq_entry(), 255 dummy_irq_entry(), 256 hpd_rx_int_entry(0), 257 hpd_rx_int_entry(1), 258 dummy_irq_entry(), 259 dummy_irq_entry(), 260 dummy_irq_entry(), 261 dummy_irq_entry(), 262 i2c_int_entry(1), 263 i2c_int_entry(2), 264 dummy_irq_entry(), 265 dummy_irq_entry(), 266 dummy_irq_entry(), 267 dummy_irq_entry(), 268 dp_sink_int_entry(1), 269 dp_sink_int_entry(2), 270 dummy_irq_entry(), 271 dummy_irq_entry(), 272 dummy_irq_entry(), 273 dummy_irq_entry(), 274 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 275 pflip_int_entry(0), 276 pflip_int_entry(1), 277 pflip_int_entry(2), 278 pflip_int_entry(3), 279 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 280 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 281 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 282 gpio_pad_int_entry(0), 283 gpio_pad_int_entry(1), 284 gpio_pad_int_entry(2), 285 gpio_pad_int_entry(3), 286 gpio_pad_int_entry(4), 287 gpio_pad_int_entry(5), 288 gpio_pad_int_entry(6), 289 gpio_pad_int_entry(7), 290 gpio_pad_int_entry(8), 291 gpio_pad_int_entry(9), 292 gpio_pad_int_entry(10), 293 gpio_pad_int_entry(11), 294 gpio_pad_int_entry(12), 295 gpio_pad_int_entry(13), 296 gpio_pad_int_entry(14), 297 gpio_pad_int_entry(15), 298 gpio_pad_int_entry(16), 299 gpio_pad_int_entry(17), 300 gpio_pad_int_entry(18), 301 gpio_pad_int_entry(19), 302 gpio_pad_int_entry(20), 303 gpio_pad_int_entry(21), 304 gpio_pad_int_entry(22), 305 gpio_pad_int_entry(23), 306 gpio_pad_int_entry(24), 307 gpio_pad_int_entry(25), 308 gpio_pad_int_entry(26), 309 gpio_pad_int_entry(27), 310 gpio_pad_int_entry(28), 311 gpio_pad_int_entry(29), 312 gpio_pad_int_entry(30), 313 dc_underflow_int_entry(1), 314 dc_underflow_int_entry(2), 315 dummy_irq_entry(), 316 dummy_irq_entry(), 317 dummy_irq_entry(), 318 dummy_irq_entry(), 319 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 320 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 321 vupdate_no_lock_int_entry(0), 322 vupdate_no_lock_int_entry(1), 323 dummy_irq_entry(), 324 dummy_irq_entry(), 325 dummy_irq_entry(), 326 dummy_irq_entry(), 327 vblank_int_entry(0), 328 vblank_int_entry(1), 329 dummy_irq_entry(), 330 dummy_irq_entry(), 331 dummy_irq_entry(), 332 dummy_irq_entry(), 333 vline0_int_entry(0), 334 vline0_int_entry(1), 335 dummy_irq_entry(), 336 dummy_irq_entry(), 337 dummy_irq_entry(), 338 dummy_irq_entry(), 339 }; 340 341 static const struct irq_service_funcs irq_service_funcs_dcn201 = { 342 .to_dal_irq_source = to_dal_irq_source_dcn201 343 }; 344 345 static void dcn201_irq_construct( 346 struct irq_service *irq_service, 347 struct irq_service_init_data *init_data) 348 { 349 dal_irq_service_construct(irq_service, init_data); 350 351 irq_service->info = irq_source_info_dcn201; 352 irq_service->funcs = &irq_service_funcs_dcn201; 353 } 354 355 struct irq_service *dal_irq_service_dcn201_create( 356 struct irq_service_init_data *init_data) 357 { 358 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 359 GFP_KERNEL); 360 361 if (!irq_service) 362 return NULL; 363 364 dcn201_irq_construct(irq_service, init_data); 365 return irq_service; 366 } 367