1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "include/logger_interface.h" 31 32 #include "../dce110/irq_service_dce110.h" 33 34 #include "dcn/dcn_1_0_offset.h" 35 #include "dcn/dcn_1_0_sh_mask.h" 36 #include "soc15_hw_ip.h" 37 #include "vega10_ip_offset.h" 38 39 #include "irq_service_dcn10.h" 40 41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 42 43 static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_service, 44 uint32_t src_id, 45 uint32_t ext_id) 46 { 47 switch (src_id) { 48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 49 return DC_IRQ_SOURCE_VBLANK1; 50 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 51 return DC_IRQ_SOURCE_VBLANK2; 52 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 53 return DC_IRQ_SOURCE_VBLANK3; 54 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 55 return DC_IRQ_SOURCE_VBLANK4; 56 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 57 return DC_IRQ_SOURCE_VBLANK5; 58 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 59 return DC_IRQ_SOURCE_VBLANK6; 60 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: 61 return DC_IRQ_SOURCE_DC1_VLINE0; 62 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: 63 return DC_IRQ_SOURCE_DC2_VLINE0; 64 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: 65 return DC_IRQ_SOURCE_DC3_VLINE0; 66 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: 67 return DC_IRQ_SOURCE_DC4_VLINE0; 68 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: 69 return DC_IRQ_SOURCE_DC5_VLINE0; 70 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: 71 return DC_IRQ_SOURCE_DC6_VLINE0; 72 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 73 return DC_IRQ_SOURCE_VUPDATE1; 74 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 75 return DC_IRQ_SOURCE_VUPDATE2; 76 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 77 return DC_IRQ_SOURCE_VUPDATE3; 78 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 79 return DC_IRQ_SOURCE_VUPDATE4; 80 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 81 return DC_IRQ_SOURCE_VUPDATE5; 82 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 83 return DC_IRQ_SOURCE_VUPDATE6; 84 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 85 return DC_IRQ_SOURCE_PFLIP1; 86 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 87 return DC_IRQ_SOURCE_PFLIP2; 88 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 89 return DC_IRQ_SOURCE_PFLIP3; 90 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 91 return DC_IRQ_SOURCE_PFLIP4; 92 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 93 return DC_IRQ_SOURCE_PFLIP5; 94 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 95 return DC_IRQ_SOURCE_PFLIP6; 96 97 case DCN_1_0__SRCID__DC_HPD1_INT: 98 /* generic src_id for all HPD and HPDRX interrupts */ 99 switch (ext_id) { 100 case DCN_1_0__CTXID__DC_HPD1_INT: 101 return DC_IRQ_SOURCE_HPD1; 102 case DCN_1_0__CTXID__DC_HPD2_INT: 103 return DC_IRQ_SOURCE_HPD2; 104 case DCN_1_0__CTXID__DC_HPD3_INT: 105 return DC_IRQ_SOURCE_HPD3; 106 case DCN_1_0__CTXID__DC_HPD4_INT: 107 return DC_IRQ_SOURCE_HPD4; 108 case DCN_1_0__CTXID__DC_HPD5_INT: 109 return DC_IRQ_SOURCE_HPD5; 110 case DCN_1_0__CTXID__DC_HPD6_INT: 111 return DC_IRQ_SOURCE_HPD6; 112 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 113 return DC_IRQ_SOURCE_HPD1RX; 114 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 115 return DC_IRQ_SOURCE_HPD2RX; 116 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 117 return DC_IRQ_SOURCE_HPD3RX; 118 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 119 return DC_IRQ_SOURCE_HPD4RX; 120 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 121 return DC_IRQ_SOURCE_HPD5RX; 122 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 123 return DC_IRQ_SOURCE_HPD6RX; 124 default: 125 return DC_IRQ_SOURCE_INVALID; 126 } 127 break; 128 129 default: 130 return DC_IRQ_SOURCE_INVALID; 131 } 132 } 133 134 static bool hpd_ack( 135 struct irq_service *irq_service, 136 const struct irq_source_info *info) 137 { 138 uint32_t addr = info->status_reg; 139 uint32_t value = dm_read_reg(irq_service->ctx, addr); 140 uint32_t current_status = 141 get_reg_field_value( 142 value, 143 HPD0_DC_HPD_INT_STATUS, 144 DC_HPD_SENSE_DELAYED); 145 146 dal_irq_service_ack_generic(irq_service, info); 147 148 value = dm_read_reg(irq_service->ctx, info->enable_reg); 149 150 set_reg_field_value( 151 value, 152 current_status ? 0 : 1, 153 HPD0_DC_HPD_INT_CONTROL, 154 DC_HPD_INT_POLARITY); 155 156 dm_write_reg(irq_service->ctx, info->enable_reg, value); 157 158 return true; 159 } 160 161 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 162 .set = NULL, 163 .ack = hpd_ack 164 }; 165 166 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 167 .set = NULL, 168 .ack = NULL 169 }; 170 171 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 172 .set = NULL, 173 .ack = NULL 174 }; 175 176 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 177 .set = NULL, 178 .ack = NULL 179 }; 180 181 static const struct irq_source_info_funcs vline0_irq_info_funcs = { 182 .set = NULL, 183 .ack = NULL 184 }; 185 186 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 187 .set = NULL, 188 .ack = NULL 189 }; 190 191 #define BASE_INNER(seg) \ 192 DCE_BASE__INST0_SEG ## seg 193 194 #define BASE(seg) \ 195 BASE_INNER(seg) 196 197 #define SRI(reg_name, block, id)\ 198 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 199 mm ## block ## id ## _ ## reg_name 200 201 202 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 203 .enable_reg = SRI(reg1, block, reg_num),\ 204 .enable_mask = \ 205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 206 .enable_value = {\ 207 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 208 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 209 },\ 210 .ack_reg = SRI(reg2, block, reg_num),\ 211 .ack_mask = \ 212 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 213 .ack_value = \ 214 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 215 216 #define hpd_int_entry(reg_num)\ 217 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 218 IRQ_REG_ENTRY(HPD, reg_num,\ 219 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 220 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 221 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 222 .funcs = &hpd_irq_info_funcs\ 223 } 224 225 #define hpd_rx_int_entry(reg_num)\ 226 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 227 IRQ_REG_ENTRY(HPD, reg_num,\ 228 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 229 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 230 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 231 .funcs = &hpd_rx_irq_info_funcs\ 232 } 233 #define pflip_int_entry(reg_num)\ 234 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 235 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 236 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 237 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 238 .funcs = &pflip_irq_info_funcs\ 239 } 240 241 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 242 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 243 */ 244 #define vupdate_no_lock_int_entry(reg_num)\ 245 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 246 IRQ_REG_ENTRY(OTG, reg_num,\ 247 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 248 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 249 .funcs = &vupdate_no_lock_irq_info_funcs\ 250 } 251 252 #define vblank_int_entry(reg_num)\ 253 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 254 IRQ_REG_ENTRY(OTG, reg_num,\ 255 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 256 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 257 .funcs = &vblank_irq_info_funcs\ 258 } 259 260 #define vline0_int_entry(reg_num)\ 261 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ 262 IRQ_REG_ENTRY(OTG, reg_num,\ 263 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ 264 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ 265 .funcs = &vline0_irq_info_funcs\ 266 } 267 268 #define dummy_irq_entry() \ 269 {\ 270 .funcs = &dummy_irq_info_funcs\ 271 } 272 273 #define i2c_int_entry(reg_num) \ 274 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 275 276 #define dp_sink_int_entry(reg_num) \ 277 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 278 279 #define gpio_pad_int_entry(reg_num) \ 280 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 281 282 #define dc_underflow_int_entry(reg_num) \ 283 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 284 285 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 286 .set = dal_irq_service_dummy_set, 287 .ack = dal_irq_service_dummy_ack 288 }; 289 290 static const struct irq_source_info 291 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = { 292 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 293 hpd_int_entry(0), 294 hpd_int_entry(1), 295 hpd_int_entry(2), 296 hpd_int_entry(3), 297 hpd_int_entry(4), 298 hpd_int_entry(5), 299 hpd_rx_int_entry(0), 300 hpd_rx_int_entry(1), 301 hpd_rx_int_entry(2), 302 hpd_rx_int_entry(3), 303 hpd_rx_int_entry(4), 304 hpd_rx_int_entry(5), 305 i2c_int_entry(1), 306 i2c_int_entry(2), 307 i2c_int_entry(3), 308 i2c_int_entry(4), 309 i2c_int_entry(5), 310 i2c_int_entry(6), 311 dp_sink_int_entry(1), 312 dp_sink_int_entry(2), 313 dp_sink_int_entry(3), 314 dp_sink_int_entry(4), 315 dp_sink_int_entry(5), 316 dp_sink_int_entry(6), 317 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 318 pflip_int_entry(0), 319 pflip_int_entry(1), 320 pflip_int_entry(2), 321 pflip_int_entry(3), 322 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 323 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 324 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 325 gpio_pad_int_entry(0), 326 gpio_pad_int_entry(1), 327 gpio_pad_int_entry(2), 328 gpio_pad_int_entry(3), 329 gpio_pad_int_entry(4), 330 gpio_pad_int_entry(5), 331 gpio_pad_int_entry(6), 332 gpio_pad_int_entry(7), 333 gpio_pad_int_entry(8), 334 gpio_pad_int_entry(9), 335 gpio_pad_int_entry(10), 336 gpio_pad_int_entry(11), 337 gpio_pad_int_entry(12), 338 gpio_pad_int_entry(13), 339 gpio_pad_int_entry(14), 340 gpio_pad_int_entry(15), 341 gpio_pad_int_entry(16), 342 gpio_pad_int_entry(17), 343 gpio_pad_int_entry(18), 344 gpio_pad_int_entry(19), 345 gpio_pad_int_entry(20), 346 gpio_pad_int_entry(21), 347 gpio_pad_int_entry(22), 348 gpio_pad_int_entry(23), 349 gpio_pad_int_entry(24), 350 gpio_pad_int_entry(25), 351 gpio_pad_int_entry(26), 352 gpio_pad_int_entry(27), 353 gpio_pad_int_entry(28), 354 gpio_pad_int_entry(29), 355 gpio_pad_int_entry(30), 356 dc_underflow_int_entry(1), 357 dc_underflow_int_entry(2), 358 dc_underflow_int_entry(3), 359 dc_underflow_int_entry(4), 360 dc_underflow_int_entry(5), 361 dc_underflow_int_entry(6), 362 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 363 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 364 vupdate_no_lock_int_entry(0), 365 vupdate_no_lock_int_entry(1), 366 vupdate_no_lock_int_entry(2), 367 vupdate_no_lock_int_entry(3), 368 vupdate_no_lock_int_entry(4), 369 vupdate_no_lock_int_entry(5), 370 vblank_int_entry(0), 371 vblank_int_entry(1), 372 vblank_int_entry(2), 373 vblank_int_entry(3), 374 vblank_int_entry(4), 375 vblank_int_entry(5), 376 vline0_int_entry(0), 377 vline0_int_entry(1), 378 vline0_int_entry(2), 379 vline0_int_entry(3), 380 vline0_int_entry(4), 381 vline0_int_entry(5), 382 }; 383 384 static const struct irq_service_funcs irq_service_funcs_dcn10 = { 385 .to_dal_irq_source = to_dal_irq_source_dcn10 386 }; 387 388 static void dcn10_irq_construct( 389 struct irq_service *irq_service, 390 struct irq_service_init_data *init_data) 391 { 392 dal_irq_service_construct(irq_service, init_data); 393 394 irq_service->info = irq_source_info_dcn10; 395 irq_service->funcs = &irq_service_funcs_dcn10; 396 } 397 398 struct irq_service *dal_irq_service_dcn10_create( 399 struct irq_service_init_data *init_data) 400 { 401 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 402 GFP_KERNEL); 403 404 if (!irq_service) 405 return NULL; 406 407 dcn10_irq_construct(irq_service, init_data); 408 return irq_service; 409 } 410