1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "include/logger_interface.h" 29 30 #include "../dce110/irq_service_dce110.h" 31 32 #include "dcn/dcn_1_0_offset.h" 33 #include "dcn/dcn_1_0_sh_mask.h" 34 #include "soc15_hw_ip.h" 35 #include "vega10_ip_offset.h" 36 37 #include "irq_service_dcn10.h" 38 39 #include "ivsrcid/irqsrcs_dcn_1_0.h" 40 41 enum dc_irq_source to_dal_irq_source_dcn10( 42 struct irq_service *irq_service, 43 uint32_t src_id, 44 uint32_t ext_id) 45 { 46 switch (src_id) { 47 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 48 return DC_IRQ_SOURCE_VBLANK1; 49 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 50 return DC_IRQ_SOURCE_VBLANK2; 51 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 52 return DC_IRQ_SOURCE_VBLANK3; 53 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 54 return DC_IRQ_SOURCE_VBLANK4; 55 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 56 return DC_IRQ_SOURCE_VBLANK5; 57 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 58 return DC_IRQ_SOURCE_VBLANK6; 59 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 60 return DC_IRQ_SOURCE_VUPDATE1; 61 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 62 return DC_IRQ_SOURCE_VUPDATE2; 63 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 64 return DC_IRQ_SOURCE_VUPDATE3; 65 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 66 return DC_IRQ_SOURCE_VUPDATE4; 67 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 68 return DC_IRQ_SOURCE_VUPDATE5; 69 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 70 return DC_IRQ_SOURCE_VUPDATE6; 71 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 72 return DC_IRQ_SOURCE_PFLIP1; 73 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 74 return DC_IRQ_SOURCE_PFLIP2; 75 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 76 return DC_IRQ_SOURCE_PFLIP3; 77 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 78 return DC_IRQ_SOURCE_PFLIP4; 79 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 80 return DC_IRQ_SOURCE_PFLIP5; 81 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 82 return DC_IRQ_SOURCE_PFLIP6; 83 84 case DCN_1_0__SRCID__DC_HPD1_INT: 85 /* generic src_id for all HPD and HPDRX interrupts */ 86 switch (ext_id) { 87 case DCN_1_0__CTXID__DC_HPD1_INT: 88 return DC_IRQ_SOURCE_HPD1; 89 case DCN_1_0__CTXID__DC_HPD2_INT: 90 return DC_IRQ_SOURCE_HPD2; 91 case DCN_1_0__CTXID__DC_HPD3_INT: 92 return DC_IRQ_SOURCE_HPD3; 93 case DCN_1_0__CTXID__DC_HPD4_INT: 94 return DC_IRQ_SOURCE_HPD4; 95 case DCN_1_0__CTXID__DC_HPD5_INT: 96 return DC_IRQ_SOURCE_HPD5; 97 case DCN_1_0__CTXID__DC_HPD6_INT: 98 return DC_IRQ_SOURCE_HPD6; 99 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 100 return DC_IRQ_SOURCE_HPD1RX; 101 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 102 return DC_IRQ_SOURCE_HPD2RX; 103 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 104 return DC_IRQ_SOURCE_HPD3RX; 105 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 106 return DC_IRQ_SOURCE_HPD4RX; 107 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 108 return DC_IRQ_SOURCE_HPD5RX; 109 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 110 return DC_IRQ_SOURCE_HPD6RX; 111 default: 112 return DC_IRQ_SOURCE_INVALID; 113 } 114 break; 115 116 default: 117 return DC_IRQ_SOURCE_INVALID; 118 } 119 } 120 121 static bool hpd_ack( 122 struct irq_service *irq_service, 123 const struct irq_source_info *info) 124 { 125 uint32_t addr = info->status_reg; 126 uint32_t value = dm_read_reg(irq_service->ctx, addr); 127 uint32_t current_status = 128 get_reg_field_value( 129 value, 130 HPD0_DC_HPD_INT_STATUS, 131 DC_HPD_SENSE_DELAYED); 132 133 dal_irq_service_ack_generic(irq_service, info); 134 135 value = dm_read_reg(irq_service->ctx, info->enable_reg); 136 137 set_reg_field_value( 138 value, 139 current_status ? 0 : 1, 140 HPD0_DC_HPD_INT_CONTROL, 141 DC_HPD_INT_POLARITY); 142 143 dm_write_reg(irq_service->ctx, info->enable_reg, value); 144 145 return true; 146 } 147 148 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 149 .set = NULL, 150 .ack = hpd_ack 151 }; 152 153 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 154 .set = NULL, 155 .ack = NULL 156 }; 157 158 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 159 .set = NULL, 160 .ack = NULL 161 }; 162 163 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 164 .set = NULL, 165 .ack = NULL 166 }; 167 168 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 169 .set = NULL, 170 .ack = NULL 171 }; 172 173 #define BASE_INNER(seg) \ 174 DCE_BASE__INST0_SEG ## seg 175 176 #define BASE(seg) \ 177 BASE_INNER(seg) 178 179 #define SRI(reg_name, block, id)\ 180 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 mm ## block ## id ## _ ## reg_name 182 183 184 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 185 .enable_reg = SRI(reg1, block, reg_num),\ 186 .enable_mask = \ 187 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 188 .enable_value = {\ 189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 190 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 191 },\ 192 .ack_reg = SRI(reg2, block, reg_num),\ 193 .ack_mask = \ 194 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 195 .ack_value = \ 196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 197 198 #define hpd_int_entry(reg_num)\ 199 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 200 IRQ_REG_ENTRY(HPD, reg_num,\ 201 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 202 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 203 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 204 .funcs = &hpd_irq_info_funcs\ 205 } 206 207 #define hpd_rx_int_entry(reg_num)\ 208 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 209 IRQ_REG_ENTRY(HPD, reg_num,\ 210 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 211 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 212 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 213 .funcs = &hpd_rx_irq_info_funcs\ 214 } 215 #define pflip_int_entry(reg_num)\ 216 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 217 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 218 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 219 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 220 .funcs = &pflip_irq_info_funcs\ 221 } 222 223 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 224 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 225 */ 226 #define vupdate_no_lock_int_entry(reg_num)\ 227 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 228 IRQ_REG_ENTRY(OTG, reg_num,\ 229 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 230 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 231 .funcs = &vupdate_no_lock_irq_info_funcs\ 232 } 233 234 #define vblank_int_entry(reg_num)\ 235 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 236 IRQ_REG_ENTRY(OTG, reg_num,\ 237 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 238 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 239 .funcs = &vblank_irq_info_funcs\ 240 } 241 242 #define dummy_irq_entry() \ 243 {\ 244 .funcs = &dummy_irq_info_funcs\ 245 } 246 247 #define i2c_int_entry(reg_num) \ 248 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 249 250 #define dp_sink_int_entry(reg_num) \ 251 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 252 253 #define gpio_pad_int_entry(reg_num) \ 254 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 255 256 #define dc_underflow_int_entry(reg_num) \ 257 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 258 259 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 260 .set = dal_irq_service_dummy_set, 261 .ack = dal_irq_service_dummy_ack 262 }; 263 264 static const struct irq_source_info 265 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = { 266 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 267 hpd_int_entry(0), 268 hpd_int_entry(1), 269 hpd_int_entry(2), 270 hpd_int_entry(3), 271 hpd_int_entry(4), 272 hpd_int_entry(5), 273 hpd_rx_int_entry(0), 274 hpd_rx_int_entry(1), 275 hpd_rx_int_entry(2), 276 hpd_rx_int_entry(3), 277 hpd_rx_int_entry(4), 278 hpd_rx_int_entry(5), 279 i2c_int_entry(1), 280 i2c_int_entry(2), 281 i2c_int_entry(3), 282 i2c_int_entry(4), 283 i2c_int_entry(5), 284 i2c_int_entry(6), 285 dp_sink_int_entry(1), 286 dp_sink_int_entry(2), 287 dp_sink_int_entry(3), 288 dp_sink_int_entry(4), 289 dp_sink_int_entry(5), 290 dp_sink_int_entry(6), 291 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 292 pflip_int_entry(0), 293 pflip_int_entry(1), 294 pflip_int_entry(2), 295 pflip_int_entry(3), 296 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 297 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 298 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 299 gpio_pad_int_entry(0), 300 gpio_pad_int_entry(1), 301 gpio_pad_int_entry(2), 302 gpio_pad_int_entry(3), 303 gpio_pad_int_entry(4), 304 gpio_pad_int_entry(5), 305 gpio_pad_int_entry(6), 306 gpio_pad_int_entry(7), 307 gpio_pad_int_entry(8), 308 gpio_pad_int_entry(9), 309 gpio_pad_int_entry(10), 310 gpio_pad_int_entry(11), 311 gpio_pad_int_entry(12), 312 gpio_pad_int_entry(13), 313 gpio_pad_int_entry(14), 314 gpio_pad_int_entry(15), 315 gpio_pad_int_entry(16), 316 gpio_pad_int_entry(17), 317 gpio_pad_int_entry(18), 318 gpio_pad_int_entry(19), 319 gpio_pad_int_entry(20), 320 gpio_pad_int_entry(21), 321 gpio_pad_int_entry(22), 322 gpio_pad_int_entry(23), 323 gpio_pad_int_entry(24), 324 gpio_pad_int_entry(25), 325 gpio_pad_int_entry(26), 326 gpio_pad_int_entry(27), 327 gpio_pad_int_entry(28), 328 gpio_pad_int_entry(29), 329 gpio_pad_int_entry(30), 330 dc_underflow_int_entry(1), 331 dc_underflow_int_entry(2), 332 dc_underflow_int_entry(3), 333 dc_underflow_int_entry(4), 334 dc_underflow_int_entry(5), 335 dc_underflow_int_entry(6), 336 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 337 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 338 vupdate_no_lock_int_entry(0), 339 vupdate_no_lock_int_entry(1), 340 vupdate_no_lock_int_entry(2), 341 vupdate_no_lock_int_entry(3), 342 vupdate_no_lock_int_entry(4), 343 vupdate_no_lock_int_entry(5), 344 vblank_int_entry(0), 345 vblank_int_entry(1), 346 vblank_int_entry(2), 347 vblank_int_entry(3), 348 vblank_int_entry(4), 349 vblank_int_entry(5), 350 }; 351 352 static const struct irq_service_funcs irq_service_funcs_dcn10 = { 353 .to_dal_irq_source = to_dal_irq_source_dcn10 354 }; 355 356 static void construct( 357 struct irq_service *irq_service, 358 struct irq_service_init_data *init_data) 359 { 360 dal_irq_service_construct(irq_service, init_data); 361 362 irq_service->info = irq_source_info_dcn10; 363 irq_service->funcs = &irq_service_funcs_dcn10; 364 } 365 366 struct irq_service *dal_irq_service_dcn10_create( 367 struct irq_service_init_data *init_data) 368 { 369 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 370 GFP_KERNEL); 371 372 if (!irq_service) 373 return NULL; 374 375 construct(irq_service, init_data); 376 return irq_service; 377 } 378