14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #include "dm_services.h" 274562236bSHarry Wentland 284562236bSHarry Wentland #include "include/logger_interface.h" 294562236bSHarry Wentland 304562236bSHarry Wentland #include "irq_service_dce80.h" 314562236bSHarry Wentland #include "../dce110/irq_service_dce110.h" 324562236bSHarry Wentland 334562236bSHarry Wentland #include "dce/dce_8_0_d.h" 344562236bSHarry Wentland #include "dce/dce_8_0_sh_mask.h" 354562236bSHarry Wentland 364562236bSHarry Wentland #include "ivsrcid/ivsrcid_vislands30.h" 374562236bSHarry Wentland 384562236bSHarry Wentland static bool hpd_ack( 394562236bSHarry Wentland struct irq_service *irq_service, 404562236bSHarry Wentland const struct irq_source_info *info) 414562236bSHarry Wentland { 424562236bSHarry Wentland uint32_t addr = info->status_reg; 434562236bSHarry Wentland uint32_t value = dm_read_reg(irq_service->ctx, addr); 444562236bSHarry Wentland uint32_t current_status = 454562236bSHarry Wentland get_reg_field_value( 464562236bSHarry Wentland value, 474562236bSHarry Wentland DC_HPD1_INT_STATUS, 484562236bSHarry Wentland DC_HPD1_SENSE_DELAYED); 494562236bSHarry Wentland 504562236bSHarry Wentland dal_irq_service_ack_generic(irq_service, info); 514562236bSHarry Wentland 524562236bSHarry Wentland value = dm_read_reg(irq_service->ctx, info->enable_reg); 534562236bSHarry Wentland 544562236bSHarry Wentland set_reg_field_value( 554562236bSHarry Wentland value, 564562236bSHarry Wentland current_status ? 0 : 1, 574562236bSHarry Wentland DC_HPD1_INT_CONTROL, 584562236bSHarry Wentland DC_HPD1_INT_POLARITY); 594562236bSHarry Wentland 604562236bSHarry Wentland dm_write_reg(irq_service->ctx, info->enable_reg, value); 614562236bSHarry Wentland 624562236bSHarry Wentland return true; 634562236bSHarry Wentland } 644562236bSHarry Wentland 654562236bSHarry Wentland static const struct irq_source_info_funcs hpd_irq_info_funcs = { 664562236bSHarry Wentland .set = NULL, 674562236bSHarry Wentland .ack = hpd_ack 684562236bSHarry Wentland }; 694562236bSHarry Wentland 704562236bSHarry Wentland static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 714562236bSHarry Wentland .set = NULL, 724562236bSHarry Wentland .ack = NULL 734562236bSHarry Wentland }; 744562236bSHarry Wentland 754562236bSHarry Wentland static const struct irq_source_info_funcs pflip_irq_info_funcs = { 764562236bSHarry Wentland .set = NULL, 774562236bSHarry Wentland .ack = NULL 784562236bSHarry Wentland }; 794562236bSHarry Wentland 804562236bSHarry Wentland static const struct irq_source_info_funcs vblank_irq_info_funcs = { 814562236bSHarry Wentland .set = NULL, 824562236bSHarry Wentland .ack = NULL 834562236bSHarry Wentland }; 844562236bSHarry Wentland 854562236bSHarry Wentland 864562236bSHarry Wentland #define hpd_int_entry(reg_num)\ 874562236bSHarry Wentland [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 884562236bSHarry Wentland .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 894562236bSHarry Wentland .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\ 904562236bSHarry Wentland .enable_value = {\ 914562236bSHarry Wentland DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\ 924562236bSHarry Wentland ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\ 934562236bSHarry Wentland },\ 944562236bSHarry Wentland .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 954562236bSHarry Wentland .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\ 964562236bSHarry Wentland .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\ 974562236bSHarry Wentland .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 984562236bSHarry Wentland .funcs = &hpd_irq_info_funcs\ 994562236bSHarry Wentland } 1004562236bSHarry Wentland 1014562236bSHarry Wentland #define hpd_rx_int_entry(reg_num)\ 1024562236bSHarry Wentland [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 1034562236bSHarry Wentland .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 1044562236bSHarry Wentland .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\ 1054562236bSHarry Wentland .enable_value = {\ 1064562236bSHarry Wentland DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\ 1074562236bSHarry Wentland ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\ 1084562236bSHarry Wentland .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 1094562236bSHarry Wentland .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\ 1104562236bSHarry Wentland .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\ 1114562236bSHarry Wentland .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 1124562236bSHarry Wentland .funcs = &hpd_rx_irq_info_funcs\ 1134562236bSHarry Wentland } 1144562236bSHarry Wentland 1154562236bSHarry Wentland #define pflip_int_entry(reg_num)\ 1164562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 1174562236bSHarry Wentland .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ 1184562236bSHarry Wentland .enable_mask =\ 1194562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 1204562236bSHarry Wentland .enable_value = {\ 1214562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 1224562236bSHarry Wentland ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\ 1234562236bSHarry Wentland .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\ 1244562236bSHarry Wentland .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 1254562236bSHarry Wentland .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 1264562236bSHarry Wentland .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\ 1274562236bSHarry Wentland .funcs = &pflip_irq_info_funcs\ 1284562236bSHarry Wentland } 1294562236bSHarry Wentland 1304562236bSHarry Wentland #define vupdate_int_entry(reg_num)\ 1314562236bSHarry Wentland [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 1324562236bSHarry Wentland .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ 1334562236bSHarry Wentland .enable_mask =\ 1344562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 1354562236bSHarry Wentland .enable_value = {\ 1364562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 1374562236bSHarry Wentland ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\ 1384562236bSHarry Wentland .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\ 1394562236bSHarry Wentland .ack_mask =\ 1404562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 1414562236bSHarry Wentland .ack_value =\ 1424562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 1434562236bSHarry Wentland .funcs = &vblank_irq_info_funcs\ 1444562236bSHarry Wentland } 1454562236bSHarry Wentland 1464562236bSHarry Wentland #define dummy_irq_entry() \ 1474562236bSHarry Wentland {\ 1484562236bSHarry Wentland .funcs = &dummy_irq_info_funcs\ 1494562236bSHarry Wentland } 1504562236bSHarry Wentland 1514562236bSHarry Wentland #define i2c_int_entry(reg_num) \ 1524562236bSHarry Wentland [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 1534562236bSHarry Wentland 1544562236bSHarry Wentland #define dp_sink_int_entry(reg_num) \ 1554562236bSHarry Wentland [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 1564562236bSHarry Wentland 1574562236bSHarry Wentland #define gpio_pad_int_entry(reg_num) \ 1584562236bSHarry Wentland [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 1594562236bSHarry Wentland 1604562236bSHarry Wentland #define dc_underflow_int_entry(reg_num) \ 1614562236bSHarry Wentland [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 1624562236bSHarry Wentland 1634562236bSHarry Wentland 1644562236bSHarry Wentland static const struct irq_source_info_funcs dummy_irq_info_funcs = { 1654562236bSHarry Wentland .set = dal_irq_service_dummy_set, 1664562236bSHarry Wentland .ack = dal_irq_service_dummy_ack 1674562236bSHarry Wentland }; 1684562236bSHarry Wentland 1694562236bSHarry Wentland static const struct irq_source_info 1704562236bSHarry Wentland irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = { 1714562236bSHarry Wentland [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 1724562236bSHarry Wentland hpd_int_entry(1), 1734562236bSHarry Wentland hpd_int_entry(2), 1744562236bSHarry Wentland hpd_int_entry(3), 1754562236bSHarry Wentland hpd_int_entry(4), 1764562236bSHarry Wentland hpd_int_entry(5), 1774562236bSHarry Wentland hpd_int_entry(6), 1784562236bSHarry Wentland hpd_rx_int_entry(1), 1794562236bSHarry Wentland hpd_rx_int_entry(2), 1804562236bSHarry Wentland hpd_rx_int_entry(3), 1814562236bSHarry Wentland hpd_rx_int_entry(4), 1824562236bSHarry Wentland hpd_rx_int_entry(5), 1834562236bSHarry Wentland hpd_rx_int_entry(6), 1844562236bSHarry Wentland i2c_int_entry(1), 1854562236bSHarry Wentland i2c_int_entry(2), 1864562236bSHarry Wentland i2c_int_entry(3), 1874562236bSHarry Wentland i2c_int_entry(4), 1884562236bSHarry Wentland i2c_int_entry(5), 1894562236bSHarry Wentland i2c_int_entry(6), 1904562236bSHarry Wentland dp_sink_int_entry(1), 1914562236bSHarry Wentland dp_sink_int_entry(2), 1924562236bSHarry Wentland dp_sink_int_entry(3), 1934562236bSHarry Wentland dp_sink_int_entry(4), 1944562236bSHarry Wentland dp_sink_int_entry(5), 1954562236bSHarry Wentland dp_sink_int_entry(6), 1964562236bSHarry Wentland [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 1974562236bSHarry Wentland pflip_int_entry(0), 1984562236bSHarry Wentland pflip_int_entry(1), 1994562236bSHarry Wentland pflip_int_entry(2), 2004562236bSHarry Wentland pflip_int_entry(3), 2014562236bSHarry Wentland pflip_int_entry(4), 2024562236bSHarry Wentland pflip_int_entry(5), 2034562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 2044562236bSHarry Wentland gpio_pad_int_entry(0), 2054562236bSHarry Wentland gpio_pad_int_entry(1), 2064562236bSHarry Wentland gpio_pad_int_entry(2), 2074562236bSHarry Wentland gpio_pad_int_entry(3), 2084562236bSHarry Wentland gpio_pad_int_entry(4), 2094562236bSHarry Wentland gpio_pad_int_entry(5), 2104562236bSHarry Wentland gpio_pad_int_entry(6), 2114562236bSHarry Wentland gpio_pad_int_entry(7), 2124562236bSHarry Wentland gpio_pad_int_entry(8), 2134562236bSHarry Wentland gpio_pad_int_entry(9), 2144562236bSHarry Wentland gpio_pad_int_entry(10), 2154562236bSHarry Wentland gpio_pad_int_entry(11), 2164562236bSHarry Wentland gpio_pad_int_entry(12), 2174562236bSHarry Wentland gpio_pad_int_entry(13), 2184562236bSHarry Wentland gpio_pad_int_entry(14), 2194562236bSHarry Wentland gpio_pad_int_entry(15), 2204562236bSHarry Wentland gpio_pad_int_entry(16), 2214562236bSHarry Wentland gpio_pad_int_entry(17), 2224562236bSHarry Wentland gpio_pad_int_entry(18), 2234562236bSHarry Wentland gpio_pad_int_entry(19), 2244562236bSHarry Wentland gpio_pad_int_entry(20), 2254562236bSHarry Wentland gpio_pad_int_entry(21), 2264562236bSHarry Wentland gpio_pad_int_entry(22), 2274562236bSHarry Wentland gpio_pad_int_entry(23), 2284562236bSHarry Wentland gpio_pad_int_entry(24), 2294562236bSHarry Wentland gpio_pad_int_entry(25), 2304562236bSHarry Wentland gpio_pad_int_entry(26), 2314562236bSHarry Wentland gpio_pad_int_entry(27), 2324562236bSHarry Wentland gpio_pad_int_entry(28), 2334562236bSHarry Wentland gpio_pad_int_entry(29), 2344562236bSHarry Wentland gpio_pad_int_entry(30), 2354562236bSHarry Wentland dc_underflow_int_entry(1), 2364562236bSHarry Wentland dc_underflow_int_entry(2), 2374562236bSHarry Wentland dc_underflow_int_entry(3), 2384562236bSHarry Wentland dc_underflow_int_entry(4), 2394562236bSHarry Wentland dc_underflow_int_entry(5), 2404562236bSHarry Wentland dc_underflow_int_entry(6), 2414562236bSHarry Wentland [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 2424562236bSHarry Wentland [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 2434562236bSHarry Wentland vupdate_int_entry(0), 2444562236bSHarry Wentland vupdate_int_entry(1), 2454562236bSHarry Wentland vupdate_int_entry(2), 2464562236bSHarry Wentland vupdate_int_entry(3), 2474562236bSHarry Wentland vupdate_int_entry(4), 2484562236bSHarry Wentland vupdate_int_entry(5), 2494562236bSHarry Wentland }; 2504562236bSHarry Wentland 2514562236bSHarry Wentland static const struct irq_service_funcs irq_service_funcs_dce80 = { 2524562236bSHarry Wentland .to_dal_irq_source = to_dal_irq_source_dce110 2534562236bSHarry Wentland }; 2544562236bSHarry Wentland 2554562236bSHarry Wentland static bool construct( 2564562236bSHarry Wentland struct irq_service *irq_service, 2574562236bSHarry Wentland struct irq_service_init_data *init_data) 2584562236bSHarry Wentland { 2594562236bSHarry Wentland if (!dal_irq_service_construct(irq_service, init_data)) 2604562236bSHarry Wentland return false; 2614562236bSHarry Wentland 2624562236bSHarry Wentland irq_service->info = irq_source_info_dce80; 2634562236bSHarry Wentland irq_service->funcs = &irq_service_funcs_dce80; 2644562236bSHarry Wentland 2654562236bSHarry Wentland return true; 2664562236bSHarry Wentland } 2674562236bSHarry Wentland 2684562236bSHarry Wentland struct irq_service *dal_irq_service_dce80_create( 2694562236bSHarry Wentland struct irq_service_init_data *init_data) 2704562236bSHarry Wentland { 2714562236bSHarry Wentland struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); 2724562236bSHarry Wentland 2734562236bSHarry Wentland if (!irq_service) 2744562236bSHarry Wentland return NULL; 2754562236bSHarry Wentland 2764562236bSHarry Wentland if (construct(irq_service, init_data)) 2774562236bSHarry Wentland return irq_service; 2784562236bSHarry Wentland 2794562236bSHarry Wentland dm_free(irq_service); 2804562236bSHarry Wentland return NULL; 2814562236bSHarry Wentland } 2824562236bSHarry Wentland 2834562236bSHarry Wentland 284