14562236bSHarry Wentland /*
24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc.
34562236bSHarry Wentland *
44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a
54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"),
64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation
74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense,
84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the
94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions:
104562236bSHarry Wentland *
114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in
124562236bSHarry Wentland * all copies or substantial portions of the Software.
134562236bSHarry Wentland *
144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE.
214562236bSHarry Wentland *
224562236bSHarry Wentland * Authors: AMD
234562236bSHarry Wentland *
244562236bSHarry Wentland */
254562236bSHarry Wentland
264562236bSHarry Wentland #include "dm_services.h"
274562236bSHarry Wentland
284562236bSHarry Wentland #include "include/logger_interface.h"
294562236bSHarry Wentland
304562236bSHarry Wentland #include "irq_service_dce110.h"
314562236bSHarry Wentland
324562236bSHarry Wentland #include "dce/dce_11_0_d.h"
334562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h"
34667e1498SAndrey Grodzovsky
354562236bSHarry Wentland #include "ivsrcid/ivsrcid_vislands30.h"
364562236bSHarry Wentland
37fb3466a4SBhawanpreet Lakha #include "dc.h"
38fb3466a4SBhawanpreet Lakha #include "core_types.h"
391296423bSBhawanpreet Lakha #define DC_LOGGER \
401296423bSBhawanpreet Lakha irq_service->ctx->logger
411296423bSBhawanpreet Lakha
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)4233f2d94eSHarry Wentland static bool hpd_ack(struct irq_service *irq_service,
434562236bSHarry Wentland const struct irq_source_info *info)
444562236bSHarry Wentland {
454562236bSHarry Wentland uint32_t addr = info->status_reg;
464562236bSHarry Wentland uint32_t value = dm_read_reg(irq_service->ctx, addr);
4733f2d94eSHarry Wentland uint32_t current_status = get_reg_field_value(value,
484562236bSHarry Wentland DC_HPD_INT_STATUS,
494562236bSHarry Wentland DC_HPD_SENSE_DELAYED);
504562236bSHarry Wentland
514562236bSHarry Wentland dal_irq_service_ack_generic(irq_service, info);
524562236bSHarry Wentland
534562236bSHarry Wentland value = dm_read_reg(irq_service->ctx, info->enable_reg);
544562236bSHarry Wentland
5533f2d94eSHarry Wentland set_reg_field_value(value, current_status ? 0 : 1,
564562236bSHarry Wentland DC_HPD_INT_CONTROL,
574562236bSHarry Wentland DC_HPD_INT_POLARITY);
584562236bSHarry Wentland
594562236bSHarry Wentland dm_write_reg(irq_service->ctx, info->enable_reg, value);
604562236bSHarry Wentland
614562236bSHarry Wentland return true;
624562236bSHarry Wentland }
634562236bSHarry Wentland
644562236bSHarry Wentland static const struct irq_source_info_funcs hpd_irq_info_funcs = {
654562236bSHarry Wentland .set = NULL,
664562236bSHarry Wentland .ack = hpd_ack
674562236bSHarry Wentland };
684562236bSHarry Wentland
694562236bSHarry Wentland static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
704562236bSHarry Wentland .set = NULL,
714562236bSHarry Wentland .ack = NULL
724562236bSHarry Wentland };
734562236bSHarry Wentland
744562236bSHarry Wentland static const struct irq_source_info_funcs pflip_irq_info_funcs = {
754562236bSHarry Wentland .set = NULL,
764562236bSHarry Wentland .ack = NULL
774562236bSHarry Wentland };
784562236bSHarry Wentland
794562236bSHarry Wentland static const struct irq_source_info_funcs vblank_irq_info_funcs = {
80667e1498SAndrey Grodzovsky .set = dce110_vblank_set,
814562236bSHarry Wentland .ack = NULL
824562236bSHarry Wentland };
834562236bSHarry Wentland
84d2574c33SMario Kleiner static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
85d2574c33SMario Kleiner .set = NULL,
86d2574c33SMario Kleiner .ack = NULL
87d2574c33SMario Kleiner };
88d2574c33SMario Kleiner
894562236bSHarry Wentland #define hpd_int_entry(reg_num)\
904562236bSHarry Wentland [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
914562236bSHarry Wentland .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
924562236bSHarry Wentland .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
934562236bSHarry Wentland .enable_value = {\
944562236bSHarry Wentland DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
954562236bSHarry Wentland ~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
964562236bSHarry Wentland },\
974562236bSHarry Wentland .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
984562236bSHarry Wentland .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
994562236bSHarry Wentland .ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
1004562236bSHarry Wentland .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
1014562236bSHarry Wentland .funcs = &hpd_irq_info_funcs\
1024562236bSHarry Wentland }
1034562236bSHarry Wentland
1044562236bSHarry Wentland #define hpd_rx_int_entry(reg_num)\
1054562236bSHarry Wentland [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
1064562236bSHarry Wentland .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
1074562236bSHarry Wentland .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
1084562236bSHarry Wentland .enable_value = {\
1094562236bSHarry Wentland DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
1104562236bSHarry Wentland ~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
1114562236bSHarry Wentland .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
1124562236bSHarry Wentland .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
1134562236bSHarry Wentland .ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
1144562236bSHarry Wentland .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
1154562236bSHarry Wentland .funcs = &hpd_rx_irq_info_funcs\
1164562236bSHarry Wentland }
1174562236bSHarry Wentland #define pflip_int_entry(reg_num)\
1184562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
1194562236bSHarry Wentland .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
1204562236bSHarry Wentland .enable_mask =\
1214562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
1224562236bSHarry Wentland .enable_value = {\
1234562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
1244562236bSHarry Wentland ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
1254562236bSHarry Wentland .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
1264562236bSHarry Wentland .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
1274562236bSHarry Wentland .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
1284562236bSHarry Wentland .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
1294562236bSHarry Wentland .funcs = &pflip_irq_info_funcs\
1304562236bSHarry Wentland }
1314562236bSHarry Wentland
1324562236bSHarry Wentland #define vupdate_int_entry(reg_num)\
1334562236bSHarry Wentland [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
1344562236bSHarry Wentland .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
1354562236bSHarry Wentland .enable_mask =\
1364562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
1374562236bSHarry Wentland .enable_value = {\
1384562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
1394562236bSHarry Wentland ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
1404562236bSHarry Wentland .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
1414562236bSHarry Wentland .ack_mask =\
1424562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
1434562236bSHarry Wentland .ack_value =\
1444562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
145d2574c33SMario Kleiner .funcs = &vupdate_irq_info_funcs\
1464562236bSHarry Wentland }
1474562236bSHarry Wentland
148b10d51f8SAndrey Grodzovsky #define vblank_int_entry(reg_num)\
149b10d51f8SAndrey Grodzovsky [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
150667e1498SAndrey Grodzovsky .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
151b10d51f8SAndrey Grodzovsky .enable_mask =\
152667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
153b10d51f8SAndrey Grodzovsky .enable_value = {\
154667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155667e1498SAndrey Grodzovsky ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
156667e1498SAndrey Grodzovsky .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
157b10d51f8SAndrey Grodzovsky .ack_mask =\
158667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
159b10d51f8SAndrey Grodzovsky .ack_value =\
160667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
161667e1498SAndrey Grodzovsky .funcs = &vblank_irq_info_funcs,\
162667e1498SAndrey Grodzovsky .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
163b10d51f8SAndrey Grodzovsky }
164b10d51f8SAndrey Grodzovsky
1654562236bSHarry Wentland #define dummy_irq_entry() \
1664562236bSHarry Wentland {\
1674562236bSHarry Wentland .funcs = &dummy_irq_info_funcs\
1684562236bSHarry Wentland }
1694562236bSHarry Wentland
1704562236bSHarry Wentland #define i2c_int_entry(reg_num) \
1714562236bSHarry Wentland [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
1724562236bSHarry Wentland
1734562236bSHarry Wentland #define dp_sink_int_entry(reg_num) \
1744562236bSHarry Wentland [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
1754562236bSHarry Wentland
1764562236bSHarry Wentland #define gpio_pad_int_entry(reg_num) \
1774562236bSHarry Wentland [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
1784562236bSHarry Wentland
1794562236bSHarry Wentland #define dc_underflow_int_entry(reg_num) \
1804562236bSHarry Wentland [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
1814562236bSHarry Wentland
dal_irq_service_dummy_set(struct irq_service * irq_service,const struct irq_source_info * info,bool enable)18233f2d94eSHarry Wentland bool dal_irq_service_dummy_set(struct irq_service *irq_service,
1834562236bSHarry Wentland const struct irq_source_info *info,
1844562236bSHarry Wentland bool enable)
1854562236bSHarry Wentland {
186*741fe8a4SSolomon Chiu DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
187*741fe8a4SSolomon Chiu __func__, info->src_id, info->ext_id);
188*741fe8a4SSolomon Chiu
1894562236bSHarry Wentland return false;
1904562236bSHarry Wentland }
1914562236bSHarry Wentland
dal_irq_service_dummy_ack(struct irq_service * irq_service,const struct irq_source_info * info)19233f2d94eSHarry Wentland bool dal_irq_service_dummy_ack(struct irq_service *irq_service,
1934562236bSHarry Wentland const struct irq_source_info *info)
1944562236bSHarry Wentland {
195*741fe8a4SSolomon Chiu DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
196*741fe8a4SSolomon Chiu __func__, info->src_id, info->ext_id);
197*741fe8a4SSolomon Chiu
1984562236bSHarry Wentland return false;
1994562236bSHarry Wentland }
2004562236bSHarry Wentland
201667e1498SAndrey Grodzovsky
dce110_vblank_set(struct irq_service * irq_service,const struct irq_source_info * info,bool enable)20233f2d94eSHarry Wentland bool dce110_vblank_set(struct irq_service *irq_service,
203667e1498SAndrey Grodzovsky const struct irq_source_info *info,
204667e1498SAndrey Grodzovsky bool enable)
205667e1498SAndrey Grodzovsky {
206667e1498SAndrey Grodzovsky struct dc_context *dc_ctx = irq_service->ctx;
2072b77dcc5SAnthony Koo struct dc *dc = irq_service->ctx->dc;
20833f2d94eSHarry Wentland enum dc_irq_source dal_irq_src =
20933f2d94eSHarry Wentland dc_interrupt_to_irq_source(irq_service->ctx->dc,
210667e1498SAndrey Grodzovsky info->src_id,
211667e1498SAndrey Grodzovsky info->ext_id);
212667e1498SAndrey Grodzovsky uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
213667e1498SAndrey Grodzovsky
214667e1498SAndrey Grodzovsky struct timing_generator *tg =
2152b77dcc5SAnthony Koo dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
216667e1498SAndrey Grodzovsky
217667e1498SAndrey Grodzovsky if (enable) {
218c827206fSHarry Wentland if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
219667e1498SAndrey Grodzovsky DC_ERROR("Failed to get VBLANK!\n");
220667e1498SAndrey Grodzovsky return false;
221667e1498SAndrey Grodzovsky }
222667e1498SAndrey Grodzovsky }
223667e1498SAndrey Grodzovsky
224667e1498SAndrey Grodzovsky dal_irq_service_set_generic(irq_service, info, enable);
225667e1498SAndrey Grodzovsky return true;
226667e1498SAndrey Grodzovsky }
227667e1498SAndrey Grodzovsky
2284562236bSHarry Wentland static const struct irq_source_info_funcs dummy_irq_info_funcs = {
2294562236bSHarry Wentland .set = dal_irq_service_dummy_set,
2304562236bSHarry Wentland .ack = dal_irq_service_dummy_ack
2314562236bSHarry Wentland };
2324562236bSHarry Wentland
2334562236bSHarry Wentland static const struct irq_source_info
2344562236bSHarry Wentland irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
2354562236bSHarry Wentland [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
2364562236bSHarry Wentland hpd_int_entry(0),
2374562236bSHarry Wentland hpd_int_entry(1),
2384562236bSHarry Wentland hpd_int_entry(2),
2394562236bSHarry Wentland hpd_int_entry(3),
2404562236bSHarry Wentland hpd_int_entry(4),
2414562236bSHarry Wentland hpd_int_entry(5),
2424562236bSHarry Wentland hpd_rx_int_entry(0),
2434562236bSHarry Wentland hpd_rx_int_entry(1),
2444562236bSHarry Wentland hpd_rx_int_entry(2),
2454562236bSHarry Wentland hpd_rx_int_entry(3),
2464562236bSHarry Wentland hpd_rx_int_entry(4),
2474562236bSHarry Wentland hpd_rx_int_entry(5),
2484562236bSHarry Wentland i2c_int_entry(1),
2494562236bSHarry Wentland i2c_int_entry(2),
2504562236bSHarry Wentland i2c_int_entry(3),
2514562236bSHarry Wentland i2c_int_entry(4),
2524562236bSHarry Wentland i2c_int_entry(5),
2534562236bSHarry Wentland i2c_int_entry(6),
2544562236bSHarry Wentland dp_sink_int_entry(1),
2554562236bSHarry Wentland dp_sink_int_entry(2),
2564562236bSHarry Wentland dp_sink_int_entry(3),
2574562236bSHarry Wentland dp_sink_int_entry(4),
2584562236bSHarry Wentland dp_sink_int_entry(5),
2594562236bSHarry Wentland dp_sink_int_entry(6),
2604562236bSHarry Wentland [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
2614562236bSHarry Wentland pflip_int_entry(0),
2624562236bSHarry Wentland pflip_int_entry(1),
2634562236bSHarry Wentland pflip_int_entry(2),
2644562236bSHarry Wentland pflip_int_entry(3),
2654562236bSHarry Wentland pflip_int_entry(4),
2664562236bSHarry Wentland pflip_int_entry(5),
2674562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
2684562236bSHarry Wentland gpio_pad_int_entry(0),
2694562236bSHarry Wentland gpio_pad_int_entry(1),
2704562236bSHarry Wentland gpio_pad_int_entry(2),
2714562236bSHarry Wentland gpio_pad_int_entry(3),
2724562236bSHarry Wentland gpio_pad_int_entry(4),
2734562236bSHarry Wentland gpio_pad_int_entry(5),
2744562236bSHarry Wentland gpio_pad_int_entry(6),
2754562236bSHarry Wentland gpio_pad_int_entry(7),
2764562236bSHarry Wentland gpio_pad_int_entry(8),
2774562236bSHarry Wentland gpio_pad_int_entry(9),
2784562236bSHarry Wentland gpio_pad_int_entry(10),
2794562236bSHarry Wentland gpio_pad_int_entry(11),
2804562236bSHarry Wentland gpio_pad_int_entry(12),
2814562236bSHarry Wentland gpio_pad_int_entry(13),
2824562236bSHarry Wentland gpio_pad_int_entry(14),
2834562236bSHarry Wentland gpio_pad_int_entry(15),
2844562236bSHarry Wentland gpio_pad_int_entry(16),
2854562236bSHarry Wentland gpio_pad_int_entry(17),
2864562236bSHarry Wentland gpio_pad_int_entry(18),
2874562236bSHarry Wentland gpio_pad_int_entry(19),
2884562236bSHarry Wentland gpio_pad_int_entry(20),
2894562236bSHarry Wentland gpio_pad_int_entry(21),
2904562236bSHarry Wentland gpio_pad_int_entry(22),
2914562236bSHarry Wentland gpio_pad_int_entry(23),
2924562236bSHarry Wentland gpio_pad_int_entry(24),
2934562236bSHarry Wentland gpio_pad_int_entry(25),
2944562236bSHarry Wentland gpio_pad_int_entry(26),
2954562236bSHarry Wentland gpio_pad_int_entry(27),
2964562236bSHarry Wentland gpio_pad_int_entry(28),
2974562236bSHarry Wentland gpio_pad_int_entry(29),
2984562236bSHarry Wentland gpio_pad_int_entry(30),
2994562236bSHarry Wentland dc_underflow_int_entry(1),
3004562236bSHarry Wentland dc_underflow_int_entry(2),
3014562236bSHarry Wentland dc_underflow_int_entry(3),
3024562236bSHarry Wentland dc_underflow_int_entry(4),
3034562236bSHarry Wentland dc_underflow_int_entry(5),
3044562236bSHarry Wentland dc_underflow_int_entry(6),
3054562236bSHarry Wentland [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
3064562236bSHarry Wentland [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
3074562236bSHarry Wentland vupdate_int_entry(0),
3084562236bSHarry Wentland vupdate_int_entry(1),
3094562236bSHarry Wentland vupdate_int_entry(2),
3104562236bSHarry Wentland vupdate_int_entry(3),
3114562236bSHarry Wentland vupdate_int_entry(4),
3124562236bSHarry Wentland vupdate_int_entry(5),
313b10d51f8SAndrey Grodzovsky vblank_int_entry(0),
314b10d51f8SAndrey Grodzovsky vblank_int_entry(1),
315b10d51f8SAndrey Grodzovsky vblank_int_entry(2),
316b10d51f8SAndrey Grodzovsky vblank_int_entry(3),
317b10d51f8SAndrey Grodzovsky vblank_int_entry(4),
318b10d51f8SAndrey Grodzovsky vblank_int_entry(5),
319b10d51f8SAndrey Grodzovsky
3204562236bSHarry Wentland };
3214562236bSHarry Wentland
to_dal_irq_source_dce110(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)3224562236bSHarry Wentland enum dc_irq_source to_dal_irq_source_dce110(
3234562236bSHarry Wentland struct irq_service *irq_service,
3244562236bSHarry Wentland uint32_t src_id,
3254562236bSHarry Wentland uint32_t ext_id)
3264562236bSHarry Wentland {
3274562236bSHarry Wentland switch (src_id) {
328667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
329b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK1;
330667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
331b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK2;
332667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
333b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK3;
334667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
335b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK4;
336667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
337b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK5;
338667e1498SAndrey Grodzovsky case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
339b10d51f8SAndrey Grodzovsky return DC_IRQ_SOURCE_VBLANK6;
3404562236bSHarry Wentland case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
3414562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE1;
3424562236bSHarry Wentland case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
3434562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE2;
3444562236bSHarry Wentland case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
3454562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE3;
3464562236bSHarry Wentland case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
3474562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE4;
3484562236bSHarry Wentland case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
3494562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE5;
3504562236bSHarry Wentland case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
3514562236bSHarry Wentland return DC_IRQ_SOURCE_VUPDATE6;
3524562236bSHarry Wentland case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
3534562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP1;
3544562236bSHarry Wentland case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
3554562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP2;
3564562236bSHarry Wentland case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
3574562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP3;
3584562236bSHarry Wentland case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
3594562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP4;
3604562236bSHarry Wentland case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
3614562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP5;
3624562236bSHarry Wentland case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
3634562236bSHarry Wentland return DC_IRQ_SOURCE_PFLIP6;
3644562236bSHarry Wentland
3654562236bSHarry Wentland case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
3664562236bSHarry Wentland /* generic src_id for all HPD and HPDRX interrupts */
3674562236bSHarry Wentland switch (ext_id) {
3684562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
3694562236bSHarry Wentland return DC_IRQ_SOURCE_HPD1;
3704562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
3714562236bSHarry Wentland return DC_IRQ_SOURCE_HPD2;
3724562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
3734562236bSHarry Wentland return DC_IRQ_SOURCE_HPD3;
3744562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
3754562236bSHarry Wentland return DC_IRQ_SOURCE_HPD4;
3764562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
3774562236bSHarry Wentland return DC_IRQ_SOURCE_HPD5;
3784562236bSHarry Wentland case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
3794562236bSHarry Wentland return DC_IRQ_SOURCE_HPD6;
3804562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_A:
3814562236bSHarry Wentland return DC_IRQ_SOURCE_HPD1RX;
3824562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_B:
3834562236bSHarry Wentland return DC_IRQ_SOURCE_HPD2RX;
3844562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_C:
3854562236bSHarry Wentland return DC_IRQ_SOURCE_HPD3RX;
3864562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_D:
3874562236bSHarry Wentland return DC_IRQ_SOURCE_HPD4RX;
3884562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_E:
3894562236bSHarry Wentland return DC_IRQ_SOURCE_HPD5RX;
3904562236bSHarry Wentland case VISLANDS30_IV_EXTID_HPD_RX_F:
3914562236bSHarry Wentland return DC_IRQ_SOURCE_HPD6RX;
3924562236bSHarry Wentland default:
3934562236bSHarry Wentland return DC_IRQ_SOURCE_INVALID;
3944562236bSHarry Wentland }
3954562236bSHarry Wentland break;
3964562236bSHarry Wentland
3974562236bSHarry Wentland default:
3984562236bSHarry Wentland return DC_IRQ_SOURCE_INVALID;
3994562236bSHarry Wentland }
4004562236bSHarry Wentland }
4014562236bSHarry Wentland
4024562236bSHarry Wentland static const struct irq_service_funcs irq_service_funcs_dce110 = {
4034562236bSHarry Wentland .to_dal_irq_source = to_dal_irq_source_dce110
4044562236bSHarry Wentland };
4054562236bSHarry Wentland
dce110_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)406d9e32672SAnthony Koo static void dce110_irq_construct(struct irq_service *irq_service,
4074562236bSHarry Wentland struct irq_service_init_data *init_data)
4084562236bSHarry Wentland {
4096be663b5SDave Airlie dal_irq_service_construct(irq_service, init_data);
4104562236bSHarry Wentland
4114562236bSHarry Wentland irq_service->info = irq_source_info_dce110;
4124562236bSHarry Wentland irq_service->funcs = &irq_service_funcs_dce110;
4134562236bSHarry Wentland }
4144562236bSHarry Wentland
41533f2d94eSHarry Wentland struct irq_service *
dal_irq_service_dce110_create(struct irq_service_init_data * init_data)41633f2d94eSHarry Wentland dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
4174562236bSHarry Wentland {
4182004f45eSHarry Wentland struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
4192004f45eSHarry Wentland GFP_KERNEL);
4204562236bSHarry Wentland
4214562236bSHarry Wentland if (!irq_service)
4224562236bSHarry Wentland return NULL;
4234562236bSHarry Wentland
424d9e32672SAnthony Koo dce110_irq_construct(irq_service, init_data);
4254562236bSHarry Wentland return irq_service;
4264562236bSHarry Wentland }
427