1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 27 28 #include "core_types.h" 29 #include "core_status.h" 30 #include "dal_asic_id.h" 31 32 /* TODO unhardcode, 4 for CZ*/ 33 #define MEMORY_TYPE_MULTIPLIER 4 34 35 enum dce_version resource_parse_asic_id( 36 struct hw_asic_id asic_id); 37 38 struct resource_caps { 39 int num_timing_generator; 40 int num_video_plane; 41 int num_audio; 42 int num_stream_encoder; 43 int num_pll; 44 int num_dwb; 45 }; 46 47 struct resource_straps { 48 uint32_t hdmi_disable; 49 uint32_t dc_pinstraps_audio; 50 uint32_t audio_stream_number; 51 }; 52 53 struct resource_create_funcs { 54 void (*read_dce_straps)( 55 struct dc_context *ctx, struct resource_straps *straps); 56 57 struct audio *(*create_audio)( 58 struct dc_context *ctx, unsigned int inst); 59 60 struct stream_encoder *(*create_stream_encoder)( 61 enum engine_id eng_id, struct dc_context *ctx); 62 63 struct dce_hwseq *(*create_hwseq)( 64 struct dc_context *ctx); 65 }; 66 67 bool resource_construct( 68 unsigned int num_virtual_links, 69 struct dc *dc, 70 struct resource_pool *pool, 71 const struct resource_create_funcs *create_funcs); 72 73 struct resource_pool *dc_create_resource_pool( 74 struct dc *dc, 75 int num_virtual_links, 76 enum dce_version dc_version, 77 struct hw_asic_id asic_id); 78 79 void dc_destroy_resource_pool(struct dc *dc); 80 81 enum dc_status resource_map_pool_resources( 82 const struct dc *dc, 83 struct validate_context *context, 84 struct validate_context *old_context); 85 86 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 87 88 enum dc_status resource_build_scaling_params_for_context( 89 const struct dc *dc, 90 struct validate_context *context); 91 92 void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 93 94 void resource_unreference_clock_source( 95 struct resource_context *res_ctx, 96 const struct resource_pool *pool, 97 struct clock_source **clock_source); 98 99 void resource_reference_clock_source( 100 struct resource_context *res_ctx, 101 const struct resource_pool *pool, 102 struct clock_source *clock_source); 103 104 bool resource_are_streams_timing_synchronizable( 105 struct dc_stream_state *stream1, 106 struct dc_stream_state *stream2); 107 108 struct clock_source *resource_find_used_clk_src_for_sharing( 109 struct resource_context *res_ctx, 110 struct pipe_ctx *pipe_ctx); 111 112 struct clock_source *dc_resource_find_first_free_pll( 113 struct resource_context *res_ctx, 114 const struct resource_pool *pool); 115 116 struct pipe_ctx *resource_get_head_pipe_for_stream( 117 struct resource_context *res_ctx, 118 struct dc_stream_state *stream); 119 120 bool resource_attach_surfaces_to_context( 121 struct dc_plane_state *const *plane_state, 122 int surface_count, 123 struct dc_stream_state *dc_stream, 124 struct validate_context *context, 125 const struct resource_pool *pool); 126 127 struct pipe_ctx *find_idle_secondary_pipe( 128 struct resource_context *res_ctx, 129 const struct resource_pool *pool); 130 131 bool resource_is_stream_unchanged( 132 struct validate_context *old_context, struct dc_stream_state *stream); 133 134 bool resource_validate_attach_surfaces( 135 const struct dc_validation_set set[], 136 int set_count, 137 const struct validate_context *old_context, 138 struct validate_context *context, 139 const struct resource_pool *pool); 140 141 void validate_guaranteed_copy_streams( 142 struct validate_context *context, 143 int max_streams); 144 145 void resource_validate_ctx_update_pointer_after_copy( 146 const struct validate_context *src_ctx, 147 struct validate_context *dst_ctx); 148 149 enum dc_status resource_map_clock_resources( 150 const struct dc *dc, 151 struct validate_context *context, 152 struct validate_context *old_context); 153 154 enum dc_status resource_map_phy_clock_resources( 155 const struct dc *dc, 156 struct validate_context *context, 157 struct validate_context *old_context); 158 159 bool pipe_need_reprogram( 160 struct pipe_ctx *pipe_ctx_old, 161 struct pipe_ctx *pipe_ctx); 162 163 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 164 struct bit_depth_reduction_params *fmt_bit_depth); 165 166 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ 167