1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 27 28 #include "core_types.h" 29 #include "core_status.h" 30 #include "core_dc.h" 31 #include "dal_asic_id.h" 32 33 /* TODO unhardcode, 4 for CZ*/ 34 #define MEMORY_TYPE_MULTIPLIER 4 35 36 enum dce_version resource_parse_asic_id( 37 struct hw_asic_id asic_id); 38 39 struct resource_caps { 40 int num_timing_generator; 41 int num_video_plane; 42 int num_audio; 43 int num_stream_encoder; 44 int num_pll; 45 }; 46 47 struct resource_straps { 48 uint32_t hdmi_disable; 49 uint32_t dc_pinstraps_audio; 50 uint32_t audio_stream_number; 51 }; 52 53 struct resource_create_funcs { 54 void (*read_dce_straps)( 55 struct dc_context *ctx, struct resource_straps *straps); 56 57 struct audio *(*create_audio)( 58 struct dc_context *ctx, unsigned int inst); 59 60 struct stream_encoder *(*create_stream_encoder)( 61 enum engine_id eng_id, struct dc_context *ctx); 62 63 struct dce_hwseq *(*create_hwseq)( 64 struct dc_context *ctx); 65 }; 66 67 bool resource_construct( 68 unsigned int num_virtual_links, 69 struct core_dc *dc, 70 struct resource_pool *pool, 71 const struct resource_create_funcs *create_funcs); 72 73 struct resource_pool *dc_create_resource_pool( 74 struct core_dc *dc, 75 int num_virtual_links, 76 enum dce_version dc_version, 77 struct hw_asic_id asic_id); 78 79 void dc_destroy_resource_pool(struct core_dc *dc); 80 81 enum dc_status resource_map_pool_resources( 82 const struct core_dc *dc, 83 struct validate_context *context); 84 85 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 86 87 enum dc_status resource_build_scaling_params_for_context( 88 const struct core_dc *dc, 89 struct validate_context *context); 90 91 void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 92 93 void resource_unreference_clock_source( 94 struct resource_context *res_ctx, 95 const struct resource_pool *pool, 96 struct clock_source **clock_source); 97 98 void resource_reference_clock_source( 99 struct resource_context *res_ctx, 100 const struct resource_pool *pool, 101 struct clock_source *clock_source); 102 103 bool resource_are_streams_timing_synchronizable( 104 const struct core_stream *stream1, 105 const struct core_stream *stream2); 106 107 struct clock_source *resource_find_used_clk_src_for_sharing( 108 struct resource_context *res_ctx, 109 struct pipe_ctx *pipe_ctx); 110 111 struct clock_source *dc_resource_find_first_free_pll( 112 struct resource_context *res_ctx, 113 const struct resource_pool *pool); 114 115 struct pipe_ctx *resource_get_head_pipe_for_stream( 116 struct resource_context *res_ctx, 117 const struct core_stream *stream); 118 119 bool resource_attach_surfaces_to_context( 120 const struct dc_surface *const *surfaces, 121 int surface_count, 122 const struct dc_stream *dc_stream, 123 struct validate_context *context, 124 const struct resource_pool *pool); 125 126 struct pipe_ctx *find_idle_secondary_pipe( 127 struct resource_context *res_ctx, 128 const struct resource_pool *pool); 129 130 bool resource_is_stream_unchanged( 131 const struct validate_context *old_context, const struct core_stream *stream); 132 133 bool is_stream_unchanged( 134 const struct core_stream *old_stream, const struct core_stream *stream); 135 136 bool resource_validate_attach_surfaces( 137 const struct dc_validation_set set[], 138 int set_count, 139 const struct validate_context *old_context, 140 struct validate_context *context, 141 const struct resource_pool *pool); 142 143 void validate_guaranteed_copy_streams( 144 struct validate_context *context, 145 int max_streams); 146 147 void resource_validate_ctx_update_pointer_after_copy( 148 const struct validate_context *src_ctx, 149 struct validate_context *dst_ctx); 150 151 enum dc_status resource_map_clock_resources( 152 const struct core_dc *dc, 153 struct validate_context *context); 154 155 enum dc_status resource_map_phy_clock_resources( 156 const struct core_dc *dc, 157 struct validate_context *context); 158 159 bool pipe_need_reprogram( 160 struct pipe_ctx *pipe_ctx_old, 161 struct pipe_ctx *pipe_ctx); 162 163 void resource_build_bit_depth_reduction_params(const struct core_stream *stream, 164 struct bit_depth_reduction_params *fmt_bit_depth); 165 166 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ 167