1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 27 28 #include "core_types.h" 29 #include "core_status.h" 30 #include "dal_asic_id.h" 31 #include "dm_pp_smu.h" 32 33 #define MEMORY_TYPE_MULTIPLIER_CZ 4 34 #define MEMORY_TYPE_HBM 2 35 36 37 #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0) 38 #define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F) 39 #define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd)) 40 41 enum dce_version resource_parse_asic_id( 42 struct hw_asic_id asic_id); 43 44 struct resource_caps { 45 int num_timing_generator; 46 int num_opp; 47 int num_video_plane; 48 int num_audio; 49 int num_stream_encoder; 50 int num_pll; 51 int num_dwb; 52 int num_ddc; 53 int num_vmid; 54 int num_dsc; 55 unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output). 56 unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters). 57 #if defined(CONFIG_DRM_AMD_DC_DCN) 58 int num_hpo_dp_stream_encoder; 59 int num_hpo_dp_link_encoder; 60 #endif 61 int num_mpc_3dlut; 62 }; 63 64 struct resource_straps { 65 uint32_t hdmi_disable; 66 uint32_t dc_pinstraps_audio; 67 uint32_t audio_stream_number; 68 }; 69 70 struct resource_create_funcs { 71 void (*read_dce_straps)( 72 struct dc_context *ctx, struct resource_straps *straps); 73 74 struct audio *(*create_audio)( 75 struct dc_context *ctx, unsigned int inst); 76 77 struct stream_encoder *(*create_stream_encoder)( 78 enum engine_id eng_id, struct dc_context *ctx); 79 80 #if defined(CONFIG_DRM_AMD_DC_DCN) 81 struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)( 82 enum engine_id eng_id, struct dc_context *ctx); 83 84 struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)( 85 uint8_t inst, 86 struct dc_context *ctx); 87 #endif 88 89 struct dce_hwseq *(*create_hwseq)( 90 struct dc_context *ctx); 91 }; 92 93 bool resource_construct( 94 unsigned int num_virtual_links, 95 struct dc *dc, 96 struct resource_pool *pool, 97 const struct resource_create_funcs *create_funcs); 98 99 struct resource_pool *dc_create_resource_pool(struct dc *dc, 100 const struct dc_init_data *init_data, 101 enum dce_version dc_version); 102 103 void dc_destroy_resource_pool(struct dc *dc); 104 105 enum dc_status resource_map_pool_resources( 106 const struct dc *dc, 107 struct dc_state *context, 108 struct dc_stream_state *stream); 109 110 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 111 112 enum dc_status resource_build_scaling_params_for_context( 113 const struct dc *dc, 114 struct dc_state *context); 115 116 void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 117 118 void resource_unreference_clock_source( 119 struct resource_context *res_ctx, 120 const struct resource_pool *pool, 121 struct clock_source *clock_source); 122 123 void resource_reference_clock_source( 124 struct resource_context *res_ctx, 125 const struct resource_pool *pool, 126 struct clock_source *clock_source); 127 128 int resource_get_clock_source_reference( 129 struct resource_context *res_ctx, 130 const struct resource_pool *pool, 131 struct clock_source *clock_source); 132 133 bool resource_are_streams_timing_synchronizable( 134 struct dc_stream_state *stream1, 135 struct dc_stream_state *stream2); 136 137 bool resource_are_vblanks_synchronizable( 138 struct dc_stream_state *stream1, 139 struct dc_stream_state *stream2); 140 141 struct clock_source *resource_find_used_clk_src_for_sharing( 142 struct resource_context *res_ctx, 143 struct pipe_ctx *pipe_ctx); 144 145 struct clock_source *dc_resource_find_first_free_pll( 146 struct resource_context *res_ctx, 147 const struct resource_pool *pool); 148 149 struct pipe_ctx *resource_get_head_pipe_for_stream( 150 struct resource_context *res_ctx, 151 struct dc_stream_state *stream); 152 153 bool resource_attach_surfaces_to_context( 154 struct dc_plane_state *const *plane_state, 155 int surface_count, 156 struct dc_stream_state *dc_stream, 157 struct dc_state *context, 158 const struct resource_pool *pool); 159 160 struct pipe_ctx *find_idle_secondary_pipe( 161 struct resource_context *res_ctx, 162 const struct resource_pool *pool, 163 const struct pipe_ctx *primary_pipe); 164 165 bool resource_validate_attach_surfaces( 166 const struct dc_validation_set set[], 167 int set_count, 168 const struct dc_state *old_context, 169 struct dc_state *context, 170 const struct resource_pool *pool); 171 172 void resource_validate_ctx_update_pointer_after_copy( 173 const struct dc_state *src_ctx, 174 struct dc_state *dst_ctx); 175 176 enum dc_status resource_map_clock_resources( 177 const struct dc *dc, 178 struct dc_state *context, 179 struct dc_stream_state *stream); 180 181 enum dc_status resource_map_phy_clock_resources( 182 const struct dc *dc, 183 struct dc_state *context, 184 struct dc_stream_state *stream); 185 186 bool pipe_need_reprogram( 187 struct pipe_ctx *pipe_ctx_old, 188 struct pipe_ctx *pipe_ctx); 189 190 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 191 struct bit_depth_reduction_params *fmt_bit_depth); 192 193 void update_audio_usage( 194 struct resource_context *res_ctx, 195 const struct resource_pool *pool, 196 struct audio *audio, 197 bool acquired); 198 199 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format); 200 201 void get_audio_check(struct audio_info *aud_modes, 202 struct audio_check *aud_chk); 203 204 int get_num_mpc_splits(struct pipe_ctx *pipe); 205 206 int get_num_odm_splits(struct pipe_ctx *pipe); 207 208 #if defined(CONFIG_DRM_AMD_DC_DCN) 209 struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( 210 const struct resource_context *res_ctx, 211 const struct resource_pool *pool, 212 const struct dc_link *link); 213 #endif 214 215 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, 216 struct dc_state *context); 217 218 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, 219 struct dc_state *context, 220 uint8_t disabled_master_pipe_idx); 221 222 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter); 223 224 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ 225