1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ 27 28 #include "core_types.h" 29 #include "core_status.h" 30 #include "dal_asic_id.h" 31 #include "dm_pp_smu.h" 32 33 /* TODO unhardcode, 4 for CZ*/ 34 #define MEMORY_TYPE_MULTIPLIER 4 35 36 enum dce_version resource_parse_asic_id( 37 struct hw_asic_id asic_id); 38 39 struct resource_caps { 40 int num_timing_generator; 41 int num_video_plane; 42 int num_audio; 43 int num_stream_encoder; 44 int num_pll; 45 int num_dwb; 46 }; 47 48 struct resource_straps { 49 uint32_t hdmi_disable; 50 uint32_t dc_pinstraps_audio; 51 uint32_t audio_stream_number; 52 }; 53 54 struct resource_create_funcs { 55 void (*read_dce_straps)( 56 struct dc_context *ctx, struct resource_straps *straps); 57 58 struct audio *(*create_audio)( 59 struct dc_context *ctx, unsigned int inst); 60 61 struct stream_encoder *(*create_stream_encoder)( 62 enum engine_id eng_id, struct dc_context *ctx); 63 64 struct dce_hwseq *(*create_hwseq)( 65 struct dc_context *ctx); 66 }; 67 68 bool resource_construct( 69 unsigned int num_virtual_links, 70 struct dc *dc, 71 struct resource_pool *pool, 72 const struct resource_create_funcs *create_funcs); 73 74 struct resource_pool *dc_create_resource_pool( 75 struct dc *dc, 76 int num_virtual_links, 77 enum dce_version dc_version, 78 struct hw_asic_id asic_id); 79 80 void dc_destroy_resource_pool(struct dc *dc); 81 82 enum dc_status resource_map_pool_resources( 83 const struct dc *dc, 84 struct dc_state *context, 85 struct dc_stream_state *stream); 86 87 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 88 89 enum dc_status resource_build_scaling_params_for_context( 90 const struct dc *dc, 91 struct dc_state *context); 92 93 void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 94 95 void resource_unreference_clock_source( 96 struct resource_context *res_ctx, 97 const struct resource_pool *pool, 98 struct clock_source *clock_source); 99 100 void resource_reference_clock_source( 101 struct resource_context *res_ctx, 102 const struct resource_pool *pool, 103 struct clock_source *clock_source); 104 105 bool resource_are_streams_timing_synchronizable( 106 struct dc_stream_state *stream1, 107 struct dc_stream_state *stream2); 108 109 struct clock_source *resource_find_used_clk_src_for_sharing( 110 struct resource_context *res_ctx, 111 struct pipe_ctx *pipe_ctx); 112 113 struct clock_source *dc_resource_find_first_free_pll( 114 struct resource_context *res_ctx, 115 const struct resource_pool *pool); 116 117 struct pipe_ctx *resource_get_head_pipe_for_stream( 118 struct resource_context *res_ctx, 119 struct dc_stream_state *stream); 120 121 bool resource_attach_surfaces_to_context( 122 struct dc_plane_state *const *plane_state, 123 int surface_count, 124 struct dc_stream_state *dc_stream, 125 struct dc_state *context, 126 const struct resource_pool *pool); 127 128 struct pipe_ctx *find_idle_secondary_pipe( 129 struct resource_context *res_ctx, 130 const struct resource_pool *pool); 131 132 bool resource_is_stream_unchanged( 133 struct dc_state *old_context, struct dc_stream_state *stream); 134 135 bool resource_validate_attach_surfaces( 136 const struct dc_validation_set set[], 137 int set_count, 138 const struct dc_state *old_context, 139 struct dc_state *context, 140 const struct resource_pool *pool); 141 142 void validate_guaranteed_copy_streams( 143 struct dc_state *context, 144 int max_streams); 145 146 void resource_validate_ctx_update_pointer_after_copy( 147 const struct dc_state *src_ctx, 148 struct dc_state *dst_ctx); 149 150 enum dc_status resource_map_clock_resources( 151 const struct dc *dc, 152 struct dc_state *context, 153 struct dc_stream_state *stream); 154 155 enum dc_status resource_map_phy_clock_resources( 156 const struct dc *dc, 157 struct dc_state *context, 158 struct dc_stream_state *stream); 159 160 bool pipe_need_reprogram( 161 struct pipe_ctx *pipe_ctx_old, 162 struct pipe_ctx *pipe_ctx); 163 164 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 165 struct bit_depth_reduction_params *fmt_bit_depth); 166 167 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ 168