1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/link_encoder.h" 32 #include "core_status.h" 33 34 enum pipe_gating_control { 35 PIPE_GATING_CONTROL_DISABLE = 0, 36 PIPE_GATING_CONTROL_ENABLE, 37 PIPE_GATING_CONTROL_INIT 38 }; 39 40 struct dce_hwseq_wa { 41 bool blnd_crtc_trigger; 42 bool DEGVIDCN10_253; 43 }; 44 45 struct hwseq_wa_state { 46 bool DEGVIDCN10_253_applied; 47 }; 48 49 struct dce_hwseq { 50 struct dc_context *ctx; 51 const struct dce_hwseq_registers *regs; 52 const struct dce_hwseq_shift *shifts; 53 const struct dce_hwseq_mask *masks; 54 struct dce_hwseq_wa wa; 55 struct hwseq_wa_state wa_state; 56 }; 57 58 struct pipe_ctx; 59 struct dc_state; 60 struct dchub_init_data; 61 struct dc_static_screen_events; 62 struct resource_pool; 63 struct resource_context; 64 65 struct hw_sequencer_funcs { 66 67 void (*init_hw)(struct dc *dc); 68 69 enum dc_status (*apply_ctx_to_hw)( 70 struct dc *dc, struct dc_state *context); 71 72 void (*reset_hw_ctx_wrap)( 73 struct dc *dc, struct dc_state *context); 74 75 void (*apply_ctx_for_surface)( 76 struct dc *dc, 77 const struct dc_stream_state *stream, 78 int num_planes, 79 struct dc_state *context); 80 81 void (*set_plane_config)( 82 const struct dc *dc, 83 struct pipe_ctx *pipe_ctx, 84 struct resource_context *res_ctx); 85 86 void (*program_gamut_remap)( 87 struct pipe_ctx *pipe_ctx); 88 89 void (*program_csc_matrix)( 90 struct pipe_ctx *pipe_ctx, 91 enum dc_color_space colorspace, 92 uint16_t *matrix); 93 94 void (*update_plane_addr)( 95 const struct dc *dc, 96 struct pipe_ctx *pipe_ctx); 97 98 void (*update_dchub)( 99 struct dce_hwseq *hws, 100 struct dchub_init_data *dh_data); 101 102 void (*update_pending_status)( 103 struct pipe_ctx *pipe_ctx); 104 105 bool (*set_input_transfer_func)( 106 struct pipe_ctx *pipe_ctx, 107 const struct dc_plane_state *plane_state); 108 109 bool (*set_output_transfer_func)( 110 struct pipe_ctx *pipe_ctx, 111 const struct dc_stream_state *stream); 112 113 void (*power_down)(struct dc *dc); 114 115 void (*enable_accelerated_mode)(struct dc *dc); 116 117 void (*enable_timing_synchronization)( 118 struct dc *dc, 119 int group_index, 120 int group_size, 121 struct pipe_ctx *grouped_pipes[]); 122 123 void (*enable_per_frame_crtc_position_reset)( 124 struct dc *dc, 125 int group_size, 126 struct pipe_ctx *grouped_pipes[]); 127 128 void (*enable_display_pipe_clock_gating)( 129 struct dc_context *ctx, 130 bool clock_gating); 131 132 bool (*enable_display_power_gating)( 133 struct dc *dc, 134 uint8_t controller_id, 135 struct dc_bios *dcb, 136 enum pipe_gating_control power_gating); 137 138 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 139 140 void (*enable_plane)(struct dc *dc, 141 struct pipe_ctx *pipe, 142 struct dc_state *context); 143 144 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 145 146 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 147 148 void (*disable_stream)(struct pipe_ctx *pipe_ctx, 149 int option); 150 151 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 152 struct dc_link_settings *link_settings); 153 154 void (*pipe_control_lock)( 155 struct dc *dc, 156 struct pipe_ctx *pipe, 157 bool lock); 158 159 void (*set_bandwidth)( 160 struct dc *dc, 161 struct dc_state *context, 162 bool decrease_allowed); 163 164 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 165 int vmin, int vmax); 166 167 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 168 struct crtc_position *position); 169 170 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 171 int num_pipes, const struct dc_static_screen_events *events); 172 173 enum dc_status (*prog_pixclk_crtc_otg)( 174 struct pipe_ctx *pipe_ctx, 175 struct dc_state *context, 176 struct dc *dc); 177 178 void (*setup_stereo)( 179 struct pipe_ctx *pipe_ctx, 180 struct dc *dc); 181 182 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 183 184 void (*log_hw_state)(struct dc *dc); 185 186 void (*wait_for_mpcc_disconnect)(struct dc *dc, 187 struct resource_pool *res_pool, 188 struct pipe_ctx *pipe_ctx); 189 190 void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); 191 void (*optimize_shared_resources)(struct dc *dc); 192 void (*pplib_apply_display_requirements)( 193 struct dc *dc, 194 struct dc_state *context); 195 void (*edp_power_control)( 196 struct dc_link *link, 197 bool enable); 198 void (*edp_backlight_control)( 199 struct dc_link *link, 200 bool enable); 201 202 }; 203 204 void color_space_to_black_color( 205 const struct dc *dc, 206 enum dc_color_space colorspace, 207 struct tg_color *black_color); 208 209 bool hwss_wait_for_blank_complete( 210 struct timing_generator *tg); 211 212 #endif /* __DC_HW_SEQUENCER_H__ */ 213