1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 enum pipe_gating_control { 36 PIPE_GATING_CONTROL_DISABLE = 0, 37 PIPE_GATING_CONTROL_ENABLE, 38 PIPE_GATING_CONTROL_INIT 39 }; 40 41 enum vline_select { 42 VLINE0, 43 VLINE1 44 }; 45 46 struct dce_hwseq_wa { 47 bool blnd_crtc_trigger; 48 bool DEGVIDCN10_253; 49 bool false_optc_underflow; 50 bool DEGVIDCN10_254; 51 }; 52 53 struct hwseq_wa_state { 54 bool DEGVIDCN10_253_applied; 55 }; 56 57 struct dce_hwseq { 58 struct dc_context *ctx; 59 const struct dce_hwseq_registers *regs; 60 const struct dce_hwseq_shift *shifts; 61 const struct dce_hwseq_mask *masks; 62 struct dce_hwseq_wa wa; 63 struct hwseq_wa_state wa_state; 64 }; 65 66 struct pipe_ctx; 67 struct dc_state; 68 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 69 struct dc_stream_status; 70 struct dc_writeback_info; 71 #endif 72 struct dchub_init_data; 73 struct dc_static_screen_events; 74 struct resource_pool; 75 struct resource_context; 76 struct stream_resource; 77 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 78 struct dc_phy_addr_space_config; 79 struct dc_virtual_addr_space_config; 80 #endif 81 82 struct hw_sequencer_funcs { 83 84 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 85 86 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 87 88 void (*init_hw)(struct dc *dc); 89 90 void (*init_pipes)(struct dc *dc, struct dc_state *context); 91 92 enum dc_status (*apply_ctx_to_hw)( 93 struct dc *dc, struct dc_state *context); 94 95 void (*reset_hw_ctx_wrap)( 96 struct dc *dc, struct dc_state *context); 97 98 void (*apply_ctx_for_surface)( 99 struct dc *dc, 100 const struct dc_stream_state *stream, 101 int num_planes, 102 struct dc_state *context); 103 104 void (*program_gamut_remap)( 105 struct pipe_ctx *pipe_ctx); 106 107 void (*program_output_csc)(struct dc *dc, 108 struct pipe_ctx *pipe_ctx, 109 enum dc_color_space colorspace, 110 uint16_t *matrix, 111 int opp_id); 112 113 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 114 void (*program_triplebuffer)( 115 const struct dc *dc, 116 struct pipe_ctx *pipe_ctx, 117 bool enableTripleBuffer); 118 void (*set_flip_control_gsl)( 119 struct pipe_ctx *pipe_ctx, 120 bool flip_immediate); 121 #endif 122 123 void (*update_plane_addr)( 124 const struct dc *dc, 125 struct pipe_ctx *pipe_ctx); 126 127 void (*plane_atomic_disconnect)( 128 struct dc *dc, 129 struct pipe_ctx *pipe_ctx); 130 131 void (*update_dchub)( 132 struct dce_hwseq *hws, 133 struct dchub_init_data *dh_data); 134 135 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 136 int (*init_sys_ctx)( 137 struct dce_hwseq *hws, 138 struct dc *dc, 139 struct dc_phy_addr_space_config *pa_config); 140 void (*init_vm_ctx)( 141 struct dce_hwseq *hws, 142 struct dc *dc, 143 struct dc_virtual_addr_space_config *va_config, 144 int vmid); 145 #endif 146 void (*update_mpcc)( 147 struct dc *dc, 148 struct pipe_ctx *pipe_ctx); 149 150 void (*update_pending_status)( 151 struct pipe_ctx *pipe_ctx); 152 153 bool (*set_input_transfer_func)( 154 struct pipe_ctx *pipe_ctx, 155 const struct dc_plane_state *plane_state); 156 157 bool (*set_output_transfer_func)( 158 struct pipe_ctx *pipe_ctx, 159 const struct dc_stream_state *stream); 160 161 void (*power_down)(struct dc *dc); 162 163 void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context); 164 165 void (*enable_timing_synchronization)( 166 struct dc *dc, 167 int group_index, 168 int group_size, 169 struct pipe_ctx *grouped_pipes[]); 170 171 void (*enable_per_frame_crtc_position_reset)( 172 struct dc *dc, 173 int group_size, 174 struct pipe_ctx *grouped_pipes[]); 175 176 void (*enable_display_pipe_clock_gating)( 177 struct dc_context *ctx, 178 bool clock_gating); 179 180 bool (*enable_display_power_gating)( 181 struct dc *dc, 182 uint8_t controller_id, 183 struct dc_bios *dcb, 184 enum pipe_gating_control power_gating); 185 186 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 187 188 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 189 190 void (*send_immediate_sdp_message)( 191 struct pipe_ctx *pipe_ctx, 192 const uint8_t *custom_sdp_message, 193 unsigned int sdp_message_size); 194 195 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 196 197 void (*disable_stream)(struct pipe_ctx *pipe_ctx, 198 int option); 199 200 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 201 struct dc_link_settings *link_settings); 202 203 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 204 205 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 206 207 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option); 208 209 void (*pipe_control_lock)( 210 struct dc *dc, 211 struct pipe_ctx *pipe, 212 bool lock); 213 214 void (*pipe_control_lock_global)( 215 struct dc *dc, 216 struct pipe_ctx *pipe, 217 bool lock); 218 void (*blank_pixel_data)( 219 struct dc *dc, 220 struct pipe_ctx *pipe_ctx, 221 bool blank); 222 223 void (*prepare_bandwidth)( 224 struct dc *dc, 225 struct dc_state *context); 226 void (*optimize_bandwidth)( 227 struct dc *dc, 228 struct dc_state *context); 229 230 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 231 bool (*update_bandwidth)( 232 struct dc *dc, 233 struct dc_state *context); 234 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 235 #endif 236 237 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 238 int vmin, int vmax); 239 240 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 241 struct crtc_position *position); 242 243 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 244 int num_pipes, const struct dc_static_screen_events *events); 245 246 enum dc_status (*enable_stream_timing)( 247 struct pipe_ctx *pipe_ctx, 248 struct dc_state *context, 249 struct dc *dc); 250 251 void (*setup_stereo)( 252 struct pipe_ctx *pipe_ctx, 253 struct dc *dc); 254 255 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 256 257 void (*log_hw_state)(struct dc *dc, 258 struct dc_log_buffer_ctx *log_ctx); 259 void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask); 260 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 261 262 void (*wait_for_mpcc_disconnect)(struct dc *dc, 263 struct resource_pool *res_pool, 264 struct pipe_ctx *pipe_ctx); 265 266 void (*edp_power_control)( 267 struct dc_link *link, 268 bool enable); 269 void (*edp_backlight_control)( 270 struct dc_link *link, 271 bool enable); 272 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 273 274 void (*set_cursor_position)(struct pipe_ctx *pipe); 275 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 276 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 277 278 void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline); 279 void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx); 280 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); 281 282 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 283 void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 284 void (*program_all_writeback_pipes_in_tree)( 285 struct dc *dc, 286 const struct dc_stream_state *stream, 287 struct dc_state *context); 288 void (*update_writeback)(struct dc *dc, 289 const struct dc_stream_status *stream_status, 290 struct dc_writeback_info *wb_info); 291 void (*enable_writeback)(struct dc *dc, 292 const struct dc_stream_status *stream_status, 293 struct dc_writeback_info *wb_info); 294 void (*disable_writeback)(struct dc *dc, 295 unsigned int dwb_pipe_inst); 296 #endif 297 }; 298 299 void color_space_to_black_color( 300 const struct dc *dc, 301 enum dc_color_space colorspace, 302 struct tg_color *black_color); 303 304 bool hwss_wait_for_blank_complete( 305 struct timing_generator *tg); 306 307 const uint16_t *find_color_matrix( 308 enum dc_color_space color_space, 309 uint32_t *array_size); 310 311 #endif /* __DC_HW_SEQUENCER_H__ */ 312