1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_HW_SEQUENCER_H__
27 #define __DC_HW_SEQUENCER_H__
28 #include "dc_types.h"
29 #include "clock_source.h"
30 #include "inc/hw/timing_generator.h"
31 #include "inc/hw/opp.h"
32 #include "inc/hw/link_encoder.h"
33 #include "core_status.h"
34 
35 #define EDP_BACKLIGHT_RAMP_DISABLE_LEVEL 0xFFFFFFFF
36 
37 enum pipe_gating_control {
38 	PIPE_GATING_CONTROL_DISABLE = 0,
39 	PIPE_GATING_CONTROL_ENABLE,
40 	PIPE_GATING_CONTROL_INIT
41 };
42 
43 struct dce_hwseq_wa {
44 	bool blnd_crtc_trigger;
45 	bool DEGVIDCN10_253;
46 	bool false_optc_underflow;
47 };
48 
49 struct hwseq_wa_state {
50 	bool DEGVIDCN10_253_applied;
51 };
52 
53 struct dce_hwseq {
54 	struct dc_context *ctx;
55 	const struct dce_hwseq_registers *regs;
56 	const struct dce_hwseq_shift *shifts;
57 	const struct dce_hwseq_mask *masks;
58 	struct dce_hwseq_wa wa;
59 	struct hwseq_wa_state wa_state;
60 };
61 
62 struct pipe_ctx;
63 struct dc_state;
64 struct dchub_init_data;
65 struct dc_static_screen_events;
66 struct resource_pool;
67 struct resource_context;
68 struct stream_resource;
69 
70 struct hw_sequencer_funcs {
71 
72 	void (*init_hw)(struct dc *dc);
73 
74 	enum dc_status (*apply_ctx_to_hw)(
75 			struct dc *dc, struct dc_state *context);
76 
77 	void (*reset_hw_ctx_wrap)(
78 			struct dc *dc, struct dc_state *context);
79 
80 	void (*apply_ctx_for_surface)(
81 			struct dc *dc,
82 			const struct dc_stream_state *stream,
83 			int num_planes,
84 			struct dc_state *context);
85 
86 	void (*program_gamut_remap)(
87 			struct pipe_ctx *pipe_ctx);
88 
89 	void (*program_csc_matrix)(
90 			struct pipe_ctx *pipe_ctx,
91 			enum dc_color_space colorspace,
92 			uint16_t *matrix);
93 
94 	void (*program_output_csc)(struct dc *dc,
95 			struct pipe_ctx *pipe_ctx,
96 			enum dc_color_space colorspace,
97 			uint16_t *matrix,
98 			int opp_id);
99 
100 	void (*update_plane_addr)(
101 		const struct dc *dc,
102 		struct pipe_ctx *pipe_ctx);
103 
104 	void (*update_dchub)(
105 		struct dce_hwseq *hws,
106 		struct dchub_init_data *dh_data);
107 
108 	void (*update_pending_status)(
109 			struct pipe_ctx *pipe_ctx);
110 
111 	bool (*set_input_transfer_func)(
112 				struct pipe_ctx *pipe_ctx,
113 				const struct dc_plane_state *plane_state);
114 
115 	bool (*set_output_transfer_func)(
116 				struct pipe_ctx *pipe_ctx,
117 				const struct dc_stream_state *stream);
118 
119 	void (*power_down)(struct dc *dc);
120 
121 	void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
122 
123 	void (*enable_timing_synchronization)(
124 			struct dc *dc,
125 			int group_index,
126 			int group_size,
127 			struct pipe_ctx *grouped_pipes[]);
128 
129 	void (*enable_per_frame_crtc_position_reset)(
130 			struct dc *dc,
131 			int group_size,
132 			struct pipe_ctx *grouped_pipes[]);
133 
134 	void (*enable_display_pipe_clock_gating)(
135 					struct dc_context *ctx,
136 					bool clock_gating);
137 
138 	bool (*enable_display_power_gating)(
139 					struct dc *dc,
140 					uint8_t controller_id,
141 					struct dc_bios *dcb,
142 					enum pipe_gating_control power_gating);
143 
144 	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
145 
146 	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
147 
148 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
149 
150 	void (*disable_stream)(struct pipe_ctx *pipe_ctx,
151 			int option);
152 
153 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
154 			struct dc_link_settings *link_settings);
155 
156 	void (*blank_stream)(struct pipe_ctx *pipe_ctx);
157 	void (*pipe_control_lock)(
158 				struct dc *dc,
159 				struct pipe_ctx *pipe,
160 				bool lock);
161 	void (*blank_pixel_data)(
162 			struct dc *dc,
163 			struct stream_resource *stream_res,
164 			struct dc_stream_state *stream,
165 			bool blank);
166 
167 	void (*set_bandwidth)(
168 			struct dc *dc,
169 			struct dc_state *context,
170 			bool decrease_allowed);
171 
172 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
173 			int vmin, int vmax);
174 
175 	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
176 			struct crtc_position *position);
177 
178 	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
179 			int num_pipes, const struct dc_static_screen_events *events);
180 
181 	enum dc_status (*enable_stream_timing)(
182 			struct pipe_ctx *pipe_ctx,
183 			struct dc_state *context,
184 			struct dc *dc);
185 
186 	void (*setup_stereo)(
187 			struct pipe_ctx *pipe_ctx,
188 			struct dc *dc);
189 
190 	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
191 
192 	void (*log_hw_state)(struct dc *dc);
193 
194 	void (*wait_for_mpcc_disconnect)(struct dc *dc,
195 			struct resource_pool *res_pool,
196 			struct pipe_ctx *pipe_ctx);
197 
198 	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
199 	void (*optimize_shared_resources)(struct dc *dc);
200 	void (*pplib_apply_display_requirements)(
201 			struct dc *dc,
202 			struct dc_state *context);
203 	void (*edp_power_control)(
204 			struct dc_link *link,
205 			bool enable);
206 	void (*edp_backlight_control)(
207 			struct dc_link *link,
208 			bool enable);
209 	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
210 
211 	void (*set_cursor_position)(struct pipe_ctx *pipe);
212 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
213 
214 };
215 
216 void color_space_to_black_color(
217 	const struct dc *dc,
218 	enum dc_color_space colorspace,
219 	struct tg_color *black_color);
220 
221 bool hwss_wait_for_blank_complete(
222 		struct timing_generator *tg);
223 
224 const uint16_t *find_color_matrix(
225 		enum dc_color_space color_space,
226 		uint32_t *array_size);
227 
228 #endif /* __DC_HW_SEQUENCER_H__ */
229