1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 enum vline_select { 36 VLINE0, 37 VLINE1 38 }; 39 40 struct pipe_ctx; 41 struct dc_state; 42 struct dc_stream_status; 43 struct dc_writeback_info; 44 struct dchub_init_data; 45 struct dc_static_screen_params; 46 struct resource_pool; 47 struct dc_phy_addr_space_config; 48 struct dc_virtual_addr_space_config; 49 struct dpp; 50 struct dce_hwseq; 51 52 struct hw_sequencer_funcs { 53 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 54 void (*hardware_release)(struct dc *dc); 55 #endif 56 /* Embedded Display Related */ 57 void (*edp_power_control)(struct dc_link *link, bool enable); 58 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 59 60 /* Pipe Programming Related */ 61 void (*init_hw)(struct dc *dc); 62 void (*power_down_on_boot)(struct dc *dc); 63 void (*enable_accelerated_mode)(struct dc *dc, 64 struct dc_state *context); 65 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 66 struct dc_state *context); 67 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 68 void (*apply_ctx_for_surface)(struct dc *dc, 69 const struct dc_stream_state *stream, 70 int num_planes, struct dc_state *context); 71 void (*program_front_end_for_ctx)(struct dc *dc, 72 struct dc_state *context); 73 void (*wait_for_pending_cleared)(struct dc *dc, 74 struct dc_state *context); 75 void (*post_unlock_program_front_end)(struct dc *dc, 76 struct dc_state *context); 77 void (*update_plane_addr)(const struct dc *dc, 78 struct pipe_ctx *pipe_ctx); 79 void (*update_dchub)(struct dce_hwseq *hws, 80 struct dchub_init_data *dh_data); 81 void (*wait_for_mpcc_disconnect)(struct dc *dc, 82 struct resource_pool *res_pool, 83 struct pipe_ctx *pipe_ctx); 84 void (*edp_backlight_control)( 85 struct dc_link *link, 86 bool enable); 87 void (*program_triplebuffer)(const struct dc *dc, 88 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 89 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 90 void (*power_down)(struct dc *dc); 91 92 /* Pipe Lock Related */ 93 void (*pipe_control_lock)(struct dc *dc, 94 struct pipe_ctx *pipe, bool lock); 95 void (*interdependent_update_lock)(struct dc *dc, 96 struct dc_state *context, bool lock); 97 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 98 bool flip_immediate); 99 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 100 101 /* Timing Related */ 102 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 103 struct crtc_position *position); 104 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 105 void (*calc_vupdate_position)( 106 struct dc *dc, 107 struct pipe_ctx *pipe_ctx, 108 uint32_t *start_line, 109 uint32_t *end_line); 110 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 111 int group_size, struct pipe_ctx *grouped_pipes[]); 112 void (*enable_timing_synchronization)(struct dc *dc, 113 int group_index, int group_size, 114 struct pipe_ctx *grouped_pipes[]); 115 void (*setup_periodic_interrupt)(struct dc *dc, 116 struct pipe_ctx *pipe_ctx, 117 enum vline_select vline); 118 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 119 unsigned int vmin, unsigned int vmax, 120 unsigned int vmid, unsigned int vmid_frame_number); 121 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 122 int num_pipes, 123 const struct dc_static_screen_params *events); 124 #ifndef TRIM_FSFT 125 bool (*optimize_timing_for_fsft)(struct dc *dc, 126 struct dc_crtc_timing *timing, 127 unsigned int max_input_rate_in_khz); 128 #endif 129 130 /* Stream Related */ 131 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 132 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 133 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 134 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 135 struct dc_link_settings *link_settings); 136 137 /* Bandwidth Related */ 138 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 139 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 140 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 141 142 /* Infopacket Related */ 143 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 144 void (*send_immediate_sdp_message)( 145 struct pipe_ctx *pipe_ctx, 146 const uint8_t *custom_sdp_message, 147 unsigned int sdp_message_size); 148 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 149 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 150 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 151 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 152 153 /* Cursor Related */ 154 void (*set_cursor_position)(struct pipe_ctx *pipe); 155 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 156 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 157 158 /* Colour Related */ 159 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 160 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 161 enum dc_color_space colorspace, 162 uint16_t *matrix, int opp_id); 163 164 /* VM Related */ 165 int (*init_sys_ctx)(struct dce_hwseq *hws, 166 struct dc *dc, 167 struct dc_phy_addr_space_config *pa_config); 168 void (*init_vm_ctx)(struct dce_hwseq *hws, 169 struct dc *dc, 170 struct dc_virtual_addr_space_config *va_config, 171 int vmid); 172 173 /* Writeback Related */ 174 void (*update_writeback)(struct dc *dc, 175 struct dc_writeback_info *wb_info, 176 struct dc_state *context); 177 void (*enable_writeback)(struct dc *dc, 178 struct dc_writeback_info *wb_info, 179 struct dc_state *context); 180 void (*disable_writeback)(struct dc *dc, 181 unsigned int dwb_pipe_inst); 182 183 bool (*mmhubbub_warmup)(struct dc *dc, 184 unsigned int num_dwb, 185 struct dc_writeback_info *wb_info); 186 187 /* Clock Related */ 188 enum dc_status (*set_clock)(struct dc *dc, 189 enum dc_clock_type clock_type, 190 uint32_t clk_khz, uint32_t stepping); 191 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 192 struct dc_clock_config *clock_cfg); 193 void (*optimize_pwr_state)(const struct dc *dc, 194 struct dc_state *context); 195 void (*exit_optimized_pwr_state)(const struct dc *dc, 196 struct dc_state *context); 197 198 /* Audio Related */ 199 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 200 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 201 202 /* Stereo 3D Related */ 203 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 204 205 /* HW State Logging Related */ 206 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 207 void (*get_hw_state)(struct dc *dc, char *pBuf, 208 unsigned int bufSize, unsigned int mask); 209 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 210 211 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 212 uint32_t backlight_pwm_u16_16, 213 uint32_t frame_ramp); 214 215 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 216 217 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 218 219 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 220 /* Idle Optimization Related */ 221 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 222 #endif 223 224 bool (*is_abm_supported)(struct dc *dc, 225 struct dc_state *context, struct dc_stream_state *stream); 226 }; 227 228 void color_space_to_black_color( 229 const struct dc *dc, 230 enum dc_color_space colorspace, 231 struct tg_color *black_color); 232 233 bool hwss_wait_for_blank_complete( 234 struct timing_generator *tg); 235 236 const uint16_t *find_color_matrix( 237 enum dc_color_space color_space, 238 uint32_t *array_size); 239 240 #endif /* __DC_HW_SEQUENCER_H__ */ 241