1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "core_types.h" 29 #include "timing_generator.h" 30 31 enum pipe_gating_control { 32 PIPE_GATING_CONTROL_DISABLE = 0, 33 PIPE_GATING_CONTROL_ENABLE, 34 PIPE_GATING_CONTROL_INIT 35 }; 36 37 struct dce_hwseq_wa { 38 bool blnd_crtc_trigger; 39 }; 40 41 struct dce_hwseq { 42 struct dc_context *ctx; 43 const struct dce_hwseq_registers *regs; 44 const struct dce_hwseq_shift *shifts; 45 const struct dce_hwseq_mask *masks; 46 struct dce_hwseq_wa wa; 47 }; 48 49 50 struct hw_sequencer_funcs { 51 52 void (*init_hw)(struct core_dc *dc); 53 54 enum dc_status (*apply_ctx_to_hw)( 55 struct core_dc *dc, struct validate_context *context); 56 57 void (*reset_hw_ctx_wrap)( 58 struct core_dc *dc, struct validate_context *context); 59 60 void (*apply_ctx_for_surface)( 61 struct core_dc *dc, 62 struct core_surface *surface, 63 struct validate_context *context); 64 65 void (*set_plane_config)( 66 const struct core_dc *dc, 67 struct pipe_ctx *pipe_ctx, 68 struct resource_context *res_ctx); 69 70 void (*update_plane_addr)( 71 const struct core_dc *dc, 72 struct pipe_ctx *pipe_ctx); 73 74 void (*update_pending_status)( 75 struct pipe_ctx *pipe_ctx); 76 77 bool (*set_input_transfer_func)( 78 struct pipe_ctx *pipe_ctx, 79 const struct core_surface *surface); 80 81 bool (*set_output_transfer_func)( 82 struct pipe_ctx *pipe_ctx, 83 const struct core_surface *surface, 84 const struct core_stream *stream); 85 86 void (*power_down)(struct core_dc *dc); 87 88 void (*enable_accelerated_mode)(struct core_dc *dc); 89 90 void (*enable_timing_synchronization)( 91 struct core_dc *dc, 92 int group_index, 93 int group_size, 94 struct pipe_ctx *grouped_pipes[]); 95 96 void (*enable_display_pipe_clock_gating)( 97 struct dc_context *ctx, 98 bool clock_gating); 99 100 bool (*enable_display_power_gating)( 101 struct core_dc *dc, 102 uint8_t controller_id, 103 struct dc_bios *dcb, 104 enum pipe_gating_control power_gating); 105 106 void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe); 107 108 void (*power_on_front_end)(struct core_dc *dc, 109 struct pipe_ctx *pipe, 110 struct validate_context *context); 111 112 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 113 114 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 115 116 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 117 118 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 119 struct dc_link_settings *link_settings); 120 121 void (*pipe_control_lock)( 122 struct core_dc *dc, 123 struct pipe_ctx *pipe, 124 bool lock); 125 126 void (*set_displaymarks)( 127 const struct core_dc *dc, 128 struct validate_context *context); 129 130 void (*set_bandwidth)( 131 struct core_dc *dc, 132 struct validate_context *context, 133 bool decrease_allowed); 134 135 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 136 int vmin, int vmax); 137 138 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 139 int num_pipes, int value); 140 141 enum dc_status (*prog_pixclk_crtc_otg)( 142 struct pipe_ctx *pipe_ctx, 143 struct validate_context *context, 144 struct core_dc *dc); 145 }; 146 147 void color_space_to_black_color( 148 const struct core_dc *dc, 149 enum dc_color_space colorspace, 150 struct tg_color *black_color); 151 152 bool hwss_wait_for_blank_complete( 153 struct timing_generator *tg); 154 155 #endif /* __DC_HW_SEQUENCER_H__ */ 156