1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/link_encoder.h" 32 #include "core_status.h" 33 34 enum pipe_gating_control { 35 PIPE_GATING_CONTROL_DISABLE = 0, 36 PIPE_GATING_CONTROL_ENABLE, 37 PIPE_GATING_CONTROL_INIT 38 }; 39 40 struct dce_hwseq_wa { 41 bool blnd_crtc_trigger; 42 }; 43 44 struct dce_hwseq { 45 struct dc_context *ctx; 46 const struct dce_hwseq_registers *regs; 47 const struct dce_hwseq_shift *shifts; 48 const struct dce_hwseq_mask *masks; 49 struct dce_hwseq_wa wa; 50 }; 51 52 struct pipe_ctx; 53 struct dc_state; 54 struct dchub_init_data; 55 struct dc_static_screen_events; 56 struct resource_pool; 57 struct resource_context; 58 59 struct hw_sequencer_funcs { 60 61 void (*init_hw)(struct dc *dc); 62 63 enum dc_status (*apply_ctx_to_hw)( 64 struct dc *dc, struct dc_state *context); 65 66 void (*reset_hw_ctx_wrap)( 67 struct dc *dc, struct dc_state *context); 68 69 void (*apply_ctx_for_surface)( 70 struct dc *dc, 71 const struct dc_stream_state *stream, 72 int num_planes, 73 struct dc_state *context); 74 75 void (*set_plane_config)( 76 const struct dc *dc, 77 struct pipe_ctx *pipe_ctx, 78 struct resource_context *res_ctx); 79 80 void (*program_gamut_remap)( 81 struct pipe_ctx *pipe_ctx); 82 83 void (*program_csc_matrix)( 84 struct pipe_ctx *pipe_ctx, 85 enum dc_color_space colorspace, 86 uint16_t *matrix); 87 88 void (*update_plane_addr)( 89 const struct dc *dc, 90 struct pipe_ctx *pipe_ctx); 91 92 void (*update_dchub)( 93 struct dce_hwseq *hws, 94 struct dchub_init_data *dh_data); 95 96 void (*update_pending_status)( 97 struct pipe_ctx *pipe_ctx); 98 99 bool (*set_input_transfer_func)( 100 struct pipe_ctx *pipe_ctx, 101 const struct dc_plane_state *plane_state); 102 103 bool (*set_output_transfer_func)( 104 struct pipe_ctx *pipe_ctx, 105 const struct dc_stream_state *stream); 106 107 void (*power_down)(struct dc *dc); 108 109 void (*enable_accelerated_mode)(struct dc *dc); 110 111 void (*enable_timing_synchronization)( 112 struct dc *dc, 113 int group_index, 114 int group_size, 115 struct pipe_ctx *grouped_pipes[]); 116 117 void (*enable_display_pipe_clock_gating)( 118 struct dc_context *ctx, 119 bool clock_gating); 120 121 bool (*enable_display_power_gating)( 122 struct dc *dc, 123 uint8_t controller_id, 124 struct dc_bios *dcb, 125 enum pipe_gating_control power_gating); 126 127 void (*power_down_front_end)(struct dc *dc, int fe_idx); 128 129 void (*power_on_front_end)(struct dc *dc, 130 struct pipe_ctx *pipe, 131 struct dc_state *context); 132 133 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 134 135 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 136 137 void (*disable_stream)(struct pipe_ctx *pipe_ctx, 138 int option); 139 140 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 141 struct dc_link_settings *link_settings); 142 143 void (*pipe_control_lock)( 144 struct dc *dc, 145 struct pipe_ctx *pipe, 146 bool lock); 147 148 void (*set_bandwidth)( 149 struct dc *dc, 150 struct dc_state *context, 151 bool decrease_allowed); 152 153 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 154 int vmin, int vmax); 155 156 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 157 struct crtc_position *position); 158 159 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 160 int num_pipes, const struct dc_static_screen_events *events); 161 162 enum dc_status (*prog_pixclk_crtc_otg)( 163 struct pipe_ctx *pipe_ctx, 164 struct dc_state *context, 165 struct dc *dc); 166 167 void (*setup_stereo)( 168 struct pipe_ctx *pipe_ctx, 169 struct dc *dc); 170 171 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 172 173 void (*log_hw_state)(struct dc *dc); 174 175 void (*wait_for_mpcc_disconnect)(struct dc *dc, 176 struct resource_pool *res_pool, 177 struct pipe_ctx *pipe_ctx); 178 179 void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); 180 void (*optimize_shared_resources)(struct dc *dc); 181 void (*edp_power_control)( 182 struct link_encoder *enc, 183 bool enable); 184 void (*edp_backlight_control)( 185 struct dc_link *link, 186 bool enable); 187 }; 188 189 void color_space_to_black_color( 190 const struct dc *dc, 191 enum dc_color_space colorspace, 192 struct tg_color *black_color); 193 194 bool hwss_wait_for_blank_complete( 195 struct timing_generator *tg); 196 197 #endif /* __DC_HW_SEQUENCER_H__ */ 198