1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_HW_SEQUENCER_H__
27 #define __DC_HW_SEQUENCER_H__
28 #include "dc_types.h"
29 #include "clock_source.h"
30 #include "inc/hw/timing_generator.h"
31 #include "inc/hw/opp.h"
32 #include "inc/hw/link_encoder.h"
33 #include "core_status.h"
34 
35 enum pipe_gating_control {
36 	PIPE_GATING_CONTROL_DISABLE = 0,
37 	PIPE_GATING_CONTROL_ENABLE,
38 	PIPE_GATING_CONTROL_INIT
39 };
40 
41 enum vline_select {
42 	VLINE0,
43 	VLINE1
44 };
45 
46 struct dce_hwseq_wa {
47 	bool blnd_crtc_trigger;
48 	bool DEGVIDCN10_253;
49 	bool false_optc_underflow;
50 	bool DEGVIDCN10_254;
51 	bool DEGVIDCN21;
52 };
53 
54 struct hwseq_wa_state {
55 	bool DEGVIDCN10_253_applied;
56 };
57 
58 struct dce_hwseq {
59 	struct dc_context *ctx;
60 	const struct dce_hwseq_registers *regs;
61 	const struct dce_hwseq_shift *shifts;
62 	const struct dce_hwseq_mask *masks;
63 	struct dce_hwseq_wa wa;
64 	struct hwseq_wa_state wa_state;
65 };
66 
67 struct pipe_ctx;
68 struct dc_state;
69 struct dc_stream_status;
70 struct dc_writeback_info;
71 struct dchub_init_data;
72 struct dc_static_screen_events;
73 struct resource_pool;
74 struct resource_context;
75 struct stream_resource;
76 struct dc_phy_addr_space_config;
77 struct dc_virtual_addr_space_config;
78 struct hubp;
79 struct dpp;
80 
81 struct hw_sequencer_funcs {
82 
83 	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
84 
85 	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
86 
87 	void (*init_hw)(struct dc *dc);
88 
89 	void (*init_pipes)(struct dc *dc, struct dc_state *context);
90 
91 	enum dc_status (*apply_ctx_to_hw)(
92 			struct dc *dc, struct dc_state *context);
93 
94 	void (*reset_hw_ctx_wrap)(
95 			struct dc *dc, struct dc_state *context);
96 
97 	void (*apply_ctx_for_surface)(
98 			struct dc *dc,
99 			const struct dc_stream_state *stream,
100 			int num_planes,
101 			struct dc_state *context);
102 
103 	void (*program_gamut_remap)(
104 			struct pipe_ctx *pipe_ctx);
105 
106 	void (*program_output_csc)(struct dc *dc,
107 			struct pipe_ctx *pipe_ctx,
108 			enum dc_color_space colorspace,
109 			uint16_t *matrix,
110 			int opp_id);
111 
112 	void (*program_front_end_for_ctx)(
113 			struct dc *dc,
114 			struct dc_state *context);
115 	void (*program_triplebuffer)(
116 		const struct dc *dc,
117 		struct pipe_ctx *pipe_ctx,
118 		bool enableTripleBuffer);
119 	void (*set_flip_control_gsl)(
120 		struct pipe_ctx *pipe_ctx,
121 		bool flip_immediate);
122 
123 	void (*update_plane_addr)(
124 		const struct dc *dc,
125 		struct pipe_ctx *pipe_ctx);
126 
127 	void (*plane_atomic_disconnect)(
128 		struct dc *dc,
129 		struct pipe_ctx *pipe_ctx);
130 
131 	void (*update_dchub)(
132 		struct dce_hwseq *hws,
133 		struct dchub_init_data *dh_data);
134 
135 	int (*init_sys_ctx)(
136 			struct dce_hwseq *hws,
137 			struct dc *dc,
138 			struct dc_phy_addr_space_config *pa_config);
139 	void (*init_vm_ctx)(
140 			struct dce_hwseq *hws,
141 			struct dc *dc,
142 			struct dc_virtual_addr_space_config *va_config,
143 			int vmid);
144 	void (*update_mpcc)(
145 		struct dc *dc,
146 		struct pipe_ctx *pipe_ctx);
147 
148 	void (*update_pending_status)(
149 			struct pipe_ctx *pipe_ctx);
150 
151 	bool (*set_input_transfer_func)(struct dc *dc,
152 				struct pipe_ctx *pipe_ctx,
153 				const struct dc_plane_state *plane_state);
154 
155 	bool (*set_output_transfer_func)(struct dc *dc,
156 				struct pipe_ctx *pipe_ctx,
157 				const struct dc_stream_state *stream);
158 
159 	void (*power_down)(struct dc *dc);
160 
161 	void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
162 
163 	void (*enable_timing_synchronization)(
164 			struct dc *dc,
165 			int group_index,
166 			int group_size,
167 			struct pipe_ctx *grouped_pipes[]);
168 
169 	void (*enable_per_frame_crtc_position_reset)(
170 			struct dc *dc,
171 			int group_size,
172 			struct pipe_ctx *grouped_pipes[]);
173 
174 	void (*enable_display_pipe_clock_gating)(
175 					struct dc_context *ctx,
176 					bool clock_gating);
177 
178 	bool (*enable_display_power_gating)(
179 					struct dc *dc,
180 					uint8_t controller_id,
181 					struct dc_bios *dcb,
182 					enum pipe_gating_control power_gating);
183 
184 	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
185 
186 	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
187 
188 	void (*send_immediate_sdp_message)(
189 				struct pipe_ctx *pipe_ctx,
190 				const uint8_t *custom_sdp_message,
191 				unsigned int sdp_message_size);
192 
193 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
194 
195 	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
196 
197 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
198 			struct dc_link_settings *link_settings);
199 
200 	void (*blank_stream)(struct pipe_ctx *pipe_ctx);
201 
202 	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
203 
204 	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
205 
206 	void (*pipe_control_lock)(
207 				struct dc *dc,
208 				struct pipe_ctx *pipe,
209 				bool lock);
210 
211 	void (*pipe_control_lock_global)(
212 				struct dc *dc,
213 				struct pipe_ctx *pipe,
214 				bool lock);
215 	void (*blank_pixel_data)(
216 			struct dc *dc,
217 			struct pipe_ctx *pipe_ctx,
218 			bool blank);
219 
220 	void (*prepare_bandwidth)(
221 			struct dc *dc,
222 			struct dc_state *context);
223 	void (*optimize_bandwidth)(
224 			struct dc *dc,
225 			struct dc_state *context);
226 
227 	void (*exit_optimized_pwr_state)(
228 			const struct dc *dc,
229 			struct dc_state *context);
230 	void (*optimize_pwr_state)(
231 			const struct dc *dc,
232 			struct dc_state *context);
233 
234 	bool (*update_bandwidth)(
235 			struct dc *dc,
236 			struct dc_state *context);
237 	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
238 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
239 
240 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
241 			unsigned int vmin, unsigned int vmax,
242 			unsigned int vmid, unsigned int vmid_frame_number);
243 
244 	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
245 			struct crtc_position *position);
246 
247 	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
248 			int num_pipes, const struct dc_static_screen_events *events);
249 
250 	enum dc_status (*enable_stream_timing)(
251 			struct pipe_ctx *pipe_ctx,
252 			struct dc_state *context,
253 			struct dc *dc);
254 
255 	void (*setup_stereo)(
256 			struct pipe_ctx *pipe_ctx,
257 			struct dc *dc);
258 
259 	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
260 
261 	void (*log_hw_state)(struct dc *dc,
262 		struct dc_log_buffer_ctx *log_ctx);
263 	void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
264 	void (*clear_status_bits)(struct dc *dc, unsigned int mask);
265 
266 	void (*wait_for_mpcc_disconnect)(struct dc *dc,
267 			struct resource_pool *res_pool,
268 			struct pipe_ctx *pipe_ctx);
269 
270 	void (*edp_power_control)(
271 			struct dc_link *link,
272 			bool enable);
273 	void (*edp_backlight_control)(
274 			struct dc_link *link,
275 			bool enable);
276 	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
277 
278 	void (*set_cursor_position)(struct pipe_ctx *pipe);
279 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
280 	void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
281 
282 	void (*setup_periodic_interrupt)(struct dc *dc,
283 			struct pipe_ctx *pipe_ctx,
284 			enum vline_select vline);
285 	void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx);
286 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
287 
288 	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
289 	void (*disable_vga)(struct dce_hwseq *hws);
290 	void (*bios_golden_init)(struct dc *dc);
291 	void (*plane_atomic_power_down)(struct dc *dc,
292 			struct dpp *dpp,
293 			struct hubp *hubp);
294 
295 	void (*plane_atomic_disable)(
296 			struct dc *dc, struct pipe_ctx *pipe_ctx);
297 
298 	void (*enable_power_gating_plane)(
299 		struct dce_hwseq *hws,
300 		bool enable);
301 
302 	void (*dpp_pg_control)(
303 			struct dce_hwseq *hws,
304 			unsigned int dpp_inst,
305 			bool power_on);
306 
307 	void (*hubp_pg_control)(
308 			struct dce_hwseq *hws,
309 			unsigned int hubp_inst,
310 			bool power_on);
311 
312 	void (*dsc_pg_control)(
313 			struct dce_hwseq *hws,
314 			unsigned int dsc_inst,
315 			bool power_on);
316 
317 
318 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
319 	void (*program_all_writeback_pipes_in_tree)(
320 			struct dc *dc,
321 			const struct dc_stream_state *stream,
322 			struct dc_state *context);
323 	void (*update_writeback)(struct dc *dc,
324 			const struct dc_stream_status *stream_status,
325 			struct dc_writeback_info *wb_info,
326 			struct dc_state *context);
327 	void (*enable_writeback)(struct dc *dc,
328 			const struct dc_stream_status *stream_status,
329 			struct dc_writeback_info *wb_info,
330 			struct dc_state *context);
331 	void (*disable_writeback)(struct dc *dc,
332 			unsigned int dwb_pipe_inst);
333 	enum dc_status (*set_clock)(struct dc *dc,
334 			enum dc_clock_type clock_type,
335 			uint32_t clk_khz,
336 			uint32_t stepping);
337 
338 	void (*get_clock)(struct dc *dc,
339 			enum dc_clock_type clock_type,
340 			struct dc_clock_config *clock_cfg);
341 
342 	bool (*s0i3_golden_init_wa)(struct dc *dc);
343 
344 	void (*get_surface_visual_confirm_color)(
345 			const struct pipe_ctx *pipe_ctx,
346 			struct tg_color *color);
347 
348 	void (*get_hdr_visual_confirm_color)(
349 			struct pipe_ctx *pipe_ctx,
350 			struct tg_color *color);
351 
352 	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
353 
354 	void (*verify_allow_pstate_change_high)(struct dc *dc);
355 
356 	void (*program_pipe)(
357 			struct dc *dc,
358 			struct pipe_ctx *pipe_ctx,
359 			struct dc_state *context);
360 
361 	bool (*wait_for_blank_complete)(
362 			struct output_pixel_processor *opp);
363 
364 	void (*dccg_init)(struct dce_hwseq *hws);
365 
366 	bool (*set_blend_lut)(
367 		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
368 
369 	bool (*set_shaper_3dlut)(
370 		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
371 
372 	int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
373 };
374 
375 void color_space_to_black_color(
376 	const struct dc *dc,
377 	enum dc_color_space colorspace,
378 	struct tg_color *black_color);
379 
380 bool hwss_wait_for_blank_complete(
381 		struct timing_generator *tg);
382 
383 const uint16_t *find_color_matrix(
384 		enum dc_color_space color_space,
385 		uint32_t *array_size);
386 
387 #endif /* __DC_HW_SEQUENCER_H__ */
388