1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 enum pipe_gating_control { 36 PIPE_GATING_CONTROL_DISABLE = 0, 37 PIPE_GATING_CONTROL_ENABLE, 38 PIPE_GATING_CONTROL_INIT 39 }; 40 41 enum vline_select { 42 VLINE0, 43 VLINE1 44 }; 45 46 struct dce_hwseq_wa { 47 bool blnd_crtc_trigger; 48 bool DEGVIDCN10_253; 49 bool false_optc_underflow; 50 bool DEGVIDCN10_254; 51 bool DEGVIDCN21; 52 }; 53 54 struct hwseq_wa_state { 55 bool DEGVIDCN10_253_applied; 56 }; 57 58 struct dce_hwseq { 59 struct dc_context *ctx; 60 const struct dce_hwseq_registers *regs; 61 const struct dce_hwseq_shift *shifts; 62 const struct dce_hwseq_mask *masks; 63 struct dce_hwseq_wa wa; 64 struct hwseq_wa_state wa_state; 65 }; 66 67 struct pipe_ctx; 68 struct dc_state; 69 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 70 struct dc_stream_status; 71 struct dc_writeback_info; 72 #endif 73 struct dchub_init_data; 74 struct dc_static_screen_events; 75 struct resource_pool; 76 struct resource_context; 77 struct stream_resource; 78 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 79 struct dc_phy_addr_space_config; 80 struct dc_virtual_addr_space_config; 81 #endif 82 struct hubp; 83 struct dpp; 84 85 struct hw_sequencer_funcs { 86 87 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 88 89 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 90 91 void (*init_hw)(struct dc *dc); 92 93 void (*init_pipes)(struct dc *dc, struct dc_state *context); 94 95 enum dc_status (*apply_ctx_to_hw)( 96 struct dc *dc, struct dc_state *context); 97 98 void (*reset_hw_ctx_wrap)( 99 struct dc *dc, struct dc_state *context); 100 101 void (*apply_ctx_for_surface)( 102 struct dc *dc, 103 const struct dc_stream_state *stream, 104 int num_planes, 105 struct dc_state *context); 106 107 void (*program_gamut_remap)( 108 struct pipe_ctx *pipe_ctx); 109 110 void (*program_output_csc)(struct dc *dc, 111 struct pipe_ctx *pipe_ctx, 112 enum dc_color_space colorspace, 113 uint16_t *matrix, 114 int opp_id); 115 116 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 117 void (*program_front_end_for_ctx)( 118 struct dc *dc, 119 struct dc_state *context); 120 void (*program_triplebuffer)( 121 const struct dc *dc, 122 struct pipe_ctx *pipe_ctx, 123 bool enableTripleBuffer); 124 void (*set_flip_control_gsl)( 125 struct pipe_ctx *pipe_ctx, 126 bool flip_immediate); 127 #endif 128 129 void (*update_plane_addr)( 130 const struct dc *dc, 131 struct pipe_ctx *pipe_ctx); 132 133 void (*plane_atomic_disconnect)( 134 struct dc *dc, 135 struct pipe_ctx *pipe_ctx); 136 137 void (*update_dchub)( 138 struct dce_hwseq *hws, 139 struct dchub_init_data *dh_data); 140 141 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 142 int (*init_sys_ctx)( 143 struct dce_hwseq *hws, 144 struct dc *dc, 145 struct dc_phy_addr_space_config *pa_config); 146 void (*init_vm_ctx)( 147 struct dce_hwseq *hws, 148 struct dc *dc, 149 struct dc_virtual_addr_space_config *va_config, 150 int vmid); 151 #endif 152 void (*update_mpcc)( 153 struct dc *dc, 154 struct pipe_ctx *pipe_ctx); 155 156 void (*update_pending_status)( 157 struct pipe_ctx *pipe_ctx); 158 159 bool (*set_input_transfer_func)( 160 struct pipe_ctx *pipe_ctx, 161 const struct dc_plane_state *plane_state); 162 163 bool (*set_output_transfer_func)( 164 struct pipe_ctx *pipe_ctx, 165 const struct dc_stream_state *stream); 166 167 void (*power_down)(struct dc *dc); 168 169 void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context); 170 171 void (*enable_timing_synchronization)( 172 struct dc *dc, 173 int group_index, 174 int group_size, 175 struct pipe_ctx *grouped_pipes[]); 176 177 void (*enable_per_frame_crtc_position_reset)( 178 struct dc *dc, 179 int group_size, 180 struct pipe_ctx *grouped_pipes[]); 181 182 void (*enable_display_pipe_clock_gating)( 183 struct dc_context *ctx, 184 bool clock_gating); 185 186 bool (*enable_display_power_gating)( 187 struct dc *dc, 188 uint8_t controller_id, 189 struct dc_bios *dcb, 190 enum pipe_gating_control power_gating); 191 192 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 193 194 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 195 196 void (*send_immediate_sdp_message)( 197 struct pipe_ctx *pipe_ctx, 198 const uint8_t *custom_sdp_message, 199 unsigned int sdp_message_size); 200 201 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 202 203 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 204 205 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 206 struct dc_link_settings *link_settings); 207 208 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 209 210 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 211 212 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 213 214 void (*pipe_control_lock)( 215 struct dc *dc, 216 struct pipe_ctx *pipe, 217 bool lock); 218 219 void (*pipe_control_lock_global)( 220 struct dc *dc, 221 struct pipe_ctx *pipe, 222 bool lock); 223 void (*blank_pixel_data)( 224 struct dc *dc, 225 struct pipe_ctx *pipe_ctx, 226 bool blank); 227 228 void (*prepare_bandwidth)( 229 struct dc *dc, 230 struct dc_state *context); 231 void (*optimize_bandwidth)( 232 struct dc *dc, 233 struct dc_state *context); 234 235 void (*exit_optimized_pwr_state)( 236 const struct dc *dc, 237 struct dc_state *context); 238 void (*optimize_pwr_state)( 239 const struct dc *dc, 240 struct dc_state *context); 241 242 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 243 bool (*update_bandwidth)( 244 struct dc *dc, 245 struct dc_state *context); 246 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 247 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 248 #endif 249 250 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 251 unsigned int vmin, unsigned int vmax, 252 unsigned int vmid, unsigned int vmid_frame_number); 253 254 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 255 struct crtc_position *position); 256 257 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 258 int num_pipes, const struct dc_static_screen_events *events); 259 260 enum dc_status (*enable_stream_timing)( 261 struct pipe_ctx *pipe_ctx, 262 struct dc_state *context, 263 struct dc *dc); 264 265 void (*setup_stereo)( 266 struct pipe_ctx *pipe_ctx, 267 struct dc *dc); 268 269 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 270 271 void (*log_hw_state)(struct dc *dc, 272 struct dc_log_buffer_ctx *log_ctx); 273 void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask); 274 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 275 276 void (*wait_for_mpcc_disconnect)(struct dc *dc, 277 struct resource_pool *res_pool, 278 struct pipe_ctx *pipe_ctx); 279 280 void (*edp_power_control)( 281 struct dc_link *link, 282 bool enable); 283 void (*edp_backlight_control)( 284 struct dc_link *link, 285 bool enable); 286 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 287 288 void (*set_cursor_position)(struct pipe_ctx *pipe); 289 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 290 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 291 292 void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline); 293 void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx); 294 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); 295 296 void (*init_blank)(struct dc *dc, struct timing_generator *tg); 297 void (*disable_vga)(struct dce_hwseq *hws); 298 void (*bios_golden_init)(struct dc *dc); 299 void (*plane_atomic_power_down)(struct dc *dc, 300 struct dpp *dpp, 301 struct hubp *hubp); 302 303 void (*plane_atomic_disable)( 304 struct dc *dc, struct pipe_ctx *pipe_ctx); 305 306 void (*enable_power_gating_plane)( 307 struct dce_hwseq *hws, 308 bool enable); 309 310 void (*dpp_pg_control)( 311 struct dce_hwseq *hws, 312 unsigned int dpp_inst, 313 bool power_on); 314 315 void (*hubp_pg_control)( 316 struct dce_hwseq *hws, 317 unsigned int hubp_inst, 318 bool power_on); 319 320 void (*dsc_pg_control)( 321 struct dce_hwseq *hws, 322 unsigned int dsc_inst, 323 bool power_on); 324 325 326 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 327 void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 328 void (*program_all_writeback_pipes_in_tree)( 329 struct dc *dc, 330 const struct dc_stream_state *stream, 331 struct dc_state *context); 332 void (*update_writeback)(struct dc *dc, 333 const struct dc_stream_status *stream_status, 334 struct dc_writeback_info *wb_info, 335 struct dc_state *context); 336 void (*enable_writeback)(struct dc *dc, 337 const struct dc_stream_status *stream_status, 338 struct dc_writeback_info *wb_info, 339 struct dc_state *context); 340 void (*disable_writeback)(struct dc *dc, 341 unsigned int dwb_pipe_inst); 342 #endif 343 enum dc_status (*set_clock)(struct dc *dc, 344 enum dc_clock_type clock_type, 345 uint32_t clk_khz, 346 uint32_t stepping); 347 348 void (*get_clock)(struct dc *dc, 349 enum dc_clock_type clock_type, 350 struct dc_clock_config *clock_cfg); 351 352 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 353 bool (*s0i3_golden_init_wa)(struct dc *dc); 354 #endif 355 }; 356 357 void color_space_to_black_color( 358 const struct dc *dc, 359 enum dc_color_space colorspace, 360 struct tg_color *black_color); 361 362 bool hwss_wait_for_blank_complete( 363 struct timing_generator *tg); 364 365 const uint16_t *find_color_matrix( 366 enum dc_color_space color_space, 367 uint32_t *array_size); 368 369 #endif /* __DC_HW_SEQUENCER_H__ */ 370