1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
27 #define __DAL_TIMING_GENERATOR_TYPES_H__
28 
29 #include "hw_shared.h"
30 
31 struct dc_bios;
32 
33 /* Contains CRTC vertical/horizontal pixel counters */
34 struct crtc_position {
35 	int32_t vertical_count;
36 	int32_t horizontal_count;
37 	int32_t nominal_vcount;
38 };
39 
40 struct dcp_gsl_params {
41 	int gsl_group;
42 	int gsl_master;
43 };
44 
45 struct gsl_params {
46 	int gsl0_en;
47 	int gsl1_en;
48 	int gsl2_en;
49 	int gsl_master_en;
50 	int gsl_master_mode;
51 	int master_update_lock_gsl_en;
52 	int gsl_window_start_x;
53 	int gsl_window_end_x;
54 	int gsl_window_start_y;
55 	int gsl_window_end_y;
56 };
57 
58 /* define the structure of Dynamic Refresh Mode */
59 struct drr_params {
60 	uint32_t vertical_total_min;
61 	uint32_t vertical_total_max;
62 	uint32_t vertical_total_mid;
63 	uint32_t vertical_total_mid_frame_num;
64 	bool immediate_flip;
65 };
66 
67 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
68 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
69 
70 enum crtc_state {
71 	CRTC_STATE_VBLANK = 0,
72 	CRTC_STATE_VACTIVE
73 };
74 
75 struct vupdate_keepout_params {
76 	int start_offset;
77 	int end_offset;
78 	int enable;
79 };
80 
81 struct crtc_stereo_flags {
82 	uint8_t PROGRAM_STEREO         : 1;
83 	uint8_t PROGRAM_POLARITY       : 1;
84 	uint8_t RIGHT_EYE_POLARITY     : 1;
85 	uint8_t FRAME_PACKED           : 1;
86 	uint8_t DISABLE_STEREO_DP_SYNC : 1;
87 };
88 
89 enum crc_selection {
90 	/* Order must match values expected by hardware */
91 	UNION_WINDOW_A_B = 0,
92 	UNION_WINDOW_A_NOT_B,
93 	UNION_WINDOW_NOT_A_B,
94 	UNION_WINDOW_NOT_A_NOT_B,
95 	INTERSECT_WINDOW_A_B,
96 	INTERSECT_WINDOW_A_NOT_B,
97 	INTERSECT_WINDOW_NOT_A_B,
98 	INTERSECT_WINDOW_NOT_A_NOT_B,
99 };
100 
101 enum otg_out_mux_dest {
102 	OUT_MUX_DIO = 0,
103 	OUT_MUX_HPO_DP = 2,
104 };
105 
106 enum h_timing_div_mode {
107 	H_TIMING_NO_DIV,
108 	H_TIMING_DIV_BY2,
109 	H_TIMING_RESERVED,
110 	H_TIMING_DIV_BY4,
111 };
112 
113 enum timing_synchronization_type {
114 	NOT_SYNCHRONIZABLE,
115 	TIMING_SYNCHRONIZABLE,
116 	VBLANK_SYNCHRONIZABLE
117 };
118 
119 struct crc_params {
120 	/* Regions used to calculate CRC*/
121 	uint16_t windowa_x_start;
122 	uint16_t windowa_x_end;
123 	uint16_t windowa_y_start;
124 	uint16_t windowa_y_end;
125 
126 	uint16_t windowb_x_start;
127 	uint16_t windowb_x_end;
128 	uint16_t windowb_y_start;
129 	uint16_t windowb_y_end;
130 
131 	enum crc_selection selection;
132 
133 	uint8_t dsc_mode;
134 	uint8_t odm_mode;
135 
136 	bool continuous_mode;
137 	bool enable;
138 };
139 
140 struct timing_generator {
141 	const struct timing_generator_funcs *funcs;
142 	struct dc_bios *bp;
143 	struct dc_context *ctx;
144 	int inst;
145 };
146 
147 struct dc_crtc_timing;
148 
149 struct drr_params;
150 
151 
152 struct timing_generator_funcs {
153 	bool (*validate_timing)(struct timing_generator *tg,
154 							const struct dc_crtc_timing *timing);
155 	void (*program_timing)(struct timing_generator *tg,
156 							const struct dc_crtc_timing *timing,
157 							int vready_offset,
158 							int vstartup_start,
159 							int vupdate_offset,
160 							int vupdate_width,
161 							const enum signal_type signal,
162 							bool use_vbios
163 	);
164 	void (*setup_vertical_interrupt0)(
165 			struct timing_generator *optc,
166 			uint32_t start_line,
167 			uint32_t end_line);
168 	void (*setup_vertical_interrupt1)(
169 			struct timing_generator *optc,
170 			uint32_t start_line);
171 	void (*setup_vertical_interrupt2)(
172 			struct timing_generator *optc,
173 			uint32_t start_line);
174 
175 	bool (*enable_crtc)(struct timing_generator *tg);
176 	bool (*disable_crtc)(struct timing_generator *tg);
177 	bool (*immediate_disable_crtc)(struct timing_generator *tg);
178 	bool (*is_counter_moving)(struct timing_generator *tg);
179 	void (*get_position)(struct timing_generator *tg,
180 				struct crtc_position *position);
181 
182 	uint32_t (*get_frame_count)(struct timing_generator *tg);
183 	void (*get_scanoutpos)(
184 		struct timing_generator *tg,
185 		uint32_t *v_blank_start,
186 		uint32_t *v_blank_end,
187 		uint32_t *h_position,
188 		uint32_t *v_position);
189 	bool (*get_otg_active_size)(struct timing_generator *optc,
190 			uint32_t *otg_active_width,
191 			uint32_t *otg_active_height);
192 	bool (*is_matching_timing)(struct timing_generator *tg,
193 			const struct dc_crtc_timing *otg_timing);
194 	void (*set_early_control)(struct timing_generator *tg,
195 							   uint32_t early_cntl);
196 	void (*wait_for_state)(struct timing_generator *tg,
197 							enum crtc_state state);
198 	void (*set_blank)(struct timing_generator *tg,
199 					bool enable_blanking);
200 	bool (*is_blanked)(struct timing_generator *tg);
201 	bool (*is_locked)(struct timing_generator *tg);
202 	void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
203 	void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
204 	void (*set_colors)(struct timing_generator *tg,
205 						const struct tg_color *blank_color,
206 						const struct tg_color *overscan_color);
207 
208 	void (*disable_vga)(struct timing_generator *tg);
209 	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
210 	void (*setup_global_swap_lock)(struct timing_generator *tg,
211 							const struct dcp_gsl_params *gsl_params);
212 	void (*unlock)(struct timing_generator *tg);
213 	void (*lock)(struct timing_generator *tg);
214 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
215 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
216 	void(*triplebuffer_unlock)(struct timing_generator *tg);
217 	void(*triplebuffer_lock)(struct timing_generator *tg);
218 	void (*enable_reset_trigger)(struct timing_generator *tg,
219 				     int source_tg_inst);
220 	void (*enable_crtc_reset)(struct timing_generator *tg,
221 				  int source_tg_inst,
222 				  struct crtc_trigger_info *crtc_tp);
223 	void (*disable_reset_trigger)(struct timing_generator *tg);
224 	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
225 	void (*enable_advanced_request)(struct timing_generator *tg,
226 					bool enable, const struct dc_crtc_timing *timing);
227 	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
228 	void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
229 	void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
230 	void (*set_static_screen_control)(struct timing_generator *tg,
231 						uint32_t event_triggers,
232 						uint32_t num_frames);
233 	void (*set_test_pattern)(
234 		struct timing_generator *tg,
235 		enum controller_dp_test_pattern test_pattern,
236 		enum dc_color_depth color_depth);
237 
238 	bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
239 
240 	void (*program_global_sync)(struct timing_generator *tg,
241 			int vready_offset,
242 			int vstartup_start,
243 			int vupdate_offset,
244 			int vupdate_width);
245 	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
246 	void (*program_stereo)(struct timing_generator *tg,
247 		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
248 	bool (*is_stereo_left_eye)(struct timing_generator *tg);
249 
250 	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
251 
252 	void (*tg_init)(struct timing_generator *tg);
253 	bool (*is_tg_enabled)(struct timing_generator *tg);
254 	bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
255 	void (*clear_optc_underflow)(struct timing_generator *tg);
256 
257 	void (*set_dwb_source)(struct timing_generator *optc,
258 		uint32_t dwb_pipe_inst);
259 
260 	void (*get_optc_source)(struct timing_generator *optc,
261 			uint32_t *num_of_input_segments,
262 			uint32_t *seg0_src_sel,
263 			uint32_t *seg1_src_sel);
264 
265 	/**
266 	 * Configure CRCs for the given timing generator. Return false if TG is
267 	 * not on.
268 	 */
269 	bool (*configure_crc)(struct timing_generator *tg,
270 			       const struct crc_params *params);
271 
272 	/**
273 	 * Get CRCs for the given timing generator. Return false if CRCs are
274 	 * not enabled (via configure_crc).
275 	 */
276 	bool (*get_crc)(struct timing_generator *tg,
277 			uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
278 
279 	void (*program_manual_trigger)(struct timing_generator *optc);
280 	void (*setup_manual_trigger)(struct timing_generator *optc);
281 	bool (*get_hw_timing)(struct timing_generator *optc,
282 			struct dc_crtc_timing *hw_crtc_timing);
283 
284 	void (*set_vtg_params)(struct timing_generator *optc,
285 			const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
286 
287 	void (*set_dsc_config)(struct timing_generator *optc,
288 			       enum optc_dsc_mode dsc_mode,
289 			       uint32_t dsc_bytes_per_pixel,
290 			       uint32_t dsc_slice_width);
291 	void (*get_dsc_status)(struct timing_generator *optc,
292 					uint32_t *dsc_mode);
293 	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
294 	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
295 			struct dc_crtc_timing *timing);
296 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
297 	void (*set_gsl_source_select)(struct timing_generator *optc,
298 			int group_idx,
299 			uint32_t gsl_ready_signal);
300 	void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
301 	void (*set_vrr_m_const)(struct timing_generator *optc,
302 			double vtotal_avg);
303 	void (*set_drr_trigger_window)(struct timing_generator *optc,
304 			uint32_t window_start, uint32_t window_end);
305 	void (*set_vtotal_change_limit)(struct timing_generator *optc,
306 			uint32_t limit);
307 	void (*align_vblanks)(struct timing_generator *master_optc,
308 			struct timing_generator *slave_optc,
309 			uint32_t master_pixel_clock_100Hz,
310 			uint32_t slave_pixel_clock_100Hz,
311 			uint8_t master_clock_divider,
312 			uint8_t slave_clock_divider);
313 
314 	void (*init_odm)(struct timing_generator *tg);
315 };
316 
317 #endif
318