1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__ 27 #define __DAL_TIMING_GENERATOR_TYPES_H__ 28 29 #include "hw_shared.h" 30 31 struct dc_bios; 32 33 /* Contains CRTC vertical/horizontal pixel counters */ 34 struct crtc_position { 35 int32_t vertical_count; 36 int32_t horizontal_count; 37 int32_t nominal_vcount; 38 }; 39 40 struct dcp_gsl_params { 41 int gsl_group; 42 int gsl_master; 43 }; 44 45 struct gsl_params { 46 int gsl0_en; 47 int gsl1_en; 48 int gsl2_en; 49 int gsl_master_en; 50 int gsl_master_mode; 51 int master_update_lock_gsl_en; 52 int gsl_window_start_x; 53 int gsl_window_end_x; 54 int gsl_window_start_y; 55 int gsl_window_end_y; 56 }; 57 58 /* define the structure of Dynamic Refresh Mode */ 59 struct drr_params { 60 uint32_t vertical_total_min; 61 uint32_t vertical_total_max; 62 uint32_t vertical_total_mid; 63 uint32_t vertical_total_mid_frame_num; 64 bool immediate_flip; 65 }; 66 67 #define LEFT_EYE_3D_PRIMARY_SURFACE 1 68 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0 69 70 enum crtc_state { 71 CRTC_STATE_VBLANK = 0, 72 CRTC_STATE_VACTIVE 73 }; 74 75 struct vupdate_keepout_params { 76 int start_offset; 77 int end_offset; 78 int enable; 79 }; 80 81 struct crtc_stereo_flags { 82 uint8_t PROGRAM_STEREO : 1; 83 uint8_t PROGRAM_POLARITY : 1; 84 uint8_t RIGHT_EYE_POLARITY : 1; 85 uint8_t FRAME_PACKED : 1; 86 uint8_t DISABLE_STEREO_DP_SYNC : 1; 87 }; 88 89 enum crc_selection { 90 /* Order must match values expected by hardware */ 91 UNION_WINDOW_A_B = 0, 92 UNION_WINDOW_A_NOT_B, 93 UNION_WINDOW_NOT_A_B, 94 UNION_WINDOW_NOT_A_NOT_B, 95 INTERSECT_WINDOW_A_B, 96 INTERSECT_WINDOW_A_NOT_B, 97 INTERSECT_WINDOW_NOT_A_B, 98 INTERSECT_WINDOW_NOT_A_NOT_B, 99 }; 100 101 enum otg_out_mux_dest { 102 OUT_MUX_DIO = 0, 103 }; 104 105 enum h_timing_div_mode { 106 H_TIMING_NO_DIV, 107 H_TIMING_DIV_BY2, 108 H_TIMING_RESERVED, 109 H_TIMING_DIV_BY4, 110 }; 111 112 enum timing_synchronization_type { 113 NOT_SYNCHRONIZABLE, 114 TIMING_SYNCHRONIZABLE, 115 VBLANK_SYNCHRONIZABLE 116 }; 117 118 struct crc_params { 119 /* Regions used to calculate CRC*/ 120 uint16_t windowa_x_start; 121 uint16_t windowa_x_end; 122 uint16_t windowa_y_start; 123 uint16_t windowa_y_end; 124 125 uint16_t windowb_x_start; 126 uint16_t windowb_x_end; 127 uint16_t windowb_y_start; 128 uint16_t windowb_y_end; 129 130 enum crc_selection selection; 131 132 uint8_t dsc_mode; 133 uint8_t odm_mode; 134 135 bool continuous_mode; 136 bool enable; 137 }; 138 139 struct timing_generator { 140 const struct timing_generator_funcs *funcs; 141 struct dc_bios *bp; 142 struct dc_context *ctx; 143 int inst; 144 }; 145 146 struct dc_crtc_timing; 147 148 struct drr_params; 149 150 151 struct timing_generator_funcs { 152 bool (*validate_timing)(struct timing_generator *tg, 153 const struct dc_crtc_timing *timing); 154 void (*program_timing)(struct timing_generator *tg, 155 const struct dc_crtc_timing *timing, 156 int vready_offset, 157 int vstartup_start, 158 int vupdate_offset, 159 int vupdate_width, 160 const enum signal_type signal, 161 bool use_vbios 162 ); 163 void (*setup_vertical_interrupt0)( 164 struct timing_generator *optc, 165 uint32_t start_line, 166 uint32_t end_line); 167 void (*setup_vertical_interrupt1)( 168 struct timing_generator *optc, 169 uint32_t start_line); 170 void (*setup_vertical_interrupt2)( 171 struct timing_generator *optc, 172 uint32_t start_line); 173 174 bool (*enable_crtc)(struct timing_generator *tg); 175 bool (*disable_crtc)(struct timing_generator *tg); 176 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 177 bool (*immediate_disable_crtc)(struct timing_generator *tg); 178 #endif 179 bool (*is_counter_moving)(struct timing_generator *tg); 180 void (*get_position)(struct timing_generator *tg, 181 struct crtc_position *position); 182 183 uint32_t (*get_frame_count)(struct timing_generator *tg); 184 void (*get_scanoutpos)( 185 struct timing_generator *tg, 186 uint32_t *v_blank_start, 187 uint32_t *v_blank_end, 188 uint32_t *h_position, 189 uint32_t *v_position); 190 bool (*get_otg_active_size)(struct timing_generator *optc, 191 uint32_t *otg_active_width, 192 uint32_t *otg_active_height); 193 bool (*is_matching_timing)(struct timing_generator *tg, 194 const struct dc_crtc_timing *otg_timing); 195 void (*set_early_control)(struct timing_generator *tg, 196 uint32_t early_cntl); 197 void (*wait_for_state)(struct timing_generator *tg, 198 enum crtc_state state); 199 void (*set_blank)(struct timing_generator *tg, 200 bool enable_blanking); 201 bool (*is_blanked)(struct timing_generator *tg); 202 bool (*is_locked)(struct timing_generator *tg); 203 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); 204 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); 205 void (*set_colors)(struct timing_generator *tg, 206 const struct tg_color *blank_color, 207 const struct tg_color *overscan_color); 208 209 void (*disable_vga)(struct timing_generator *tg); 210 bool (*did_triggered_reset_occur)(struct timing_generator *tg); 211 void (*setup_global_swap_lock)(struct timing_generator *tg, 212 const struct dcp_gsl_params *gsl_params); 213 void (*unlock)(struct timing_generator *tg); 214 void (*lock)(struct timing_generator *tg); 215 void (*lock_doublebuffer_disable)(struct timing_generator *tg); 216 void (*lock_doublebuffer_enable)(struct timing_generator *tg); 217 void(*triplebuffer_unlock)(struct timing_generator *tg); 218 void(*triplebuffer_lock)(struct timing_generator *tg); 219 void (*enable_reset_trigger)(struct timing_generator *tg, 220 int source_tg_inst); 221 void (*enable_crtc_reset)(struct timing_generator *tg, 222 int source_tg_inst, 223 struct crtc_trigger_info *crtc_tp); 224 void (*disable_reset_trigger)(struct timing_generator *tg); 225 void (*tear_down_global_swap_lock)(struct timing_generator *tg); 226 void (*enable_advanced_request)(struct timing_generator *tg, 227 bool enable, const struct dc_crtc_timing *timing); 228 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); 229 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); 230 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); 231 void (*set_static_screen_control)(struct timing_generator *tg, 232 uint32_t event_triggers, 233 uint32_t num_frames); 234 void (*set_test_pattern)( 235 struct timing_generator *tg, 236 enum controller_dp_test_pattern test_pattern, 237 enum dc_color_depth color_depth); 238 239 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); 240 241 void (*program_global_sync)(struct timing_generator *tg, 242 int vready_offset, 243 int vstartup_start, 244 int vupdate_offset, 245 int vupdate_width); 246 void (*enable_optc_clock)(struct timing_generator *tg, bool enable); 247 void (*program_stereo)(struct timing_generator *tg, 248 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 249 bool (*is_stereo_left_eye)(struct timing_generator *tg); 250 251 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); 252 253 void (*tg_init)(struct timing_generator *tg); 254 bool (*is_tg_enabled)(struct timing_generator *tg); 255 bool (*is_optc_underflow_occurred)(struct timing_generator *tg); 256 void (*clear_optc_underflow)(struct timing_generator *tg); 257 258 void (*set_dwb_source)(struct timing_generator *optc, 259 uint32_t dwb_pipe_inst); 260 261 void (*get_optc_source)(struct timing_generator *optc, 262 uint32_t *num_of_input_segments, 263 uint32_t *seg0_src_sel, 264 uint32_t *seg1_src_sel); 265 266 /** 267 * Configure CRCs for the given timing generator. Return false if TG is 268 * not on. 269 */ 270 bool (*configure_crc)(struct timing_generator *tg, 271 const struct crc_params *params); 272 273 /** 274 * Get CRCs for the given timing generator. Return false if CRCs are 275 * not enabled (via configure_crc). 276 */ 277 bool (*get_crc)(struct timing_generator *tg, 278 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 279 280 void (*program_manual_trigger)(struct timing_generator *optc); 281 void (*setup_manual_trigger)(struct timing_generator *optc); 282 bool (*get_hw_timing)(struct timing_generator *optc, 283 struct dc_crtc_timing *hw_crtc_timing); 284 285 void (*set_vtg_params)(struct timing_generator *optc, 286 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 287 288 void (*set_dsc_config)(struct timing_generator *optc, 289 enum optc_dsc_mode dsc_mode, 290 uint32_t dsc_bytes_per_pixel, 291 uint32_t dsc_slice_width); 292 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); 293 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, 294 struct dc_crtc_timing *timing); 295 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); 296 void (*set_gsl_source_select)(struct timing_generator *optc, 297 int group_idx, 298 uint32_t gsl_ready_signal); 299 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); 300 void (*set_vrr_m_const)(struct timing_generator *optc, 301 double vtotal_avg); 302 void (*set_drr_trigger_window)(struct timing_generator *optc, 303 uint32_t window_start, uint32_t window_end); 304 void (*set_vtotal_change_limit)(struct timing_generator *optc, 305 uint32_t limit); 306 void (*align_vblanks)(struct timing_generator *master_optc, 307 struct timing_generator *slave_optc, 308 uint32_t master_pixel_clock_100Hz, 309 uint32_t slave_pixel_clock_100Hz, 310 uint8_t master_clock_divider, 311 uint8_t slave_clock_divider); 312 }; 313 314 #endif 315