xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h (revision 842ed298)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_OPP_H__
27 #define __DAL_OPP_H__
28 
29 #include "hw_shared.h"
30 #include "dc_hw_types.h"
31 #include "transform.h"
32 #include "mpc.h"
33 
34 struct fixed31_32;
35 
36 /* TODO: Need cleanup */
37 enum clamping_range {
38 	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
39 	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
40 	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
41 	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
42 	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
43 	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
44 };
45 
46 struct clamping_and_pixel_encoding_params {
47 	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
48 	enum clamping_range clamping_level; /* Clamping identifier */
49 	enum dc_color_depth c_depth; /* Deep color use. */
50 };
51 
52 struct bit_depth_reduction_params {
53 	struct {
54 		/* truncate/round */
55 		/* trunc/round enabled*/
56 		uint32_t TRUNCATE_ENABLED:1;
57 		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
58 		uint32_t TRUNCATE_DEPTH:2;
59 		/* truncate or round*/
60 		uint32_t TRUNCATE_MODE:1;
61 
62 		/* spatial dither */
63 		/* Spatial Bit Depth Reduction enabled*/
64 		uint32_t SPATIAL_DITHER_ENABLED:1;
65 		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
66 		uint32_t SPATIAL_DITHER_DEPTH:2;
67 		/* 0-3 to select patterns*/
68 		uint32_t SPATIAL_DITHER_MODE:2;
69 		/* Enable RGB random dithering*/
70 		uint32_t RGB_RANDOM:1;
71 		/* Enable Frame random dithering*/
72 		uint32_t FRAME_RANDOM:1;
73 		/* Enable HighPass random dithering*/
74 		uint32_t HIGHPASS_RANDOM:1;
75 
76 		/* temporal dither*/
77 		 /* frame modulation enabled*/
78 		uint32_t FRAME_MODULATION_ENABLED:1;
79 		/* same as for trunc/spatial*/
80 		uint32_t FRAME_MODULATION_DEPTH:2;
81 		/* 2/4 gray levels*/
82 		uint32_t TEMPORAL_LEVEL:1;
83 		uint32_t FRC25:2;
84 		uint32_t FRC50:2;
85 		uint32_t FRC75:2;
86 	} flags;
87 
88 	uint32_t r_seed_value;
89 	uint32_t b_seed_value;
90 	uint32_t g_seed_value;
91 	enum dc_pixel_encoding pixel_encoding;
92 };
93 
94 enum wide_gamut_regamma_mode {
95 	/*  0x0  - BITS2:0 Bypass */
96 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
97 	/*  0x1  - Fixed curve sRGB 2.4 */
98 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
99 	/*  0x2  - Fixed curve xvYCC 2.22 */
100 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
101 	/*  0x3  - Programmable control A */
102 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
103 	/*  0x4  - Programmable control B */
104 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
105 	/*  0x0  - BITS6:4 Bypass */
106 	WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
107 	/*  0x1  - Fixed curve sRGB 2.4 */
108 	WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
109 	/*  0x2  - Fixed curve xvYCC 2.22 */
110 	WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
111 	/*  0x3  - Programmable control A */
112 	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
113 	/*  0x4  - Programmable control B */
114 	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
115 };
116 
117 struct gamma_pixel {
118 	struct fixed31_32 r;
119 	struct fixed31_32 g;
120 	struct fixed31_32 b;
121 };
122 
123 enum channel_name {
124 	CHANNEL_NAME_RED,
125 	CHANNEL_NAME_GREEN,
126 	CHANNEL_NAME_BLUE
127 };
128 
129 struct custom_float_format {
130 	uint32_t mantissa_bits;
131 	uint32_t exponenta_bits;
132 	bool sign;
133 };
134 
135 struct custom_float_value {
136 	uint32_t mantissa;
137 	uint32_t exponenta;
138 	uint32_t value;
139 	bool negative;
140 };
141 
142 struct hw_x_point {
143 	uint32_t custom_float_x;
144 	struct fixed31_32 x;
145 	struct fixed31_32 regamma_y_red;
146 	struct fixed31_32 regamma_y_green;
147 	struct fixed31_32 regamma_y_blue;
148 
149 };
150 
151 struct pwl_float_data_ex {
152 	struct fixed31_32 r;
153 	struct fixed31_32 g;
154 	struct fixed31_32 b;
155 	struct fixed31_32 delta_r;
156 	struct fixed31_32 delta_g;
157 	struct fixed31_32 delta_b;
158 };
159 
160 enum hw_point_position {
161 	/* hw point sits between left and right sw points */
162 	HW_POINT_POSITION_MIDDLE,
163 	/* hw point lays left from left (smaller) sw point */
164 	HW_POINT_POSITION_LEFT,
165 	/* hw point lays stays from right (bigger) sw point */
166 	HW_POINT_POSITION_RIGHT
167 };
168 
169 struct gamma_point {
170 	int32_t left_index;
171 	int32_t right_index;
172 	enum hw_point_position pos;
173 	struct fixed31_32 coeff;
174 };
175 
176 struct pixel_gamma_point {
177 	struct gamma_point r;
178 	struct gamma_point g;
179 	struct gamma_point b;
180 };
181 
182 struct gamma_coefficients {
183 	struct fixed31_32 a0[3];
184 	struct fixed31_32 a1[3];
185 	struct fixed31_32 a2[3];
186 	struct fixed31_32 a3[3];
187 	struct fixed31_32 user_gamma[3];
188 	struct fixed31_32 user_contrast;
189 	struct fixed31_32 user_brightness;
190 };
191 
192 struct pwl_float_data {
193 	struct fixed31_32 r;
194 	struct fixed31_32 g;
195 	struct fixed31_32 b;
196 };
197 
198 struct mpc_tree_cfg {
199 	int num_pipes;
200 	int dpp[MAX_PIPES];
201 	int mpcc[MAX_PIPES];
202 };
203 
204 struct output_pixel_processor {
205 	struct dc_context *ctx;
206 	uint32_t inst;
207 	struct pwl_params regamma_params;
208 	struct mpc_tree mpc_tree_params;
209 	bool mpcc_disconnect_pending[MAX_PIPES];
210 	const struct opp_funcs *funcs;
211 	uint32_t dyn_expansion;
212 };
213 
214 enum fmt_stereo_action {
215 	FMT_STEREO_ACTION_ENABLE = 0,
216 	FMT_STEREO_ACTION_DISABLE,
217 	FMT_STEREO_ACTION_UPDATE_POLARITY
218 };
219 
220 struct opp_grph_csc_adjustment {
221 	//enum grph_color_adjust_option color_adjust_option;
222 	enum dc_color_space c_space;
223 	enum dc_color_depth color_depth; /* clean up to uint32_t */
224 	enum graphics_csc_adjust_type   csc_adjust_type;
225 	int32_t adjust_divider;
226 	int32_t grph_cont;
227 	int32_t grph_sat;
228 	int32_t grph_bright;
229 	int32_t grph_hue;
230 };
231 
232 /* Underlay related types */
233 
234 struct hw_adjustment_range {
235 	int32_t hw_default;
236 	int32_t min;
237 	int32_t max;
238 	int32_t step;
239 	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
240 };
241 
242 enum ovl_csc_adjust_item {
243 	OVERLAY_BRIGHTNESS = 0,
244 	OVERLAY_GAMMA,
245 	OVERLAY_CONTRAST,
246 	OVERLAY_SATURATION,
247 	OVERLAY_HUE,
248 	OVERLAY_ALPHA,
249 	OVERLAY_ALPHA_PER_PIX,
250 	OVERLAY_COLOR_TEMPERATURE
251 };
252 
253 enum oppbuf_display_segmentation {
254 	OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0,
255 	OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1,
256 	OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2,
257 	OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3,
258 	OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4
259 };
260 
261 struct oppbuf_params {
262 	uint32_t active_width;
263 	enum oppbuf_display_segmentation mso_segmentation;
264 	uint32_t mso_overlap_pixel_num;
265 	uint32_t pixel_repetition;
266 	uint32_t num_segment_padded_pixels;
267 };
268 
269 struct opp_funcs {
270 
271 
272 	/* FORMATTER RELATED */
273 
274 	void (*opp_program_fmt)(
275 			struct output_pixel_processor *opp,
276 			struct bit_depth_reduction_params *fmt_bit_depth,
277 			struct clamping_and_pixel_encoding_params *clamping);
278 
279 	void (*opp_set_dyn_expansion)(
280 		struct output_pixel_processor *opp,
281 		enum dc_color_space color_sp,
282 		enum dc_color_depth color_dpth,
283 		enum signal_type signal);
284 
285 	void (*opp_program_bit_depth_reduction)(
286 		struct output_pixel_processor *opp,
287 		const struct bit_depth_reduction_params *params);
288 
289 	/* underlay related */
290 	void (*opp_get_underlay_adjustment_range)(
291 			struct output_pixel_processor *opp,
292 			enum ovl_csc_adjust_item overlay_adjust_item,
293 			struct hw_adjustment_range *range);
294 
295 	void (*opp_destroy)(struct output_pixel_processor **opp);
296 
297 	void (*opp_program_stereo)(
298 		struct output_pixel_processor *opp,
299 		bool enable,
300 		const struct dc_crtc_timing *timing);
301 
302 	void (*opp_pipe_clock_control)(
303 			struct output_pixel_processor *opp,
304 			bool enable);
305 
306 	void (*opp_set_disp_pattern_generator)(
307 			struct output_pixel_processor *opp,
308 			enum controller_dp_test_pattern test_pattern,
309 			enum controller_dp_color_space color_space,
310 			enum dc_color_depth color_depth,
311 			const struct tg_color *solid_color,
312 			int width,
313 			int height,
314 			int offset);
315 
316 	void (*opp_program_dpg_dimensions)(
317 				struct output_pixel_processor *opp,
318 				int width,
319 				int height);
320 
321 	bool (*dpg_is_blanked)(
322 			struct output_pixel_processor *opp);
323 
324 	void (*opp_dpg_set_blank_color)(
325 			struct output_pixel_processor *opp,
326 			const struct tg_color *color);
327 
328 	void (*opp_program_left_edge_extra_pixel)(
329 			struct output_pixel_processor *opp,
330 			bool count);
331 
332 };
333 
334 #endif
335