xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h (revision 8795a739)
1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
2  *
3  * Permission is hereby granted, free of charge, to any person obtaining a
4  * copy of this software and associated documentation files (the "Software"),
5  * to deal in the Software without restriction, including without limitation
6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7  * and/or sell copies of the Software, and to permit persons to whom the
8  * Software is furnished to do so, subject to the following conditions:
9  *
10  * The above copyright notice and this permission notice shall be included in
11  * all copies or substantial portions of the Software.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19  * OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * Authors: AMD
22  *
23  */
24 
25 #ifndef __DC_MPCC_H__
26 #define __DC_MPCC_H__
27 
28 #include "dc_hw_types.h"
29 #include "hw_shared.h"
30 
31 #define MAX_MPCC 6
32 #define MAX_OPP 6
33 
34 #if   defined(CONFIG_DRM_AMD_DC_DCN2_0)
35 #define MAX_DWB		1
36 #endif
37 
38 enum mpc_output_csc_mode {
39 	MPC_OUTPUT_CSC_DISABLE = 0,
40 	MPC_OUTPUT_CSC_COEF_A,
41 	MPC_OUTPUT_CSC_COEF_B
42 };
43 
44 
45 enum mpcc_blend_mode {
46 	MPCC_BLEND_MODE_BYPASS,
47 	MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH,
48 	MPCC_BLEND_MODE_TOP_LAYER_ONLY,
49 	MPCC_BLEND_MODE_TOP_BOT_BLENDING
50 };
51 
52 enum mpcc_alpha_blend_mode {
53 	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA,
54 	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN,
55 	MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA
56 };
57 
58 /*
59  * MPCC blending configuration
60  */
61 struct mpcc_blnd_cfg {
62 	struct tg_color black_color;	/* background color */
63 	enum mpcc_alpha_blend_mode alpha_mode;	/* alpha blend mode */
64 	bool pre_multiplied_alpha;	/* alpha pre-multiplied mode flag */
65 	int global_gain;
66 	int global_alpha;
67 	bool overlap_only;
68 
69 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
70 	/* MPCC top/bottom gain settings */
71 	int bottom_gain_mode;
72 	int background_color_bpc;
73 	int top_gain;
74 	int bottom_inside_gain;
75 	int bottom_outside_gain;
76 #endif
77 };
78 
79 struct mpcc_sm_cfg {
80 	bool enable;
81 	/* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
82 	int sm_mode;
83 	/* 0- disable frame alternate, 1- enable frame alternate */
84 	bool frame_alt;
85 	/* 0- disable field alternate, 1- enable field alternate */
86 	bool field_alt;
87 	/* 0-no force,2-force frame polarity from top,3-force frame polarity from bottom */
88 	int force_next_frame_porlarity;
89 	/* 0-no force,2-force field polarity from top,3-force field polarity from bottom */
90 	int force_next_field_polarity;
91 };
92 
93 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
94 struct mpc_denorm_clamp {
95 	int clamp_max_r_cr;
96 	int clamp_min_r_cr;
97 	int clamp_max_g_y;
98 	int clamp_min_g_y;
99 	int clamp_max_b_cb;
100 	int clamp_min_b_cb;
101 };
102 #endif
103 
104 /*
105  * MPCC connection and blending configuration for a single MPCC instance.
106  * This struct is used as a node in an MPC tree.
107  */
108 struct mpcc {
109 	int mpcc_id;			/* MPCC physical instance */
110 	int dpp_id;			/* DPP input to this MPCC */
111 	struct mpcc *mpcc_bot;		/* pointer to bottom layer MPCC.  NULL when not connected */
112 	struct mpcc_blnd_cfg blnd_cfg;	/* The blending configuration for this MPCC */
113 	struct mpcc_sm_cfg sm_cfg;	/* stereo mix setting for this MPCC */
114 };
115 
116 /*
117  * MPC tree represents all MPCC connections for a pipe.
118  */
119 struct mpc_tree {
120 	int opp_id;			/* The OPP instance that owns this MPC tree */
121 	struct mpcc *opp_list;		/* The top MPCC layer of the MPC tree that outputs to OPP endpoint */
122 };
123 
124 struct mpc {
125 	const struct mpc_funcs *funcs;
126 	struct dc_context *ctx;
127 
128 	struct mpcc mpcc_array[MAX_MPCC];
129 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
130 	struct pwl_params blender_params;
131 	bool cm_bypass_mode;
132 #endif
133 };
134 
135 struct mpcc_state {
136 	uint32_t opp_id;
137 	uint32_t dpp_id;
138 	uint32_t bot_mpcc_id;
139 	uint32_t mode;
140 	uint32_t alpha_mode;
141 	uint32_t pre_multiplied_alpha;
142 	uint32_t overlap_only;
143 	uint32_t idle;
144 	uint32_t busy;
145 };
146 
147 struct mpc_funcs {
148 	void (*read_mpcc_state)(
149 			struct mpc *mpc,
150 			int mpcc_inst,
151 			struct mpcc_state *s);
152 
153 	/*
154 	 * Insert DPP into MPC tree based on specified blending position.
155 	 * Only used for planes that are part of blending chain for OPP output
156 	 *
157 	 * Parameters:
158 	 * [in/out] mpc		- MPC context.
159 	 * [in/out] tree	- MPC tree structure that plane will be added to.
160 	 * [in]	blnd_cfg	- MPCC blending configuration for the new blending layer.
161 	 * [in]	sm_cfg		- MPCC stereo mix configuration for the new blending layer.
162 	 *			  stereo mix must disable for the very bottom layer of the tree config.
163 	 * [in]	insert_above_mpcc - Insert new plane above this MPCC.  If NULL, insert as bottom plane.
164 	 * [in]	dpp_id		 - DPP instance for the plane to be added.
165 	 * [in]	mpcc_id		 - The MPCC physical instance to use for blending.
166 	 *
167 	 * Return:  struct mpcc* - MPCC that was added.
168 	 */
169 	struct mpcc* (*insert_plane)(
170 			struct mpc *mpc,
171 			struct mpc_tree *tree,
172 			struct mpcc_blnd_cfg *blnd_cfg,
173 			struct mpcc_sm_cfg *sm_cfg,
174 			struct mpcc *insert_above_mpcc,
175 			int dpp_id,
176 			int mpcc_id);
177 
178 	/*
179 	 * Remove a specified MPCC from the MPC tree.
180 	 *
181 	 * Parameters:
182 	 * [in/out] mpc		- MPC context.
183 	 * [in/out] tree	- MPC tree structure that plane will be removed from.
184 	 * [in/out] mpcc	- MPCC to be removed from tree.
185 	 *
186 	 * Return:  void
187 	 */
188 	void (*remove_mpcc)(
189 			struct mpc *mpc,
190 			struct mpc_tree *tree,
191 			struct mpcc *mpcc);
192 
193 	/*
194 	 * Reset the MPCC HW status by disconnecting all muxes.
195 	 *
196 	 * Parameters:
197 	 * [in/out] mpc		- MPC context.
198 	 *
199 	 * Return:  void
200 	 */
201 	void (*mpc_init)(struct mpc *mpc);
202 	void (*mpc_init_single_inst)(
203 			struct mpc *mpc,
204 			unsigned int mpcc_id);
205 
206 	/*
207 	 * Update the blending configuration for a specified MPCC.
208 	 *
209 	 * Parameters:
210 	 * [in/out] mpc		- MPC context.
211 	 * [in]     blnd_cfg	- MPCC blending configuration.
212 	 * [in]     mpcc_id	- The MPCC physical instance.
213 	 *
214 	 * Return:  void
215 	 */
216 	void (*update_blending)(
217 		struct mpc *mpc,
218 		struct mpcc_blnd_cfg *blnd_cfg,
219 		int mpcc_id);
220 
221 	struct mpcc* (*get_mpcc_for_dpp)(
222 			struct mpc_tree *tree,
223 			int dpp_id);
224 
225 	void (*wait_for_idle)(struct mpc *mpc, int id);
226 
227 	void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
228 
229 	void (*init_mpcc_list_from_hw)(
230 		struct mpc *mpc,
231 		struct mpc_tree *tree);
232 
233 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
234 	void (*set_denorm)(struct mpc *mpc,
235 			int opp_id,
236 			enum dc_color_depth output_depth);
237 
238 	void (*set_denorm_clamp)(
239 			struct mpc *mpc,
240 			int opp_id,
241 			struct mpc_denorm_clamp denorm_clamp);
242 
243 	void (*set_output_csc)(struct mpc *mpc,
244 			int opp_id,
245 			const uint16_t *regval,
246 			enum mpc_output_csc_mode ocsc_mode);
247 
248 	void (*set_ocsc_default)(struct mpc *mpc,
249 			int opp_id,
250 			enum dc_color_space color_space,
251 			enum mpc_output_csc_mode ocsc_mode);
252 
253 	void (*set_output_gamma)(
254 			struct mpc *mpc,
255 			int mpcc_id,
256 			const struct pwl_params *params);
257 	void (*power_on_mpc_mem_pwr)(
258 			struct mpc *mpc,
259 			int mpcc_id,
260 			bool power_on);
261 #endif
262 
263 };
264 
265 #endif
266