1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 /*
24  * link_encoder.h
25  *
26  *  Created on: Oct 6, 2015
27  *      Author: yonsun
28  */
29 
30 #ifndef LINK_ENCODER_H_
31 #define LINK_ENCODER_H_
32 
33 #include "grph_object_defs.h"
34 #include "signal_types.h"
35 #include "dc_types.h"
36 
37 struct dc_context;
38 struct encoder_set_dp_phy_pattern_param;
39 struct link_mst_stream_allocation_table;
40 struct dc_link_settings;
41 struct link_training_settings;
42 struct pipe_ctx;
43 
44 struct encoder_init_data {
45 	enum channel_id channel;
46 	struct graphics_object_id connector;
47 	enum hpd_source_id hpd_source;
48 	/* TODO: in DAL2, here was pointer to EventManagerInterface */
49 	struct graphics_object_id encoder;
50 	struct dc_context *ctx;
51 	enum transmitter transmitter;
52 };
53 
54 struct encoder_feature_support {
55 	union {
56 		struct {
57 			uint32_t IS_HBR2_CAPABLE:1;
58 			uint32_t IS_HBR3_CAPABLE:1;
59 			uint32_t IS_TPS3_CAPABLE:1;
60 			uint32_t IS_TPS4_CAPABLE:1;
61 			uint32_t HDMI_6GB_EN:1;
62 			uint32_t IS_DP2_CAPABLE:1;
63 			uint32_t IS_UHBR10_CAPABLE:1;
64 			uint32_t IS_UHBR13_5_CAPABLE:1;
65 			uint32_t IS_UHBR20_CAPABLE:1;
66 			uint32_t DP_IS_USB_C:1;
67 		} bits;
68 		uint32_t raw;
69 	} flags;
70 
71 	enum dc_color_depth max_hdmi_deep_color;
72 	unsigned int max_hdmi_pixel_clock;
73 	bool hdmi_ycbcr420_supported;
74 	bool dp_ycbcr420_supported;
75 	bool fec_supported;
76 };
77 
78 union dpcd_psr_configuration {
79 	struct {
80 		unsigned char ENABLE                    : 1;
81 		unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
82 		unsigned char CRC_VERIFICATION          : 1;
83 		unsigned char FRAME_CAPTURE_INDICATION  : 1;
84 		/* For eDP 1.4, PSR v2*/
85 		unsigned char LINE_CAPTURE_INDICATION   : 1;
86 		/* For eDP 1.4, PSR v2*/
87 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
88 		unsigned char RESERVED                  : 2;
89 	} bits;
90 	unsigned char raw;
91 };
92 
93 union psr_error_status {
94 	struct {
95 		unsigned char LINK_CRC_ERROR        :1;
96 		unsigned char RFB_STORAGE_ERROR     :1;
97 		unsigned char VSC_SDP_ERROR         :1;
98 		unsigned char RESERVED              :5;
99 	} bits;
100 	unsigned char raw;
101 };
102 
103 union psr_sink_psr_status {
104 	struct {
105 	unsigned char SINK_SELF_REFRESH_STATUS  :3;
106 	unsigned char RESERVED                  :5;
107 	} bits;
108 	unsigned char raw;
109 };
110 
111 struct link_encoder {
112 	const struct link_encoder_funcs *funcs;
113 	int32_t aux_channel_offset;
114 	struct dc_context *ctx;
115 	struct graphics_object_id id;
116 	struct graphics_object_id connector;
117 	uint32_t output_signals;
118 	enum engine_id preferred_engine;
119 	struct encoder_feature_support features;
120 	enum transmitter transmitter;
121 	enum hpd_source_id hpd_source;
122 	bool usbc_combo_phy;
123 };
124 
125 struct link_enc_state {
126 
127 		uint32_t dphy_fec_en;
128 		uint32_t dphy_fec_ready_shadow;
129 		uint32_t dphy_fec_active_status;
130 		uint32_t dp_link_training_complete;
131 
132 };
133 
134 enum encoder_type_select {
135 	ENCODER_TYPE_DIG = 0,
136 	ENCODER_TYPE_HDMI_FRL = 1,
137 	ENCODER_TYPE_DP_128B132B = 2
138 };
139 
140 struct link_encoder_funcs {
141 	void (*read_state)(
142 			struct link_encoder *enc, struct link_enc_state *s);
143 	bool (*validate_output_with_stream)(
144 		struct link_encoder *enc, const struct dc_stream_state *stream);
145 	void (*hw_init)(struct link_encoder *enc);
146 	void (*setup)(struct link_encoder *enc,
147 		enum signal_type signal);
148 	void (*enable_tmds_output)(struct link_encoder *enc,
149 		enum clock_source_id clock_source,
150 		enum dc_color_depth color_depth,
151 		enum signal_type signal,
152 		uint32_t pixel_clock);
153 	void (*enable_dp_output)(struct link_encoder *enc,
154 		const struct dc_link_settings *link_settings,
155 		enum clock_source_id clock_source);
156 	void (*enable_dp_mst_output)(struct link_encoder *enc,
157 		const struct dc_link_settings *link_settings,
158 		enum clock_source_id clock_source);
159 	void (*enable_lvds_output)(struct link_encoder *enc,
160 		enum clock_source_id clock_source,
161 		uint32_t pixel_clock);
162 	void (*disable_output)(struct link_encoder *link_enc,
163 		enum signal_type signal);
164 	void (*dp_set_lane_settings)(struct link_encoder *enc,
165 		const struct link_training_settings *link_settings);
166 	void (*dp_set_phy_pattern)(struct link_encoder *enc,
167 		const struct encoder_set_dp_phy_pattern_param *para);
168 	void (*update_mst_stream_allocation_table)(
169 		struct link_encoder *enc,
170 		const struct link_mst_stream_allocation_table *table);
171 	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
172 			bool exit_link_training_required);
173 	void (*psr_program_secondary_packet)(struct link_encoder *enc,
174 				unsigned int sdp_transmit_line_num_deadline);
175 	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
176 		enum engine_id engine,
177 		bool connect);
178 	void (*enable_hpd)(struct link_encoder *enc);
179 	void (*disable_hpd)(struct link_encoder *enc);
180 	bool (*is_dig_enabled)(struct link_encoder *enc);
181 	unsigned int (*get_dig_frontend)(struct link_encoder *enc);
182 	void (*destroy)(struct link_encoder **enc);
183 
184 	void (*fec_set_enable)(struct link_encoder *enc,
185 		bool enable);
186 
187 	void (*fec_set_ready)(struct link_encoder *enc,
188 		bool ready);
189 
190 	bool (*fec_is_active)(struct link_encoder *enc);
191 	bool (*is_in_alt_mode) (struct link_encoder *enc);
192 
193 	void (*get_max_link_cap)(struct link_encoder *enc,
194 		struct dc_link_settings *link_settings);
195 
196 	enum signal_type (*get_dig_mode)(
197 		struct link_encoder *enc);
198 	void (*set_dio_phy_mux)(
199 		struct link_encoder *enc,
200 		enum encoder_type_select sel,
201 		uint32_t hpo_inst);
202 };
203 
204 /*
205  * Used to track assignments of links (display endpoints) to link encoders.
206  *
207  * Entry in link_enc_assignments table in struct resource_context.
208  * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
209  * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
210  */
211 struct link_enc_assignment {
212 	bool valid;
213 	struct display_endpoint_id ep_id;
214 	enum engine_id eng_id;
215 	struct dc_stream_state *stream;
216 };
217 
218 enum link_enc_cfg_mode {
219 	LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */
220 	LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
221 };
222 
223 #if defined(CONFIG_DRM_AMD_DC_DCN)
224 enum dp2_link_mode {
225 	DP2_LINK_TRAINING_TPS1,
226 	DP2_LINK_TRAINING_TPS2,
227 	DP2_LINK_ACTIVE,
228 	DP2_TEST_PATTERN
229 };
230 
231 enum dp2_phy_tp_select {
232 	DP_DPHY_TP_SELECT_TPS1,
233 	DP_DPHY_TP_SELECT_TPS2,
234 	DP_DPHY_TP_SELECT_PRBS,
235 	DP_DPHY_TP_SELECT_CUSTOM,
236 	DP_DPHY_TP_SELECT_SQUARE
237 };
238 
239 enum dp2_phy_tp_prbs {
240 	DP_DPHY_TP_PRBS7,
241 	DP_DPHY_TP_PRBS9,
242 	DP_DPHY_TP_PRBS11,
243 	DP_DPHY_TP_PRBS15,
244 	DP_DPHY_TP_PRBS23,
245 	DP_DPHY_TP_PRBS31
246 };
247 
248 struct hpo_dp_link_enc_state {
249 	uint32_t   link_enc_enabled;
250 	uint32_t   link_mode;
251 	uint32_t   lane_count;
252 	uint32_t   slot_count[4];
253 	uint32_t   stream_src[4];
254 	uint32_t   vc_rate_x[4];
255 	uint32_t   vc_rate_y[4];
256 };
257 
258 struct hpo_dp_link_encoder {
259 	const struct hpo_dp_link_encoder_funcs *funcs;
260 	struct dc_context *ctx;
261 	int inst;
262 	enum engine_id preferred_engine;
263 	enum transmitter transmitter;
264 	enum hpd_source_id hpd_source;
265 };
266 
267 struct hpo_dp_link_encoder_funcs {
268 
269 	void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
270 		const struct dc_link_settings *link_settings,
271 		enum transmitter transmitter);
272 
273 	void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
274 		enum signal_type signal);
275 
276 	void (*link_enable)(
277 			struct hpo_dp_link_encoder *enc,
278 			enum dc_lane_count num_lanes);
279 
280 	void (*link_disable)(
281 			struct hpo_dp_link_encoder *enc);
282 
283 	void (*set_link_test_pattern)(
284 			struct hpo_dp_link_encoder *enc,
285 			struct encoder_set_dp_phy_pattern_param *tp_params);
286 
287 	void (*update_stream_allocation_table)(
288 			struct hpo_dp_link_encoder *enc,
289 			const struct link_mst_stream_allocation_table *table);
290 
291 	void (*set_throttled_vcp_size)(
292 			struct hpo_dp_link_encoder *enc,
293 			uint32_t stream_encoder_inst,
294 			struct fixed31_32 avg_time_slots_per_mtp);
295 
296 	bool (*is_in_alt_mode) (
297 			struct hpo_dp_link_encoder *enc);
298 
299 	void (*read_state)(
300 			struct hpo_dp_link_encoder *enc,
301 			struct hpo_dp_link_enc_state *state);
302 
303 	void (*set_ffe)(
304 		struct hpo_dp_link_encoder *enc,
305 		const struct dc_link_settings *link_settings,
306 		uint8_t ffe_preset);
307 };
308 #endif
309 
310 #endif /* LINK_ENCODER_H_ */
311