1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 #define MAX_PIPES 6 39 #define MAX_DWB_PIPES 1 40 41 struct gamma_curve { 42 uint32_t offset; 43 uint32_t segments_num; 44 }; 45 46 struct curve_points { 47 struct fixed31_32 x; 48 struct fixed31_32 y; 49 struct fixed31_32 offset; 50 struct fixed31_32 slope; 51 52 uint32_t custom_float_x; 53 uint32_t custom_float_y; 54 uint32_t custom_float_offset; 55 uint32_t custom_float_slope; 56 }; 57 58 struct curve_points3 { 59 struct curve_points red; 60 struct curve_points green; 61 struct curve_points blue; 62 }; 63 64 struct pwl_result_data { 65 struct fixed31_32 red; 66 struct fixed31_32 green; 67 struct fixed31_32 blue; 68 69 struct fixed31_32 delta_red; 70 struct fixed31_32 delta_green; 71 struct fixed31_32 delta_blue; 72 73 uint32_t red_reg; 74 uint32_t green_reg; 75 uint32_t blue_reg; 76 77 uint32_t delta_red_reg; 78 uint32_t delta_green_reg; 79 uint32_t delta_blue_reg; 80 }; 81 82 struct dc_rgb { 83 uint32_t red; 84 uint32_t green; 85 uint32_t blue; 86 }; 87 88 struct tetrahedral_17x17x17 { 89 struct dc_rgb lut0[1229]; 90 struct dc_rgb lut1[1228]; 91 struct dc_rgb lut2[1228]; 92 struct dc_rgb lut3[1228]; 93 }; 94 struct tetrahedral_9x9x9 { 95 struct dc_rgb lut0[183]; 96 struct dc_rgb lut1[182]; 97 struct dc_rgb lut2[182]; 98 struct dc_rgb lut3[182]; 99 }; 100 101 struct tetrahedral_params { 102 union { 103 struct tetrahedral_17x17x17 tetrahedral_17; 104 struct tetrahedral_9x9x9 tetrahedral_9; 105 }; 106 bool use_tetrahedral_9; 107 bool use_12bits; 108 109 }; 110 111 /* arr_curve_points - regamma regions/segments specification 112 * arr_points - beginning and end point specified separately (only one on DCE) 113 * corner_points - beginning and end point for all 3 colors (DCN) 114 * rgb_resulted - final curve 115 */ 116 struct pwl_params { 117 struct gamma_curve arr_curve_points[34]; 118 union { 119 struct curve_points arr_points[2]; 120 struct curve_points3 corner_points[2]; 121 }; 122 struct pwl_result_data rgb_resulted[256 + 3]; 123 uint32_t hw_points_num; 124 }; 125 126 /* move to dpp 127 * while we are moving functionality out of opp to dpp to align 128 * HW programming to HW IP, we define these struct in hw_shared 129 * so we can still compile while refactoring 130 */ 131 132 enum lb_pixel_depth { 133 /* do not change the values because it is used as bit vector */ 134 LB_PIXEL_DEPTH_18BPP = 1, 135 LB_PIXEL_DEPTH_24BPP = 2, 136 LB_PIXEL_DEPTH_30BPP = 4, 137 LB_PIXEL_DEPTH_36BPP = 8 138 }; 139 140 enum graphics_csc_adjust_type { 141 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 142 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 143 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 144 }; 145 146 enum ipp_degamma_mode { 147 IPP_DEGAMMA_MODE_BYPASS, 148 IPP_DEGAMMA_MODE_HW_sRGB, 149 IPP_DEGAMMA_MODE_HW_xvYCC, 150 IPP_DEGAMMA_MODE_USER_PWL 151 }; 152 153 enum gamcor_mode { 154 GAMCOR_MODE_BYPASS, 155 GAMCOR_MODE_RESERVED_1, 156 GAMCOR_MODE_USER_PWL, 157 GAMCOR_MODE_RESERVED_3 158 }; 159 160 enum ipp_output_format { 161 IPP_OUTPUT_FORMAT_12_BIT_FIX, 162 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 163 IPP_OUTPUT_FORMAT_FLOAT 164 }; 165 166 enum expansion_mode { 167 EXPANSION_MODE_DYNAMIC, 168 EXPANSION_MODE_ZERO 169 }; 170 171 struct default_adjustment { 172 enum lb_pixel_depth lb_color_depth; 173 enum dc_color_space out_color_space; 174 enum dc_color_space in_color_space; 175 enum dc_color_depth color_depth; 176 enum pixel_format surface_pixel_format; 177 enum graphics_csc_adjust_type csc_adjust_type; 178 bool force_hw_default; 179 }; 180 181 182 struct out_csc_color_matrix { 183 enum dc_color_space color_space; 184 uint16_t regval[12]; 185 }; 186 187 enum gamut_remap_select { 188 GAMUT_REMAP_BYPASS = 0, 189 GAMUT_REMAP_COEFF, 190 GAMUT_REMAP_COMA_COEFF, 191 GAMUT_REMAP_COMB_COEFF 192 }; 193 194 enum opp_regamma { 195 OPP_REGAMMA_BYPASS = 0, 196 OPP_REGAMMA_SRGB, 197 OPP_REGAMMA_XVYCC, 198 OPP_REGAMMA_USER 199 }; 200 201 enum optc_dsc_mode { 202 OPTC_DSC_DISABLED = 0, 203 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 204 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 205 }; 206 207 struct dc_bias_and_scale { 208 uint16_t scale_red; 209 uint16_t bias_red; 210 uint16_t scale_green; 211 uint16_t bias_green; 212 uint16_t scale_blue; 213 uint16_t bias_blue; 214 }; 215 216 enum test_pattern_dyn_range { 217 TEST_PATTERN_DYN_RANGE_VESA = 0, 218 TEST_PATTERN_DYN_RANGE_CEA 219 }; 220 221 enum test_pattern_mode { 222 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 223 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 224 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 225 TEST_PATTERN_MODE_VERTICALBARS, 226 TEST_PATTERN_MODE_HORIZONTALBARS, 227 TEST_PATTERN_MODE_SINGLERAMP_RGB, 228 TEST_PATTERN_MODE_DUALRAMP_RGB, 229 TEST_PATTERN_MODE_XR_BIAS_RGB 230 }; 231 232 enum test_pattern_color_format { 233 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 234 TEST_PATTERN_COLOR_FORMAT_BPC_8, 235 TEST_PATTERN_COLOR_FORMAT_BPC_10, 236 TEST_PATTERN_COLOR_FORMAT_BPC_12 237 }; 238 239 enum controller_dp_test_pattern { 240 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 241 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 242 CONTROLLER_DP_TEST_PATTERN_PRBS7, 243 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 244 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 245 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 246 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 247 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 248 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 249 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 250 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 251 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 252 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 253 }; 254 255 enum controller_dp_color_space { 256 CONTROLLER_DP_COLOR_SPACE_RGB, 257 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 258 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 259 CONTROLLER_DP_COLOR_SPACE_UDEFINED 260 }; 261 262 enum dc_lut_mode { 263 LUT_BYPASS, 264 LUT_RAM_A, 265 LUT_RAM_B 266 }; 267 268 /** 269 * speakersToChannels 270 * 271 * @brief 272 * translate speakers to channels 273 * 274 * FL - Front Left 275 * FR - Front Right 276 * RL - Rear Left 277 * RR - Rear Right 278 * RC - Rear Center 279 * FC - Front Center 280 * FLC - Front Left Center 281 * FRC - Front Right Center 282 * RLC - Rear Left Center 283 * RRC - Rear Right Center 284 * LFE - Low Freq Effect 285 * 286 * FC 287 * FLC FRC 288 * FL FR 289 * 290 * LFE 291 * () 292 * 293 * 294 * RL RR 295 * RLC RRC 296 * RC 297 * 298 * ch 8 7 6 5 4 3 2 1 299 * 0b00000011 - - - - - - FR FL 300 * 0b00000111 - - - - - LFE FR FL 301 * 0b00001011 - - - - FC - FR FL 302 * 0b00001111 - - - - FC LFE FR FL 303 * 0b00010011 - - - RC - - FR FL 304 * 0b00010111 - - - RC - LFE FR FL 305 * 0b00011011 - - - RC FC - FR FL 306 * 0b00011111 - - - RC FC LFE FR FL 307 * 0b00110011 - - RR RL - - FR FL 308 * 0b00110111 - - RR RL - LFE FR FL 309 * 0b00111011 - - RR RL FC - FR FL 310 * 0b00111111 - - RR RL FC LFE FR FL 311 * 0b01110011 - RC RR RL - - FR FL 312 * 0b01110111 - RC RR RL - LFE FR FL 313 * 0b01111011 - RC RR RL FC - FR FL 314 * 0b01111111 - RC RR RL FC LFE FR FL 315 * 0b11110011 RRC RLC RR RL - - FR FL 316 * 0b11110111 RRC RLC RR RL - LFE FR FL 317 * 0b11111011 RRC RLC RR RL FC - FR FL 318 * 0b11111111 RRC RLC RR RL FC LFE FR FL 319 * 0b11000011 FRC FLC - - - - FR FL 320 * 0b11000111 FRC FLC - - - LFE FR FL 321 * 0b11001011 FRC FLC - - FC - FR FL 322 * 0b11001111 FRC FLC - - FC LFE FR FL 323 * 0b11010011 FRC FLC - RC - - FR FL 324 * 0b11010111 FRC FLC - RC - LFE FR FL 325 * 0b11011011 FRC FLC - RC FC - FR FL 326 * 0b11011111 FRC FLC - RC FC LFE FR FL 327 * 0b11110011 FRC FLC RR RL - - FR FL 328 * 0b11110111 FRC FLC RR RL - LFE FR FL 329 * 0b11111011 FRC FLC RR RL FC - FR FL 330 * 0b11111111 FRC FLC RR RL FC LFE FR FL 331 * 332 * @param 333 * speakers - speaker information as it comes from CEA audio block 334 */ 335 /* translate speakers to channels */ 336 337 union audio_cea_channels { 338 uint8_t all; 339 struct audio_cea_channels_bits { 340 uint32_t FL:1; 341 uint32_t FR:1; 342 uint32_t LFE:1; 343 uint32_t FC:1; 344 uint32_t RL_RC:1; 345 uint32_t RR:1; 346 uint32_t RC_RLC_FLC:1; 347 uint32_t RRC_FRC:1; 348 } channels; 349 }; 350 351 #endif /* __DAL_HW_SHARED_H__ */ 352