1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_HW_SHARED_H__
27 #define __DAL_HW_SHARED_H__
28 
29 #include "os_types.h"
30 #include "fixed31_32.h"
31 #include "dc_hw_types.h"
32 
33 /******************************************************************************
34  * Data types shared between different Virtual HW blocks
35  ******************************************************************************/
36 
37 #define MAX_AUDIOS 7
38 #define MAX_PIPES 6
39 #define MAX_DIG_LINK_ENCODERS 7
40 #define MAX_DWB_PIPES	1
41 #define MAX_HPO_DP2_ENCODERS	4
42 #define MAX_HPO_DP2_LINK_ENCODERS	2
43 
44 struct gamma_curve {
45 	uint32_t offset;
46 	uint32_t segments_num;
47 };
48 
49 struct curve_points {
50 	struct fixed31_32 x;
51 	struct fixed31_32 y;
52 	struct fixed31_32 offset;
53 	struct fixed31_32 slope;
54 
55 	uint32_t custom_float_x;
56 	uint32_t custom_float_y;
57 	uint32_t custom_float_offset;
58 	uint32_t custom_float_slope;
59 };
60 
61 struct curve_points3 {
62 	struct curve_points red;
63 	struct curve_points green;
64 	struct curve_points blue;
65 };
66 
67 struct pwl_result_data {
68 	struct fixed31_32 red;
69 	struct fixed31_32 green;
70 	struct fixed31_32 blue;
71 
72 	struct fixed31_32 delta_red;
73 	struct fixed31_32 delta_green;
74 	struct fixed31_32 delta_blue;
75 
76 	uint32_t red_reg;
77 	uint32_t green_reg;
78 	uint32_t blue_reg;
79 
80 	uint32_t delta_red_reg;
81 	uint32_t delta_green_reg;
82 	uint32_t delta_blue_reg;
83 };
84 
85 struct dc_rgb {
86 	uint32_t red;
87 	uint32_t green;
88 	uint32_t blue;
89 };
90 
91 struct tetrahedral_17x17x17 {
92 	struct dc_rgb lut0[1229];
93 	struct dc_rgb lut1[1228];
94 	struct dc_rgb lut2[1228];
95 	struct dc_rgb lut3[1228];
96 };
97 struct tetrahedral_9x9x9 {
98 	struct dc_rgb lut0[183];
99 	struct dc_rgb lut1[182];
100 	struct dc_rgb lut2[182];
101 	struct dc_rgb lut3[182];
102 };
103 
104 struct tetrahedral_params {
105 	union {
106 		struct tetrahedral_17x17x17 tetrahedral_17;
107 		struct tetrahedral_9x9x9 tetrahedral_9;
108 	};
109 	bool use_tetrahedral_9;
110 	bool use_12bits;
111 
112 };
113 
114 /* arr_curve_points - regamma regions/segments specification
115  * arr_points - beginning and end point specified separately (only one on DCE)
116  * corner_points - beginning and end point for all 3 colors (DCN)
117  * rgb_resulted - final curve
118  */
119 struct pwl_params {
120 	struct gamma_curve arr_curve_points[34];
121 	union {
122 		struct curve_points arr_points[2];
123 		struct curve_points3 corner_points[2];
124 	};
125 	struct pwl_result_data rgb_resulted[256 + 3];
126 	uint32_t hw_points_num;
127 };
128 
129 /* move to dpp
130  * while we are moving functionality out of opp to dpp to align
131  * HW programming to HW IP, we define these struct in hw_shared
132  * so we can still compile while refactoring
133  */
134 
135 enum lb_pixel_depth {
136 	/* do not change the values because it is used as bit vector */
137 	LB_PIXEL_DEPTH_18BPP = 1,
138 	LB_PIXEL_DEPTH_24BPP = 2,
139 	LB_PIXEL_DEPTH_30BPP = 4,
140 	LB_PIXEL_DEPTH_36BPP = 8
141 };
142 
143 enum graphics_csc_adjust_type {
144 	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
145 	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
146 	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
147 };
148 
149 enum ipp_degamma_mode {
150 	IPP_DEGAMMA_MODE_BYPASS,
151 	IPP_DEGAMMA_MODE_HW_sRGB,
152 	IPP_DEGAMMA_MODE_HW_xvYCC,
153 	IPP_DEGAMMA_MODE_USER_PWL
154 };
155 
156 enum gamcor_mode {
157 	GAMCOR_MODE_BYPASS,
158 	GAMCOR_MODE_RESERVED_1,
159 	GAMCOR_MODE_USER_PWL,
160 	GAMCOR_MODE_RESERVED_3
161 };
162 
163 enum ipp_output_format {
164 	IPP_OUTPUT_FORMAT_12_BIT_FIX,
165 	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
166 	IPP_OUTPUT_FORMAT_FLOAT
167 };
168 
169 enum expansion_mode {
170 	EXPANSION_MODE_DYNAMIC,
171 	EXPANSION_MODE_ZERO
172 };
173 
174 struct default_adjustment {
175 	enum lb_pixel_depth lb_color_depth;
176 	enum dc_color_space out_color_space;
177 	enum dc_color_space in_color_space;
178 	enum dc_color_depth color_depth;
179 	enum pixel_format surface_pixel_format;
180 	enum graphics_csc_adjust_type csc_adjust_type;
181 	bool force_hw_default;
182 };
183 
184 
185 struct out_csc_color_matrix {
186 	enum dc_color_space color_space;
187 	uint16_t regval[12];
188 };
189 
190 enum gamut_remap_select {
191 	GAMUT_REMAP_BYPASS = 0,
192 	GAMUT_REMAP_COEFF,
193 	GAMUT_REMAP_COMA_COEFF,
194 	GAMUT_REMAP_COMB_COEFF
195 };
196 
197 enum opp_regamma {
198 	OPP_REGAMMA_BYPASS = 0,
199 	OPP_REGAMMA_SRGB,
200 	OPP_REGAMMA_XVYCC,
201 	OPP_REGAMMA_USER
202 };
203 
204 enum optc_dsc_mode {
205 	OPTC_DSC_DISABLED = 0,
206 	OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
207 	OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
208 };
209 
210 struct dc_bias_and_scale {
211 	uint16_t scale_red;
212 	uint16_t bias_red;
213 	uint16_t scale_green;
214 	uint16_t bias_green;
215 	uint16_t scale_blue;
216 	uint16_t bias_blue;
217 };
218 
219 enum test_pattern_dyn_range {
220 	TEST_PATTERN_DYN_RANGE_VESA = 0,
221 	TEST_PATTERN_DYN_RANGE_CEA
222 };
223 
224 enum test_pattern_mode {
225 	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
226 	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
227 	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
228 	TEST_PATTERN_MODE_VERTICALBARS,
229 	TEST_PATTERN_MODE_HORIZONTALBARS,
230 	TEST_PATTERN_MODE_SINGLERAMP_RGB,
231 	TEST_PATTERN_MODE_DUALRAMP_RGB,
232 	TEST_PATTERN_MODE_XR_BIAS_RGB
233 };
234 
235 enum test_pattern_color_format {
236 	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
237 	TEST_PATTERN_COLOR_FORMAT_BPC_8,
238 	TEST_PATTERN_COLOR_FORMAT_BPC_10,
239 	TEST_PATTERN_COLOR_FORMAT_BPC_12
240 };
241 
242 enum controller_dp_test_pattern {
243 	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
244 	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
245 	CONTROLLER_DP_TEST_PATTERN_PRBS7,
246 	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
247 	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
248 	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
249 	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
250 	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
251 	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
252 	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
253 	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
254 	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
255 	CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
256 };
257 
258 enum controller_dp_color_space {
259 	CONTROLLER_DP_COLOR_SPACE_RGB,
260 	CONTROLLER_DP_COLOR_SPACE_YCBCR601,
261 	CONTROLLER_DP_COLOR_SPACE_YCBCR709,
262 	CONTROLLER_DP_COLOR_SPACE_UDEFINED
263 };
264 
265 enum dc_lut_mode {
266 	LUT_BYPASS,
267 	LUT_RAM_A,
268 	LUT_RAM_B
269 };
270 
271 enum symclk_state {
272 	SYMCLK_OFF_TX_OFF,
273 	SYMCLK_ON_TX_ON,
274 	SYMCLK_ON_TX_OFF,
275 };
276 
277 struct phy_state {
278 	struct {
279 		uint8_t otg		: 1;
280 		uint8_t reserved	: 7;
281 	} symclk_ref_cnts;
282 	enum symclk_state symclk_state;
283 };
284 
285 /**
286  * speakersToChannels
287  *
288  * @brief
289  *  translate speakers to channels
290  *
291  *  FL  - Front Left
292  *  FR  - Front Right
293  *  RL  - Rear Left
294  *  RR  - Rear Right
295  *  RC  - Rear Center
296  *  FC  - Front Center
297  *  FLC - Front Left Center
298  *  FRC - Front Right Center
299  *  RLC - Rear Left Center
300  *  RRC - Rear Right Center
301  *  LFE - Low Freq Effect
302  *
303  *               FC
304  *          FLC      FRC
305  *    FL                    FR
306  *
307  *                    LFE
308  *              ()
309  *
310  *
311  *    RL                    RR
312  *          RLC      RRC
313  *               RC
314  *
315  *             ch  8   7   6   5   4   3   2   1
316  * 0b00000011      -   -   -   -   -   -   FR  FL
317  * 0b00000111      -   -   -   -   -   LFE FR  FL
318  * 0b00001011      -   -   -   -   FC  -   FR  FL
319  * 0b00001111      -   -   -   -   FC  LFE FR  FL
320  * 0b00010011      -   -   -   RC  -   -   FR  FL
321  * 0b00010111      -   -   -   RC  -   LFE FR  FL
322  * 0b00011011      -   -   -   RC  FC  -   FR  FL
323  * 0b00011111      -   -   -   RC  FC  LFE FR  FL
324  * 0b00110011      -   -   RR  RL  -   -   FR  FL
325  * 0b00110111      -   -   RR  RL  -   LFE FR  FL
326  * 0b00111011      -   -   RR  RL  FC  -   FR  FL
327  * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
328  * 0b01110011      -   RC  RR  RL  -   -   FR  FL
329  * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
330  * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
331  * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
332  * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
333  * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
334  * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
335  * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
336  * 0b11000011      FRC FLC -   -   -   -   FR  FL
337  * 0b11000111      FRC FLC -   -   -   LFE FR  FL
338  * 0b11001011      FRC FLC -   -   FC  -   FR  FL
339  * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
340  * 0b11010011      FRC FLC -   RC  -   -   FR  FL
341  * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
342  * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
343  * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
344  * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
345  * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
346  * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
347  * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
348  *
349  * @param
350  *  speakers - speaker information as it comes from CEA audio block
351  */
352 /* translate speakers to channels */
353 
354 union audio_cea_channels {
355 	uint8_t all;
356 	struct audio_cea_channels_bits {
357 		uint32_t FL:1;
358 		uint32_t FR:1;
359 		uint32_t LFE:1;
360 		uint32_t FC:1;
361 		uint32_t RL_RC:1;
362 		uint32_t RR:1;
363 		uint32_t RC_RLC_FLC:1;
364 		uint32_t RRC_FRC:1;
365 	} channels;
366 };
367 
368 #endif /* __DAL_HW_SHARED_H__ */
369