1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_DMCU_H__ 26 #define __DC_DMCU_H__ 27 28 #include "dm_services_types.h" 29 30 /* If HW itself ever powered down it will be 0. 31 * fwDmcuInit will write to 1. 32 * Driver will only call MCP init if current state is 1, 33 * and the MCP command will transition this to 2. 34 */ 35 enum dmcu_state { 36 DMCU_UNLOADED = 0, 37 DMCU_LOADED_UNINITIALIZED = 1, 38 DMCU_RUNNING = 2, 39 }; 40 41 struct dmcu_version { 42 unsigned int interface_version; 43 unsigned int abm_version; 44 unsigned int psr_version; 45 unsigned int build_version; 46 }; 47 48 struct dmcu { 49 struct dc_context *ctx; 50 const struct dmcu_funcs *funcs; 51 52 enum dmcu_state dmcu_state; 53 struct dmcu_version dmcu_version; 54 unsigned int cached_wait_loop_number; 55 uint32_t psp_version; 56 bool auto_load_dmcu; 57 }; 58 59 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 60 struct crc_region { 61 uint16_t x_start; 62 uint16_t y_start; 63 uint16_t x_end; 64 uint16_t y_end; 65 }; 66 67 struct otg_phy_mux { 68 uint8_t phy_output_num; 69 uint8_t otg_output_num; 70 }; 71 #endif 72 73 struct dmcu_funcs { 74 bool (*dmcu_init)(struct dmcu *dmcu); 75 bool (*load_iram)(struct dmcu *dmcu, 76 unsigned int start_offset, 77 const char *src, 78 unsigned int bytes); 79 void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait); 80 bool (*setup_psr)(struct dmcu *dmcu, 81 struct dc_link *link, 82 struct psr_context *psr_context); 83 void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state); 84 void (*set_psr_wait_loop)(struct dmcu *dmcu, 85 unsigned int wait_loop_number); 86 void (*get_psr_wait_loop)(struct dmcu *dmcu, 87 unsigned int *psr_wait_loop_number); 88 bool (*is_dmcu_initialized)(struct dmcu *dmcu); 89 bool (*lock_phy)(struct dmcu *dmcu); 90 bool (*unlock_phy)(struct dmcu *dmcu); 91 bool (*send_edid_cea)(struct dmcu *dmcu, 92 int offset, 93 int total_length, 94 uint8_t *data, 95 int length); 96 bool (*recv_amd_vsdb)(struct dmcu *dmcu, 97 int *version, 98 int *min_frame_rate, 99 int *max_frame_rate); 100 bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset); 101 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 102 void (*forward_crc_window)(struct dmcu *dmcu, 103 struct crc_region *crc_win, 104 struct otg_phy_mux *mux_mapping); 105 void (*stop_crc_win_update)(struct dmcu *dmcu, 106 struct otg_phy_mux *mux_mapping); 107 #endif 108 }; 109 110 #endif 111