1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCCG_H__ 27 #define __DAL_DCCG_H__ 28 29 #include "dc_types.h" 30 #include "hw_shared.h" 31 32 enum phyd32clk_clock_source { 33 PHYD32CLKA, 34 PHYD32CLKB, 35 PHYD32CLKC, 36 PHYD32CLKD, 37 PHYD32CLKE, 38 PHYD32CLKF, 39 PHYD32CLKG, 40 }; 41 42 enum physymclk_clock_source { 43 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO. 44 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO. 45 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. 46 }; 47 48 enum streamclk_source { 49 REFCLK, // Selects REFCLK as source for hdmistreamclk. 50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. 51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk 52 }; 53 54 enum dentist_dispclk_change_mode { 55 DISPCLK_CHANGE_MODE_IMMEDIATE, 56 DISPCLK_CHANGE_MODE_RAMPING, 57 }; 58 59 enum pixel_rate_div { 60 PIXEL_RATE_DIV_BY_1 = 0, 61 PIXEL_RATE_DIV_BY_2 = 1, 62 PIXEL_RATE_DIV_BY_4 = 3 63 }; 64 65 struct dccg { 66 struct dc_context *ctx; 67 const struct dccg_funcs *funcs; 68 int pipe_dppclk_khz[MAX_PIPES]; 69 int ref_dppclk; 70 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */ 71 //int audio_dtbclk_khz;/* TODO needs to be removed */ 72 int ref_dtbclk_khz;/* TODO needs to be removed */ 73 }; 74 75 struct dtbclk_dto_params { 76 const struct dc_crtc_timing *timing; 77 int otg_inst; 78 int pixclk_khz; 79 int req_audio_dtbclk_khz; 80 int num_odm_segments; 81 int ref_dtbclk_khz; 82 }; 83 84 struct dccg_funcs { 85 void (*update_dpp_dto)(struct dccg *dccg, 86 int dpp_inst, 87 int req_dppclk); 88 void (*get_dccg_ref_freq)(struct dccg *dccg, 89 unsigned int xtalin_freq_inKhz, 90 unsigned int *dccg_ref_freq_inKhz); 91 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg, 92 bool en); 93 void (*otg_add_pixel)(struct dccg *dccg, 94 uint32_t otg_inst); 95 void (*otg_drop_pixel)(struct dccg *dccg, 96 uint32_t otg_inst); 97 void (*dccg_init)(struct dccg *dccg); 98 99 void (*set_dpstreamclk)( 100 struct dccg *dccg, 101 enum streamclk_source src, 102 int otg_inst); 103 104 void (*enable_symclk32_se)( 105 struct dccg *dccg, 106 int hpo_se_inst, 107 enum phyd32clk_clock_source phyd32clk); 108 109 void (*disable_symclk32_se)( 110 struct dccg *dccg, 111 int hpo_se_inst); 112 113 void (*enable_symclk32_le)( 114 struct dccg *dccg, 115 int hpo_le_inst, 116 enum phyd32clk_clock_source phyd32clk); 117 118 void (*disable_symclk32_le)( 119 struct dccg *dccg, 120 int hpo_le_inst); 121 122 void (*set_physymclk)( 123 struct dccg *dccg, 124 int phy_inst, 125 enum physymclk_clock_source clk_src, 126 bool force_enable); 127 128 void (*set_dtbclk_dto)( 129 struct dccg *dccg, 130 const struct dtbclk_dto_params *params); 131 132 void (*set_audio_dtbclk_dto)( 133 struct dccg *dccg, 134 const struct dtbclk_dto_params *params); 135 136 void (*set_dispclk_change_mode)( 137 struct dccg *dccg, 138 enum dentist_dispclk_change_mode change_mode); 139 140 void (*disable_dsc)( 141 struct dccg *dccg, 142 int inst); 143 144 void (*enable_dsc)( 145 struct dccg *dccg, 146 int inst); 147 148 void (*set_pixel_rate_div)( 149 struct dccg *dccg, 150 uint32_t otg_inst, 151 enum pixel_rate_div k1, 152 enum pixel_rate_div k2); 153 154 void (*set_valid_pixel_rate)( 155 struct dccg *dccg, 156 int otg_inst, 157 int pixclk_khz); 158 159 }; 160 161 #endif //__DAL_DCCG_H__ 162