1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCCG_H__ 27 #define __DAL_DCCG_H__ 28 29 #include "dc_types.h" 30 #include "hw_shared.h" 31 32 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 33 enum phyd32clk_clock_source { 34 PHYD32CLKA, 35 PHYD32CLKB, 36 PHYD32CLKC, 37 PHYD32CLKD, 38 PHYD32CLKE, 39 PHYD32CLKF, 40 PHYD32CLKG, 41 }; 42 43 enum physymclk_clock_source { 44 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO. 45 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO. 46 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. 47 }; 48 49 enum hdmistreamclk_source { 50 REFCLK, // Selects REFCLK as source for hdmistreamclk. 51 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. 52 }; 53 54 enum dentist_dispclk_change_mode { 55 DISPCLK_CHANGE_MODE_IMMEDIATE, 56 DISPCLK_CHANGE_MODE_RAMPING, 57 }; 58 #endif 59 60 struct dccg { 61 struct dc_context *ctx; 62 const struct dccg_funcs *funcs; 63 int pipe_dppclk_khz[MAX_PIPES]; 64 int ref_dppclk; 65 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 66 int dtbclk_khz[MAX_PIPES]; 67 int audio_dtbclk_khz; 68 int ref_dtbclk_khz; 69 #endif 70 }; 71 72 struct dccg_funcs { 73 void (*update_dpp_dto)(struct dccg *dccg, 74 int dpp_inst, 75 int req_dppclk); 76 void (*get_dccg_ref_freq)(struct dccg *dccg, 77 unsigned int xtalin_freq_inKhz, 78 unsigned int *dccg_ref_freq_inKhz); 79 void (*dccg_init)(struct dccg *dccg); 80 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 81 82 void (*set_physymclk)( 83 struct dccg *dccg, 84 int phy_inst, 85 enum physymclk_clock_source clk_src, 86 bool force_enable); 87 88 void (*set_dtbclk_dto)( 89 struct dccg *dccg, 90 int dtbclk_inst, 91 int req_dtbclk_khz, 92 int num_odm_segments, 93 const struct dc_crtc_timing *timing); 94 95 void (*set_audio_dtbclk_dto)( 96 struct dccg *dccg, 97 uint32_t req_audio_dtbclk_khz); 98 99 void (*set_dispclk_change_mode)( 100 struct dccg *dccg, 101 enum dentist_dispclk_change_mode change_mode); 102 #endif 103 }; 104 105 #endif //__DAL_DCCG_H__ 106