1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_INTERNAL_H__ 27 #define __DAL_CLK_MGR_INTERNAL_H__ 28 29 #include "clk_mgr.h" 30 #include "dc.h" 31 32 /* 33 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also 34 * used in resource, perhaps this should be defined somewhere more common. 35 */ 36 #include "resource.h" 37 38 39 /* Starting DID for each range */ 40 enum dentist_base_divider_id { 41 DENTIST_BASE_DID_1 = 0x08, 42 DENTIST_BASE_DID_2 = 0x40, 43 DENTIST_BASE_DID_3 = 0x60, 44 DENTIST_BASE_DID_4 = 0x7e, 45 DENTIST_MAX_DID = 0x7f 46 }; 47 48 /* Starting point and step size for each divider range.*/ 49 enum dentist_divider_range { 50 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */ 51 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */ 52 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */ 53 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ 54 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ 55 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ 56 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */ 57 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */ 58 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 59 }; 60 61 /* 62 *************************************************************************************** 63 ****************** Clock Manager Private Macros and Defines *************************** 64 *************************************************************************************** 65 */ 66 67 /* Macros */ 68 69 #define TO_CLK_MGR_INTERNAL(clk_mgr)\ 70 container_of(clk_mgr, struct clk_mgr_internal, base) 71 72 #define CTX \ 73 clk_mgr->base.ctx 74 75 #define DC_LOGGER \ 76 clk_mgr->base.ctx->logger 77 78 79 80 81 #define CLK_BASE(inst) \ 82 CLK_BASE_INNER(inst) 83 84 #define CLK_SRI(reg_name, block, inst)\ 85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 86 mm ## block ## _ ## inst ## _ ## reg_name 87 88 #define CLK_COMMON_REG_LIST_DCE_BASE() \ 89 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ 90 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL 91 92 #define CLK_COMMON_REG_LIST_DCN_BASE() \ 93 SR(DENTIST_DISPCLK_CNTL) 94 95 #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \ 96 .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \ 97 .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ 98 .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67 99 100 #define CLK_REG_LIST_NV10() \ 101 SR(DENTIST_DISPCLK_CNTL), \ 102 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ 103 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) 104 105 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 106 // TODO: 107 #define CLK_REG_LIST_DCN3() \ 108 SR(DENTIST_DISPCLK_CNTL) 109 #endif 110 111 #define CLK_SF(reg_name, field_name, post_fix)\ 112 .field_name = reg_name ## __ ## field_name ## post_fix 113 114 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 115 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ 116 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) 117 118 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 119 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ 120 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) 121 122 #define CLK_MASK_SH_LIST_RV1(mask_sh) \ 123 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 124 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\ 125 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ 126 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), 127 128 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ 129 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 130 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ 131 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh) 132 133 #define CLK_MASK_SH_LIST_NV10(mask_sh) \ 134 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ 135 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ 136 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh) 137 138 #define CLK_REG_FIELD_LIST(type) \ 139 type DPREFCLK_SRC_SEL; \ 140 type DENTIST_DPREFCLK_WDIVIDER; \ 141 type DENTIST_DISPCLK_WDIVIDER; \ 142 type DENTIST_DISPCLK_CHG_DONE; 143 144 /* 145 *************************************************************************************** 146 ****************** Clock Manager Private Structures *********************************** 147 *************************************************************************************** 148 */ 149 #define CLK20_REG_FIELD_LIST(type) \ 150 type DENTIST_DPPCLK_WDIVIDER; \ 151 type DENTIST_DPPCLK_CHG_DONE; \ 152 type FbMult_int; \ 153 type FbMult_frac; 154 155 #define VBIOS_SMU_REG_FIELD_LIST(type) \ 156 type CONTENT; 157 158 struct clk_mgr_shift { 159 CLK_REG_FIELD_LIST(uint8_t) 160 CLK20_REG_FIELD_LIST(uint8_t) 161 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 162 }; 163 164 struct clk_mgr_mask { 165 CLK_REG_FIELD_LIST(uint32_t) 166 CLK20_REG_FIELD_LIST(uint32_t) 167 VBIOS_SMU_REG_FIELD_LIST(uint32_t) 168 }; 169 170 struct clk_mgr_registers { 171 uint32_t DPREFCLK_CNTL; 172 uint32_t DENTIST_DISPCLK_CNTL; 173 174 uint32_t CLK3_CLK2_DFS_CNTL; 175 uint32_t CLK3_CLK_PLL_REQ; 176 177 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 178 uint32_t CLK0_CLK2_DFS_CNTL; 179 uint32_t CLK0_CLK_PLL_REQ; 180 #endif 181 uint32_t MP1_SMN_C2PMSG_67; 182 uint32_t MP1_SMN_C2PMSG_83; 183 uint32_t MP1_SMN_C2PMSG_91; 184 }; 185 186 enum clock_type { 187 clock_type_dispclk = 1, 188 clock_type_dcfclk, 189 clock_type_socclk, 190 clock_type_pixelclk, 191 clock_type_phyclk, 192 clock_type_dppclk, 193 clock_type_fclk, 194 clock_type_dcfdsclk, 195 clock_type_dscclk, 196 clock_type_uclk, 197 clock_type_dramclk, 198 }; 199 200 201 struct state_dependent_clocks { 202 int display_clk_khz; 203 int pixel_clk_khz; 204 }; 205 206 struct clk_mgr_internal { 207 struct clk_mgr base; 208 int smu_ver; 209 struct pp_smu_funcs *pp_smu; 210 struct clk_mgr_internal_funcs *funcs; 211 212 struct dccg *dccg; 213 214 /* 215 * For backwards compatbility with previous implementation 216 * TODO: remove these after everything transitions to new pattern 217 * Rationale is that clk registers change a lot across DCE versions 218 * and a shared data structure doesn't really make sense. 219 */ 220 const struct clk_mgr_registers *regs; 221 const struct clk_mgr_shift *clk_mgr_shift; 222 const struct clk_mgr_mask *clk_mgr_mask; 223 224 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; 225 226 /*TODO: figure out which of the below fields should be here vs in asic specific portion */ 227 /* Cache the status of DFS-bypass feature*/ 228 bool dfs_bypass_enabled; 229 /* True if the DFS-bypass feature is enabled and active. */ 230 bool dfs_bypass_active; 231 232 uint32_t dfs_ref_freq_khz; 233 /* 234 * Cache the display clock returned by VBIOS if DFS-bypass is enabled. 235 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency 236 */ 237 int dfs_bypass_disp_clk; 238 239 /** 240 * @ss_on_dprefclk: 241 * 242 * True if spread spectrum is enabled on the DP ref clock. 243 */ 244 bool ss_on_dprefclk; 245 246 /** 247 * @xgmi_enabled: 248 * 249 * True if xGMI is enabled. On VG20, both audio and display clocks need 250 * to be adjusted with the WAFL link's SS info if xGMI is enabled. 251 */ 252 bool xgmi_enabled; 253 254 /** 255 * @dprefclk_ss_percentage: 256 * 257 * DPREFCLK SS percentage (if down-spread enabled). 258 * 259 * Note that if XGMI is enabled, the SS info (percentage and divider) 260 * from the WAFL link is used instead. This is decided during 261 * dce_clk_mgr initialization. 262 */ 263 int dprefclk_ss_percentage; 264 265 /** 266 * @dprefclk_ss_divider: 267 * 268 * DPREFCLK SS percentage Divider (100 or 1000). 269 */ 270 int dprefclk_ss_divider; 271 272 enum dm_pp_clocks_state max_clks_state; 273 enum dm_pp_clocks_state cur_min_clks_state; 274 bool periodic_retraining_disabled; 275 276 unsigned int cur_phyclk_req_table[MAX_PIPES * 2]; 277 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 278 279 bool smu_present; 280 void *wm_range_table; 281 long long wm_range_table_addr; 282 #endif 283 }; 284 285 struct clk_mgr_internal_funcs { 286 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 287 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr); 288 }; 289 290 291 /* 292 *************************************************************************************** 293 ****************** Clock Manager Level Helper functions ******************************* 294 *************************************************************************************** 295 */ 296 297 298 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) 299 { 300 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); 301 } 302 303 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) 304 { 305 if (cur_support != calc_support) { 306 if (calc_support == true && safe_to_lower) 307 return true; 308 else if (calc_support == false && !safe_to_lower) 309 return true; 310 } 311 312 return false; 313 } 314 315 int clk_mgr_helper_get_active_display_cnt( 316 struct dc *dc, 317 struct dc_state *context); 318 319 int clk_mgr_helper_get_active_plane_cnt( 320 struct dc *dc, 321 struct dc_state *context); 322 323 324 325 #endif //__DAL_CLK_MGR_INTERNAL_H__ 326