1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 struct dcn3_clk_internal { 47 int dummy; 48 /*TODO: 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 55 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 60 */ 61 }; 62 63 struct dcn301_clk_internal { 64 int dummy; 65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 71 72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 76 }; 77 78 /* Will these bw structures be ASIC specific? */ 79 80 #define MAX_NUM_DPM_LVL 8 81 #define WM_SET_COUNT 4 82 83 84 struct clk_limit_table_entry { 85 unsigned int voltage; /* milivolts withh 2 fractional bits */ 86 unsigned int dcfclk_mhz; 87 unsigned int fclk_mhz; 88 unsigned int memclk_mhz; 89 unsigned int socclk_mhz; 90 unsigned int dtbclk_mhz; 91 unsigned int dispclk_mhz; 92 unsigned int dppclk_mhz; 93 unsigned int phyclk_mhz; 94 unsigned int phyclk_d18_mhz; 95 unsigned int wck_ratio; 96 }; 97 98 /* This table is contiguous */ 99 struct clk_limit_table { 100 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 101 unsigned int num_entries; 102 }; 103 104 struct wm_range_table_entry { 105 unsigned int wm_inst; 106 unsigned int wm_type; 107 double pstate_latency_us; 108 double sr_exit_time_us; 109 double sr_enter_plus_exit_time_us; 110 bool valid; 111 }; 112 113 struct nv_wm_range_entry { 114 bool valid; 115 116 struct { 117 uint8_t wm_type; 118 uint16_t min_dcfclk; 119 uint16_t max_dcfclk; 120 uint16_t min_uclk; 121 uint16_t max_uclk; 122 } pmfw_breakdown; 123 124 struct { 125 double pstate_latency_us; 126 double sr_exit_time_us; 127 double sr_enter_plus_exit_time_us; 128 } dml_input; 129 }; 130 131 struct clk_log_info { 132 bool enabled; 133 char *pBuf; 134 unsigned int bufSize; 135 unsigned int *sum_chars_printed; 136 }; 137 138 struct clk_state_registers_and_bypass { 139 uint32_t dcfclk; 140 uint32_t dcf_deep_sleep_divider; 141 uint32_t dcf_deep_sleep_allow; 142 uint32_t dprefclk; 143 uint32_t dispclk; 144 uint32_t dppclk; 145 146 uint32_t dppclk_bypass; 147 uint32_t dcfclk_bypass; 148 uint32_t dprefclk_bypass; 149 uint32_t dispclk_bypass; 150 }; 151 152 struct rv1_clk_internal { 153 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 154 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 155 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 156 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 157 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 158 159 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 160 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 161 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 162 }; 163 164 struct rn_clk_internal { 165 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 166 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 167 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 168 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 169 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 170 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 171 172 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 173 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 174 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 175 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 176 177 }; 178 179 /* For dtn logging and debugging */ 180 struct clk_state_registers { 181 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 182 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 183 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 184 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 185 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 186 }; 187 188 /* TODO: combine this with the above */ 189 struct clk_bypass { 190 uint32_t dcfclk_bypass; 191 uint32_t dispclk_pypass; 192 uint32_t dprefclk_bypass; 193 }; 194 /* 195 * This table is not contiguous, can have holes, each 196 * entry correspond to one set of WM. For example if 197 * we have 2 DPM and LPDDR, we will WM set A, B and 198 * D occupied, C will be emptry. 199 */ 200 struct wm_table { 201 union { 202 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 203 struct wm_range_table_entry entries[WM_SET_COUNT]; 204 }; 205 }; 206 207 struct dummy_pstate_entry { 208 unsigned int dram_speed_mts; 209 unsigned int dummy_pstate_latency_us; 210 }; 211 212 struct clk_bw_params { 213 unsigned int vram_type; 214 unsigned int num_channels; 215 unsigned int dispclk_vco_khz; 216 unsigned int dc_mode_softmax_memclk; 217 struct clk_limit_table clk_table; 218 struct wm_table wm_table; 219 struct dummy_pstate_entry dummy_pstate_table[4]; 220 }; 221 /* Public interfaces */ 222 223 struct clk_states { 224 uint32_t dprefclk_khz; 225 }; 226 227 struct clk_mgr_funcs { 228 /* 229 * This function should set new clocks based on the input "safe_to_lower". 230 * If safe_to_lower == false, then only clocks which are to be increased 231 * should changed. 232 * If safe_to_lower == true, then only clocks which are to be decreased 233 * should be changed. 234 */ 235 void (*update_clocks)(struct clk_mgr *clk_mgr, 236 struct dc_state *context, 237 bool safe_to_lower); 238 239 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 240 241 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 242 243 void (*init_clocks)(struct clk_mgr *clk_mgr); 244 245 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 246 void (*get_clock)(struct clk_mgr *clk_mgr, 247 struct dc_state *context, 248 enum dc_clock_type clock_type, 249 struct dc_clock_config *clock_cfg); 250 251 bool (*are_clock_states_equal) (struct dc_clocks *a, 252 struct dc_clocks *b); 253 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 254 255 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 256 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 257 /* 258 * Send message to PMFW to set hard min memclk frequency 259 * When current_mode = false, set DPM0 260 * When current_mode = true, set required clock for current mode 261 */ 262 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 263 264 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 265 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 266 267 /* Custom set a memclk freq range*/ 268 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 269 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 270 271 /* Get current memclk states from PMFW, update relevant structures */ 272 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 273 274 /* Get SMU present */ 275 bool (*is_smu_present)(struct clk_mgr *clk_mgr); 276 }; 277 278 struct clk_mgr { 279 struct dc_context *ctx; 280 struct clk_mgr_funcs *funcs; 281 struct dc_clocks clks; 282 bool psr_allow_active_cache; 283 bool force_smu_not_present; 284 bool dc_mode_softmax_enabled; 285 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 286 int dentist_vco_freq_khz; 287 struct clk_state_registers_and_bypass boot_snapshot; 288 struct clk_bw_params *bw_params; 289 struct pp_smu_wm_range_sets ranges; 290 }; 291 292 /* forward declarations */ 293 struct dccg; 294 295 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 296 297 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 298 299 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 300 301 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 302 303 #endif /* __DAL_CLK_MGR_H__ */ 304