1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 struct dcn3_clk_internal { 47 int dummy; 48 /*TODO: 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 55 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 60 */ 61 }; 62 63 struct dcn301_clk_internal { 64 int dummy; 65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 71 72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 76 }; 77 78 /* Will these bw structures be ASIC specific? */ 79 80 #define MAX_NUM_DPM_LVL 8 81 #define WM_SET_COUNT 4 82 83 84 struct clk_limit_table_entry { 85 unsigned int voltage; /* milivolts withh 2 fractional bits */ 86 unsigned int dcfclk_mhz; 87 unsigned int fclk_mhz; 88 unsigned int memclk_mhz; 89 unsigned int socclk_mhz; 90 unsigned int dtbclk_mhz; 91 unsigned int dispclk_mhz; 92 unsigned int dppclk_mhz; 93 unsigned int phyclk_mhz; 94 unsigned int wck_ratio; 95 }; 96 97 /* This table is contiguous */ 98 struct clk_limit_table { 99 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 100 unsigned int num_entries; 101 }; 102 103 struct wm_range_table_entry { 104 unsigned int wm_inst; 105 unsigned int wm_type; 106 double pstate_latency_us; 107 double sr_exit_time_us; 108 double sr_enter_plus_exit_time_us; 109 bool valid; 110 }; 111 112 struct nv_wm_range_entry { 113 bool valid; 114 115 struct { 116 uint8_t wm_type; 117 uint16_t min_dcfclk; 118 uint16_t max_dcfclk; 119 uint16_t min_uclk; 120 uint16_t max_uclk; 121 } pmfw_breakdown; 122 123 struct { 124 double pstate_latency_us; 125 double sr_exit_time_us; 126 double sr_enter_plus_exit_time_us; 127 } dml_input; 128 }; 129 130 struct clk_log_info { 131 bool enabled; 132 char *pBuf; 133 unsigned int bufSize; 134 unsigned int *sum_chars_printed; 135 }; 136 137 struct clk_state_registers_and_bypass { 138 uint32_t dcfclk; 139 uint32_t dcf_deep_sleep_divider; 140 uint32_t dcf_deep_sleep_allow; 141 uint32_t dprefclk; 142 uint32_t dispclk; 143 uint32_t dppclk; 144 145 uint32_t dppclk_bypass; 146 uint32_t dcfclk_bypass; 147 uint32_t dprefclk_bypass; 148 uint32_t dispclk_bypass; 149 }; 150 151 struct rv1_clk_internal { 152 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 153 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 154 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 155 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 156 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 157 158 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 159 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 160 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 161 }; 162 163 struct rn_clk_internal { 164 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 165 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 166 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 167 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 168 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 169 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 170 171 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 172 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 173 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 174 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 175 176 }; 177 178 /* For dtn logging and debugging */ 179 struct clk_state_registers { 180 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 181 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 182 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 183 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 184 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 185 }; 186 187 /* TODO: combine this with the above */ 188 struct clk_bypass { 189 uint32_t dcfclk_bypass; 190 uint32_t dispclk_pypass; 191 uint32_t dprefclk_bypass; 192 }; 193 /* 194 * This table is not contiguous, can have holes, each 195 * entry correspond to one set of WM. For example if 196 * we have 2 DPM and LPDDR, we will WM set A, B and 197 * D occupied, C will be emptry. 198 */ 199 struct wm_table { 200 union { 201 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 202 struct wm_range_table_entry entries[WM_SET_COUNT]; 203 }; 204 }; 205 206 struct dummy_pstate_entry { 207 unsigned int dram_speed_mts; 208 unsigned int dummy_pstate_latency_us; 209 }; 210 211 struct clk_bw_params { 212 unsigned int vram_type; 213 unsigned int num_channels; 214 unsigned int dispclk_vco_khz; 215 unsigned int dc_mode_softmax_memclk; 216 struct clk_limit_table clk_table; 217 struct wm_table wm_table; 218 struct dummy_pstate_entry dummy_pstate_table[4]; 219 }; 220 /* Public interfaces */ 221 222 struct clk_states { 223 uint32_t dprefclk_khz; 224 }; 225 226 struct clk_mgr_funcs { 227 /* 228 * This function should set new clocks based on the input "safe_to_lower". 229 * If safe_to_lower == false, then only clocks which are to be increased 230 * should changed. 231 * If safe_to_lower == true, then only clocks which are to be decreased 232 * should be changed. 233 */ 234 void (*update_clocks)(struct clk_mgr *clk_mgr, 235 struct dc_state *context, 236 bool safe_to_lower); 237 238 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 239 240 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 241 242 void (*init_clocks)(struct clk_mgr *clk_mgr); 243 244 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 245 void (*get_clock)(struct clk_mgr *clk_mgr, 246 struct dc_state *context, 247 enum dc_clock_type clock_type, 248 struct dc_clock_config *clock_cfg); 249 250 bool (*are_clock_states_equal) (struct dc_clocks *a, 251 struct dc_clocks *b); 252 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 253 254 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 255 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 256 /* 257 * Send message to PMFW to set hard min memclk frequency 258 * When current_mode = false, set DPM0 259 * When current_mode = true, set required clock for current mode 260 */ 261 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 262 263 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 264 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 265 266 /* Custom set a memclk freq range*/ 267 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 268 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); 269 270 /* Get current memclk states from PMFW, update relevant structures */ 271 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 272 273 /* Get SMU present */ 274 bool (*is_smu_present)(struct clk_mgr *clk_mgr); 275 }; 276 277 struct clk_mgr { 278 struct dc_context *ctx; 279 struct clk_mgr_funcs *funcs; 280 struct dc_clocks clks; 281 bool psr_allow_active_cache; 282 bool force_smu_not_present; 283 bool dc_mode_softmax_enabled; 284 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 285 int dentist_vco_freq_khz; 286 struct clk_state_registers_and_bypass boot_snapshot; 287 struct clk_bw_params *bw_params; 288 struct pp_smu_wm_range_sets ranges; 289 }; 290 291 /* forward declarations */ 292 struct dccg; 293 294 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 295 296 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 297 298 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 299 300 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 301 302 #endif /* __DAL_CLK_MGR_H__ */ 303