1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 struct dcn3_clk_internal { 47 int dummy; 48 /*TODO: 49 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 51 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 53 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 54 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 55 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 60 */ 61 }; 62 63 struct dcn301_clk_internal { 64 int dummy; 65 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 67 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 68 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 69 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 70 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 71 72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 76 }; 77 78 /* Will these bw structures be ASIC specific? */ 79 80 #define MAX_NUM_DPM_LVL 8 81 #define WM_SET_COUNT 4 82 83 84 struct clk_limit_table_entry { 85 unsigned int voltage; /* milivolts withh 2 fractional bits */ 86 unsigned int dcfclk_mhz; 87 unsigned int fclk_mhz; 88 unsigned int memclk_mhz; 89 unsigned int socclk_mhz; 90 unsigned int dtbclk_mhz; 91 unsigned int dispclk_mhz; 92 unsigned int dppclk_mhz; 93 unsigned int phyclk_mhz; 94 }; 95 96 /* This table is contiguous */ 97 struct clk_limit_table { 98 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 99 unsigned int num_entries; 100 }; 101 102 struct wm_range_table_entry { 103 unsigned int wm_inst; 104 unsigned int wm_type; 105 double pstate_latency_us; 106 double sr_exit_time_us; 107 double sr_enter_plus_exit_time_us; 108 bool valid; 109 }; 110 111 struct nv_wm_range_entry { 112 bool valid; 113 114 struct { 115 uint8_t wm_type; 116 uint16_t min_dcfclk; 117 uint16_t max_dcfclk; 118 uint16_t min_uclk; 119 uint16_t max_uclk; 120 } pmfw_breakdown; 121 122 struct { 123 double pstate_latency_us; 124 double sr_exit_time_us; 125 double sr_enter_plus_exit_time_us; 126 } dml_input; 127 }; 128 129 struct clk_log_info { 130 bool enabled; 131 char *pBuf; 132 unsigned int bufSize; 133 unsigned int *sum_chars_printed; 134 }; 135 136 struct clk_state_registers_and_bypass { 137 uint32_t dcfclk; 138 uint32_t dcf_deep_sleep_divider; 139 uint32_t dcf_deep_sleep_allow; 140 uint32_t dprefclk; 141 uint32_t dispclk; 142 uint32_t dppclk; 143 144 uint32_t dppclk_bypass; 145 uint32_t dcfclk_bypass; 146 uint32_t dprefclk_bypass; 147 uint32_t dispclk_bypass; 148 }; 149 150 struct rv1_clk_internal { 151 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 152 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 153 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 154 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 155 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 156 157 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 158 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 159 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 160 }; 161 162 struct rn_clk_internal { 163 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 164 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 165 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 166 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 167 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 168 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 169 170 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 171 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 172 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 173 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 174 175 }; 176 177 /* For dtn logging and debugging */ 178 struct clk_state_registers { 179 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 180 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 181 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 182 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 183 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 184 }; 185 186 /* TODO: combine this with the above */ 187 struct clk_bypass { 188 uint32_t dcfclk_bypass; 189 uint32_t dispclk_pypass; 190 uint32_t dprefclk_bypass; 191 }; 192 /* 193 * This table is not contiguous, can have holes, each 194 * entry correspond to one set of WM. For example if 195 * we have 2 DPM and LPDDR, we will WM set A, B and 196 * D occupied, C will be emptry. 197 */ 198 struct wm_table { 199 union { 200 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 201 struct wm_range_table_entry entries[WM_SET_COUNT]; 202 }; 203 }; 204 205 struct dummy_pstate_entry { 206 unsigned int dram_speed_mts; 207 unsigned int dummy_pstate_latency_us; 208 }; 209 210 struct clk_bw_params { 211 unsigned int vram_type; 212 unsigned int num_channels; 213 struct clk_limit_table clk_table; 214 struct wm_table wm_table; 215 struct dummy_pstate_entry dummy_pstate_table[4]; 216 }; 217 /* Public interfaces */ 218 219 struct clk_states { 220 uint32_t dprefclk_khz; 221 }; 222 223 struct clk_mgr_funcs { 224 /* 225 * This function should set new clocks based on the input "safe_to_lower". 226 * If safe_to_lower == false, then only clocks which are to be increased 227 * should changed. 228 * If safe_to_lower == true, then only clocks which are to be decreased 229 * should be changed. 230 */ 231 void (*update_clocks)(struct clk_mgr *clk_mgr, 232 struct dc_state *context, 233 bool safe_to_lower); 234 235 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 236 237 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 238 239 void (*init_clocks)(struct clk_mgr *clk_mgr); 240 241 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 242 void (*get_clock)(struct clk_mgr *clk_mgr, 243 struct dc_state *context, 244 enum dc_clock_type clock_type, 245 struct dc_clock_config *clock_cfg); 246 247 bool (*are_clock_states_equal) (struct dc_clocks *a, 248 struct dc_clocks *b); 249 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 250 251 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 252 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 253 /* 254 * Send message to PMFW to set hard min memclk frequency 255 * When current_mode = false, set DPM0 256 * When current_mode = true, set required clock for current mode 257 */ 258 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 259 260 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 261 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 262 263 /* Get current memclk states from PMFW, update relevant structures */ 264 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 265 }; 266 267 struct dpm_clocks; 268 struct wartermarks; 269 270 struct smu_watermark_set { 271 struct watermarks *wm_set; 272 union large_integer mc_address; 273 }; 274 275 struct clk_mgr { 276 struct dc_context *ctx; 277 struct clk_mgr_funcs *funcs; 278 struct dc_clocks clks; 279 bool psr_allow_active_cache; 280 bool force_smu_not_present; 281 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 282 int dentist_vco_freq_khz; 283 struct clk_state_registers_and_bypass boot_snapshot; 284 struct clk_bw_params *bw_params; 285 struct pp_smu_wm_range_sets ranges; 286 struct smu_watermark_set smu_wm_set; 287 }; 288 289 /* forward declarations */ 290 struct dccg; 291 292 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 293 294 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 295 296 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 297 298 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 299 300 #endif /* __DAL_CLK_MGR_H__ */ 301