1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN) 37 #include "mpc.h" 38 #endif 39 #include "dwb.h" 40 #include "mcif_wb.h" 41 #include "panel_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 58 /************ link *****************/ 59 struct link_init_data { 60 const struct dc *dc; 61 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 62 uint32_t connector_index; /* this will be mapped to the HPD pins */ 63 uint32_t link_index; /* this is mapped to DAL display_index 64 TODO: remove it when DC is complete. */ 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "transform.h" 86 #include "dpp.h" 87 88 struct resource_pool; 89 struct dc_state; 90 struct resource_context; 91 struct clk_bw_params; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct panel_cntl*(*panel_cntl_create)( 97 const struct panel_cntl_init_data *panel_cntl_init_data); 98 struct link_encoder *(*link_enc_create)( 99 const struct encoder_init_data *init); 100 bool (*validate_bandwidth)( 101 struct dc *dc, 102 struct dc_state *context, 103 bool fast_validate); 104 void (*calculate_wm_and_dlg)( 105 struct dc *dc, struct dc_state *context, 106 display_e2e_pipe_params_st *pipes, 107 int pipe_cnt, 108 int vlevel); 109 int (*populate_dml_pipes)( 110 struct dc *dc, 111 struct dc_state *context, 112 display_e2e_pipe_params_st *pipes, 113 bool fast_validate); 114 115 enum dc_status (*validate_global)( 116 struct dc *dc, 117 struct dc_state *context); 118 119 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 120 struct dc_state *context, 121 const struct resource_pool *pool, 122 struct dc_stream_state *stream); 123 124 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 125 126 enum dc_status (*add_stream_to_ctx)( 127 struct dc *dc, 128 struct dc_state *new_ctx, 129 struct dc_stream_state *dc_stream); 130 131 enum dc_status (*remove_stream_from_ctx)( 132 struct dc *dc, 133 struct dc_state *new_ctx, 134 struct dc_stream_state *stream); 135 enum dc_status (*patch_unknown_plane_state)( 136 struct dc_plane_state *plane_state); 137 138 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 139 struct resource_context *res_ctx, 140 const struct resource_pool *pool, 141 struct dc_stream_state *stream); 142 void (*populate_dml_writeback_from_context)( 143 struct dc *dc, 144 struct resource_context *res_ctx, 145 display_e2e_pipe_params_st *pipes); 146 147 void (*set_mcif_arb_params)( 148 struct dc *dc, 149 struct dc_state *context, 150 display_e2e_pipe_params_st *pipes, 151 int pipe_cnt); 152 void (*update_bw_bounding_box)( 153 struct dc *dc, 154 struct clk_bw_params *bw_params); 155 #if defined(CONFIG_DRM_AMD_DC_DCN) 156 bool (*acquire_post_bldn_3dlut)( 157 struct resource_context *res_ctx, 158 const struct resource_pool *pool, 159 int mpcc_id, 160 struct dc_3dlut **lut, 161 struct dc_transfer_func **shaper); 162 163 bool (*release_post_bldn_3dlut)( 164 struct resource_context *res_ctx, 165 const struct resource_pool *pool, 166 struct dc_3dlut **lut, 167 struct dc_transfer_func **shaper); 168 #endif 169 enum dc_status (*add_dsc_to_stream_resource)( 170 struct dc *dc, struct dc_state *state, 171 struct dc_stream_state *stream); 172 }; 173 174 struct audio_support{ 175 bool dp_audio; 176 bool hdmi_audio_on_dongle; 177 bool hdmi_audio_native; 178 }; 179 180 #define NO_UNDERLAY_PIPE -1 181 182 struct resource_pool { 183 struct mem_input *mis[MAX_PIPES]; 184 struct hubp *hubps[MAX_PIPES]; 185 struct input_pixel_processor *ipps[MAX_PIPES]; 186 struct transform *transforms[MAX_PIPES]; 187 struct dpp *dpps[MAX_PIPES]; 188 struct output_pixel_processor *opps[MAX_PIPES]; 189 struct timing_generator *timing_generators[MAX_PIPES]; 190 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 191 struct hubbub *hubbub; 192 struct mpc *mpc; 193 struct pp_smu_funcs *pp_smu; 194 struct dce_aux *engines[MAX_PIPES]; 195 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 196 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 197 bool i2c_hw_buffer_in_use; 198 199 struct dwbc *dwbc[MAX_DWB_PIPES]; 200 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 201 struct { 202 unsigned int gsl_0:1; 203 unsigned int gsl_1:1; 204 unsigned int gsl_2:1; 205 } gsl_groups; 206 207 struct display_stream_compressor *dscs[MAX_PIPES]; 208 209 unsigned int pipe_count; 210 unsigned int underlay_pipe_index; 211 unsigned int stream_enc_count; 212 213 #if defined(CONFIG_DRM_AMD_DC_DCN) 214 struct dc_3dlut *mpc_lut[MAX_PIPES]; 215 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 216 #endif 217 struct { 218 unsigned int xtalin_clock_inKhz; 219 unsigned int dccg_ref_clock_inKhz; 220 unsigned int dchub_ref_clock_inKhz; 221 } ref_clocks; 222 unsigned int timing_generator_count; 223 unsigned int mpcc_count; 224 225 unsigned int writeback_pipe_count; 226 /* 227 * reserved clock source for DP 228 */ 229 struct clock_source *dp_clock_source; 230 231 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 232 unsigned int clk_src_count; 233 234 struct audio *audios[MAX_AUDIOS]; 235 unsigned int audio_count; 236 struct audio_support audio_support; 237 238 struct dccg *dccg; 239 struct irq_service *irqs; 240 241 struct abm *abm; 242 struct dmcu *dmcu; 243 struct dmub_psr *psr; 244 245 #if defined(CONFIG_DRM_AMD_DC_DCN) 246 struct abm *multiple_abms[MAX_PIPES]; 247 #endif 248 249 const struct resource_funcs *funcs; 250 const struct resource_caps *res_cap; 251 252 struct ddc_service *oem_device; 253 }; 254 255 struct dcn_fe_bandwidth { 256 int dppclk_khz; 257 258 }; 259 260 struct stream_resource { 261 struct output_pixel_processor *opp; 262 struct display_stream_compressor *dsc; 263 struct timing_generator *tg; 264 struct stream_encoder *stream_enc; 265 struct audio *audio; 266 267 struct pixel_clk_params pix_clk_params; 268 struct encoder_info_frame encoder_info_frame; 269 270 struct abm *abm; 271 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 272 * otherwise it's using group number 'gsl_group-1' 273 */ 274 uint8_t gsl_group; 275 }; 276 277 struct plane_resource { 278 struct scaler_data scl_data; 279 struct hubp *hubp; 280 struct mem_input *mi; 281 struct input_pixel_processor *ipp; 282 struct transform *xfm; 283 struct dpp *dpp; 284 uint8_t mpcc_inst; 285 286 struct dcn_fe_bandwidth bw; 287 }; 288 289 union pipe_update_flags { 290 struct { 291 uint32_t enable : 1; 292 uint32_t disable : 1; 293 uint32_t odm : 1; 294 uint32_t global_sync : 1; 295 uint32_t opp_changed : 1; 296 uint32_t tg_changed : 1; 297 uint32_t mpcc : 1; 298 uint32_t dppclk : 1; 299 uint32_t hubp_interdependent : 1; 300 uint32_t hubp_rq_dlg_ttu : 1; 301 uint32_t gamut_remap : 1; 302 uint32_t scaler : 1; 303 uint32_t viewport : 1; 304 uint32_t plane_changed : 1; 305 } bits; 306 uint32_t raw; 307 }; 308 309 struct pipe_ctx { 310 struct dc_plane_state *plane_state; 311 struct dc_stream_state *stream; 312 313 struct plane_resource plane_res; 314 struct stream_resource stream_res; 315 316 struct clock_source *clock_source; 317 318 struct pll_settings pll_settings; 319 320 uint8_t pipe_idx; 321 322 struct pipe_ctx *top_pipe; 323 struct pipe_ctx *bottom_pipe; 324 struct pipe_ctx *next_odm_pipe; 325 struct pipe_ctx *prev_odm_pipe; 326 327 #ifdef CONFIG_DRM_AMD_DC_DCN 328 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 329 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 330 struct _vcs_dpi_display_rq_regs_st rq_regs; 331 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 332 #endif 333 union pipe_update_flags update_flags; 334 struct dwbc *dwbc; 335 struct mcif_wb *mcif_wb; 336 bool vtp_locked; 337 }; 338 339 struct resource_context { 340 struct pipe_ctx pipe_ctx[MAX_PIPES]; 341 bool is_stream_enc_acquired[MAX_PIPES * 2]; 342 bool is_audio_acquired[MAX_PIPES]; 343 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 344 uint8_t dp_clock_source_ref_count; 345 bool is_dsc_acquired[MAX_PIPES]; 346 #if defined(CONFIG_DRM_AMD_DC_DCN) 347 bool is_mpc_3dlut_acquired[MAX_PIPES]; 348 #endif 349 }; 350 351 struct dce_bw_output { 352 bool cpuc_state_change_enable; 353 bool cpup_state_change_enable; 354 bool stutter_mode_enable; 355 bool nbp_state_change_enable; 356 bool all_displays_in_sync; 357 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 358 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 359 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 360 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 361 int sclk_khz; 362 int sclk_deep_sleep_khz; 363 int yclk_khz; 364 int dispclk_khz; 365 int blackout_recovery_time_us; 366 }; 367 368 struct dcn_bw_writeback { 369 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 370 }; 371 372 struct dcn_bw_output { 373 struct dc_clocks clk; 374 struct dcn_watermark_set watermarks; 375 struct dcn_bw_writeback bw_writeback; 376 }; 377 378 union bw_output { 379 struct dcn_bw_output dcn; 380 struct dce_bw_output dce; 381 }; 382 383 struct bw_context { 384 union bw_output bw; 385 struct display_mode_lib dml; 386 }; 387 /** 388 * struct dc_state - The full description of a state requested by a user 389 * 390 * @streams: Stream properties 391 * @stream_status: The planes on a given stream 392 * @res_ctx: Persistent state of resources 393 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 394 * @pp_display_cfg: PowerPlay clocks and settings 395 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 396 * 397 */ 398 struct dc_state { 399 struct dc_stream_state *streams[MAX_PIPES]; 400 struct dc_stream_status stream_status[MAX_PIPES]; 401 uint8_t stream_count; 402 uint8_t stream_mask; 403 404 struct resource_context res_ctx; 405 406 struct bw_context bw_ctx; 407 408 /* Note: these are big structures, do *not* put on stack! */ 409 struct dm_pp_display_configuration pp_display_cfg; 410 #ifdef CONFIG_DRM_AMD_DC_DCN 411 struct dcn_bw_internal_vars dcn_bw_vars; 412 #endif 413 414 struct clk_mgr *clk_mgr; 415 416 struct kref refcount; 417 418 struct { 419 unsigned int stutter_period_us; 420 } perf_params; 421 }; 422 423 #endif /* _CORE_TYPES_H_ */ 424