1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 41 #define MAX_CLOCK_SOURCES 7 42 #define MAX_SVP_PHANTOM_STREAMS 2 43 #define MAX_SVP_PHANTOM_PLANES 2 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #include "dm_cp_psp.h" 55 #include "link_hwss.h" 56 57 /********** DAL Core*********************/ 58 #include "transform.h" 59 #include "dpp.h" 60 61 struct resource_pool; 62 struct dc_state; 63 struct resource_context; 64 struct clk_bw_params; 65 66 struct resource_funcs { 67 void (*destroy)(struct resource_pool **pool); 68 void (*link_init)(struct dc_link *link); 69 struct panel_cntl*(*panel_cntl_create)( 70 const struct panel_cntl_init_data *panel_cntl_init_data); 71 struct link_encoder *(*link_enc_create)( 72 struct dc_context *ctx, 73 const struct encoder_init_data *init); 74 /* Create a minimal link encoder object with no dc_link object 75 * associated with it. */ 76 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 77 78 bool (*validate_bandwidth)( 79 struct dc *dc, 80 struct dc_state *context, 81 bool fast_validate); 82 void (*calculate_wm_and_dlg)( 83 struct dc *dc, struct dc_state *context, 84 display_e2e_pipe_params_st *pipes, 85 int pipe_cnt, 86 int vlevel); 87 void (*update_soc_for_wm_a)( 88 struct dc *dc, struct dc_state *context); 89 90 /** 91 * @populate_dml_pipes - Populate pipe data struct 92 * 93 * Returns: 94 * Total of pipes available in the specific ASIC. 95 */ 96 int (*populate_dml_pipes)( 97 struct dc *dc, 98 struct dc_state *context, 99 display_e2e_pipe_params_st *pipes, 100 bool fast_validate); 101 102 /* 103 * Algorithm for assigning available link encoders to links. 104 * 105 * Update link_enc_assignments table and link_enc_avail list accordingly in 106 * struct resource_context. 107 */ 108 void (*link_encs_assign)( 109 struct dc *dc, 110 struct dc_state *state, 111 struct dc_stream_state *streams[], 112 uint8_t stream_count); 113 /* 114 * Unassign a link encoder from a stream. 115 * 116 * Update link_enc_assignments table and link_enc_avail list accordingly in 117 * struct resource_context. 118 */ 119 void (*link_enc_unassign)( 120 struct dc_state *state, 121 struct dc_stream_state *stream); 122 123 enum dc_status (*validate_global)( 124 struct dc *dc, 125 struct dc_state *context); 126 127 /* 128 * Acquires a free pipe for the head pipe. 129 * The head pipe is first pipe in the current context that matches the stream 130 * and does not have a top pipe or prev_odm_pipe. 131 */ 132 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 133 struct dc_state *context, 134 const struct resource_pool *pool, 135 struct dc_stream_state *stream); 136 137 /* 138 * Acquires a free pipe for the head pipe with some additional checks for odm. 139 * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer 140 * where it is read from the context. So this allows us look for different 141 * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have 142 * a left and right pipe ). 143 * 144 * It also checks the old context to see if: 145 * 146 * 1. a pipe has already been allocated for the head pipe. If so, it will 147 * try to select that pipe as the idle pipe if it is available in the current 148 * context. 149 * 2. if the head_pipe is on the left, it will check if the right pipe has 150 * a pipe already allocated. If so, it will not use that pipe if it is 151 * selected as the idle pipe. 152 */ 153 struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)( 154 struct dc_state *context, 155 const struct resource_pool *pool, 156 struct dc_stream_state *stream, 157 struct pipe_ctx *head_pipe); 158 159 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 160 161 enum dc_status (*add_stream_to_ctx)( 162 struct dc *dc, 163 struct dc_state *new_ctx, 164 struct dc_stream_state *dc_stream); 165 166 enum dc_status (*remove_stream_from_ctx)( 167 struct dc *dc, 168 struct dc_state *new_ctx, 169 struct dc_stream_state *stream); 170 enum dc_status (*patch_unknown_plane_state)( 171 struct dc_plane_state *plane_state); 172 173 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 174 struct resource_context *res_ctx, 175 const struct resource_pool *pool, 176 struct dc_stream_state *stream); 177 void (*populate_dml_writeback_from_context)( 178 struct dc *dc, 179 struct resource_context *res_ctx, 180 display_e2e_pipe_params_st *pipes); 181 182 void (*set_mcif_arb_params)( 183 struct dc *dc, 184 struct dc_state *context, 185 display_e2e_pipe_params_st *pipes, 186 int pipe_cnt); 187 void (*update_bw_bounding_box)( 188 struct dc *dc, 189 struct clk_bw_params *bw_params); 190 bool (*acquire_post_bldn_3dlut)( 191 struct resource_context *res_ctx, 192 const struct resource_pool *pool, 193 int mpcc_id, 194 struct dc_3dlut **lut, 195 struct dc_transfer_func **shaper); 196 197 bool (*release_post_bldn_3dlut)( 198 struct resource_context *res_ctx, 199 const struct resource_pool *pool, 200 struct dc_3dlut **lut, 201 struct dc_transfer_func **shaper); 202 203 enum dc_status (*add_dsc_to_stream_resource)( 204 struct dc *dc, struct dc_state *state, 205 struct dc_stream_state *stream); 206 207 void (*add_phantom_pipes)( 208 struct dc *dc, 209 struct dc_state *context, 210 display_e2e_pipe_params_st *pipes, 211 unsigned int pipe_cnt, 212 unsigned int index); 213 214 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update); 215 void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 216 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 217 void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 218 void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 219 }; 220 221 struct audio_support{ 222 bool dp_audio; 223 bool hdmi_audio_on_dongle; 224 bool hdmi_audio_native; 225 }; 226 227 #define NO_UNDERLAY_PIPE -1 228 229 struct resource_pool { 230 struct mem_input *mis[MAX_PIPES]; 231 struct hubp *hubps[MAX_PIPES]; 232 struct input_pixel_processor *ipps[MAX_PIPES]; 233 struct transform *transforms[MAX_PIPES]; 234 struct dpp *dpps[MAX_PIPES]; 235 struct output_pixel_processor *opps[MAX_PIPES]; 236 struct timing_generator *timing_generators[MAX_PIPES]; 237 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 238 struct hubbub *hubbub; 239 struct mpc *mpc; 240 struct pp_smu_funcs *pp_smu; 241 struct dce_aux *engines[MAX_PIPES]; 242 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 243 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 244 bool i2c_hw_buffer_in_use; 245 246 struct dwbc *dwbc[MAX_DWB_PIPES]; 247 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 248 struct { 249 unsigned int gsl_0:1; 250 unsigned int gsl_1:1; 251 unsigned int gsl_2:1; 252 } gsl_groups; 253 254 struct display_stream_compressor *dscs[MAX_PIPES]; 255 256 unsigned int pipe_count; 257 unsigned int underlay_pipe_index; 258 unsigned int stream_enc_count; 259 260 /* An array for accessing the link encoder objects that have been created. 261 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 262 */ 263 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 264 /* Number of DIG link encoder objects created - i.e. number of valid 265 * entries in link_encoders array. 266 */ 267 unsigned int dig_link_enc_count; 268 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 269 unsigned int usb4_dpia_count; 270 271 unsigned int hpo_dp_stream_enc_count; 272 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 273 unsigned int hpo_dp_link_enc_count; 274 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 275 struct dc_3dlut *mpc_lut[MAX_PIPES]; 276 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 277 278 struct { 279 unsigned int xtalin_clock_inKhz; 280 unsigned int dccg_ref_clock_inKhz; 281 unsigned int dchub_ref_clock_inKhz; 282 } ref_clocks; 283 unsigned int timing_generator_count; 284 unsigned int mpcc_count; 285 286 unsigned int writeback_pipe_count; 287 /* 288 * reserved clock source for DP 289 */ 290 struct clock_source *dp_clock_source; 291 292 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 293 unsigned int clk_src_count; 294 295 struct audio *audios[MAX_AUDIOS]; 296 unsigned int audio_count; 297 struct audio_support audio_support; 298 299 struct dccg *dccg; 300 struct irq_service *irqs; 301 302 struct abm *abm; 303 struct dmcu *dmcu; 304 struct dmub_psr *psr; 305 306 struct abm *multiple_abms[MAX_PIPES]; 307 308 const struct resource_funcs *funcs; 309 const struct resource_caps *res_cap; 310 311 struct ddc_service *oem_device; 312 }; 313 314 struct dcn_fe_bandwidth { 315 int dppclk_khz; 316 317 }; 318 319 struct stream_resource { 320 struct output_pixel_processor *opp; 321 struct display_stream_compressor *dsc; 322 struct timing_generator *tg; 323 struct stream_encoder *stream_enc; 324 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 325 struct audio *audio; 326 327 struct pixel_clk_params pix_clk_params; 328 struct encoder_info_frame encoder_info_frame; 329 330 struct abm *abm; 331 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 332 * otherwise it's using group number 'gsl_group-1' 333 */ 334 uint8_t gsl_group; 335 }; 336 337 struct plane_resource { 338 struct scaler_data scl_data; 339 struct hubp *hubp; 340 struct mem_input *mi; 341 struct input_pixel_processor *ipp; 342 struct transform *xfm; 343 struct dpp *dpp; 344 uint8_t mpcc_inst; 345 346 struct dcn_fe_bandwidth bw; 347 }; 348 349 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 350 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 351 352 /* all mappable hardware resources used to enable a link */ 353 struct link_resource { 354 struct hpo_dp_link_encoder *hpo_dp_link_enc; 355 }; 356 357 struct link_config { 358 struct dc_link_settings dp_link_settings; 359 }; 360 union pipe_update_flags { 361 struct { 362 uint32_t enable : 1; 363 uint32_t disable : 1; 364 uint32_t odm : 1; 365 uint32_t global_sync : 1; 366 uint32_t opp_changed : 1; 367 uint32_t tg_changed : 1; 368 uint32_t mpcc : 1; 369 uint32_t dppclk : 1; 370 uint32_t hubp_interdependent : 1; 371 uint32_t hubp_rq_dlg_ttu : 1; 372 uint32_t gamut_remap : 1; 373 uint32_t scaler : 1; 374 uint32_t viewport : 1; 375 uint32_t plane_changed : 1; 376 uint32_t det_size : 1; 377 } bits; 378 uint32_t raw; 379 }; 380 381 struct pipe_ctx { 382 struct dc_plane_state *plane_state; 383 struct dc_stream_state *stream; 384 385 struct plane_resource plane_res; 386 387 /** 388 * @stream_res: Reference to DCN resource components such OPP and DSC. 389 */ 390 struct stream_resource stream_res; 391 struct link_resource link_res; 392 393 struct clock_source *clock_source; 394 395 struct pll_settings pll_settings; 396 397 /** 398 * @link_config: 399 * 400 * link config records software decision for what link config should be 401 * enabled given current link capability and stream during hw resource 402 * mapping. This is to decouple the dependency on link capability during 403 * dc commit or update. 404 */ 405 struct link_config link_config; 406 407 uint8_t pipe_idx; 408 uint8_t pipe_idx_syncd; 409 410 struct pipe_ctx *top_pipe; 411 struct pipe_ctx *bottom_pipe; 412 struct pipe_ctx *next_odm_pipe; 413 struct pipe_ctx *prev_odm_pipe; 414 415 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 416 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 417 struct _vcs_dpi_display_rq_regs_st rq_regs; 418 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 419 struct _vcs_dpi_display_rq_params_st dml_rq_param; 420 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 421 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 422 int det_buffer_size_kb; 423 bool unbounded_req; 424 unsigned int surface_size_in_mall_bytes; 425 426 struct dwbc *dwbc; 427 struct mcif_wb *mcif_wb; 428 union pipe_update_flags update_flags; 429 }; 430 431 /* Data used for dynamic link encoder assignment. 432 * Tracks current and future assignments; available link encoders; 433 * and mode of operation (whether to use current or future assignments). 434 */ 435 struct link_enc_cfg_context { 436 enum link_enc_cfg_mode mode; 437 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 438 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 439 struct link_enc_assignment transient_assignments[MAX_PIPES]; 440 }; 441 442 struct resource_context { 443 struct pipe_ctx pipe_ctx[MAX_PIPES]; 444 bool is_stream_enc_acquired[MAX_PIPES * 2]; 445 bool is_audio_acquired[MAX_PIPES]; 446 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 447 uint8_t dp_clock_source_ref_count; 448 bool is_dsc_acquired[MAX_PIPES]; 449 struct link_enc_cfg_context link_enc_cfg_ctx; 450 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 451 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 452 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 453 bool is_mpc_3dlut_acquired[MAX_PIPES]; 454 }; 455 456 struct dce_bw_output { 457 bool cpuc_state_change_enable; 458 bool cpup_state_change_enable; 459 bool stutter_mode_enable; 460 bool nbp_state_change_enable; 461 bool all_displays_in_sync; 462 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 463 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 464 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 465 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 466 int sclk_khz; 467 int sclk_deep_sleep_khz; 468 int yclk_khz; 469 int dispclk_khz; 470 int blackout_recovery_time_us; 471 }; 472 473 struct dcn_bw_writeback { 474 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 475 }; 476 477 struct dcn_bw_output { 478 struct dc_clocks clk; 479 struct dcn_watermark_set watermarks; 480 struct dcn_bw_writeback bw_writeback; 481 int compbuf_size_kb; 482 unsigned int mall_ss_size_bytes; 483 unsigned int mall_ss_psr_active_size_bytes; 484 unsigned int mall_subvp_size_bytes; 485 unsigned int legacy_svp_drr_stream_index; 486 bool legacy_svp_drr_stream_index_valid; 487 }; 488 489 union bw_output { 490 struct dcn_bw_output dcn; 491 struct dce_bw_output dce; 492 }; 493 494 struct bw_context { 495 union bw_output bw; 496 struct display_mode_lib dml; 497 }; 498 499 /** 500 * struct dc_state - The full description of a state requested by users 501 */ 502 struct dc_state { 503 /** 504 * @streams: Stream state properties 505 */ 506 struct dc_stream_state *streams[MAX_PIPES]; 507 508 /** 509 * @stream_status: Planes status on a given stream 510 */ 511 struct dc_stream_status stream_status[MAX_PIPES]; 512 513 /** 514 * @stream_count: Total of streams in use 515 */ 516 uint8_t stream_count; 517 uint8_t stream_mask; 518 519 /** 520 * @res_ctx: Persistent state of resources 521 */ 522 struct resource_context res_ctx; 523 524 /** 525 * @pp_display_cfg: PowerPlay clocks and settings 526 * Note: this is a big struct, do *not* put on stack! 527 */ 528 struct dm_pp_display_configuration pp_display_cfg; 529 530 /** 531 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 532 * Note: this is a big struct, do *not* put on stack! 533 */ 534 struct dcn_bw_internal_vars dcn_bw_vars; 535 536 struct clk_mgr *clk_mgr; 537 538 /** 539 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 540 * 541 * Each context must have its own instance of VBA, and in order to 542 * initialize and obtain IP and SOC, the base DML instance from DC is 543 * initially copied into every context. 544 */ 545 struct bw_context bw_ctx; 546 547 /** 548 * @refcount: refcount reference 549 * 550 * Notice that dc_state is used around the code to capture the current 551 * context, so we need to pass it everywhere. That's why we want to use 552 * kref in this struct. 553 */ 554 struct kref refcount; 555 556 struct { 557 unsigned int stutter_period_us; 558 } perf_params; 559 }; 560 561 struct dc_bounding_box_max_clk { 562 int max_dcfclk_mhz; 563 int max_dispclk_mhz; 564 int max_dppclk_mhz; 565 int max_phyclk_mhz; 566 }; 567 568 #endif /* _CORE_TYPES_H_ */ 569