14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36ff5ef992SAlex Deucher #include "mpc.h" 37345429a6SHarry Wentland #include "dwb.h" 38345429a6SHarry Wentland #include "mcif_wb.h" 39d4caa72eSAnthony Koo #include "panel_cntl.h" 404562236bSHarry Wentland 414562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 4220dad381SJun Lei #define MAX_SVP_PHANTOM_STREAMS 2 4320dad381SJun Lei #define MAX_SVP_PHANTOM_PLANES 2 444562236bSHarry Wentland 453be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 464562236bSHarry Wentland uint32_t controller_id); 474562236bSHarry Wentland 484562236bSHarry Wentland #include "grph_object_id.h" 494562236bSHarry Wentland #include "link_encoder.h" 504562236bSHarry Wentland #include "stream_encoder.h" 514562236bSHarry Wentland #include "clock_source.h" 524562236bSHarry Wentland #include "audio.h" 53a185048cSTony Cheng #include "dm_pp_smu.h" 54d462fcf5SBhawanpreet Lakha #ifdef CONFIG_DRM_AMD_DC_HDCP 55d462fcf5SBhawanpreet Lakha #include "dm_cp_psp.h" 56d462fcf5SBhawanpreet Lakha #endif 57fd249266SWenjing Liu #include "link_hwss.h" 584562236bSHarry Wentland 594562236bSHarry Wentland /************ link *****************/ 604562236bSHarry Wentland struct link_init_data { 61fb3466a4SBhawanpreet Lakha const struct dc *dc; 624562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 634562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 644562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 654562236bSHarry Wentland TODO: remove it when DC is complete. */ 669fa0fb77SMeenakshikumar Somasundaram bool is_dpia_link; 674562236bSHarry Wentland }; 684562236bSHarry Wentland 69d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 70d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 714562236bSHarry Wentland 724562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 730971c40eSHarry Wentland const struct dc_stream_state *stream, 74d0778ebfSHarry Wentland struct dc_link *link, 754562236bSHarry Wentland const struct dc_crtc_timing *timing); 764562236bSHarry Wentland 77d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 784562236bSHarry Wentland 79ab8db3e1SAndrey Grodzovsky void core_link_enable_stream( 80ab8db3e1SAndrey Grodzovsky struct dc_state *state, 81ab8db3e1SAndrey Grodzovsky struct pipe_ctx *pipe_ctx); 824562236bSHarry Wentland 8357430404SSu Sung Chung void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 844562236bSHarry Wentland 8515e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 864562236bSHarry Wentland /********** DAL Core*********************/ 874562236bSHarry Wentland #include "transform.h" 88d94585a0SYue Hin Lau #include "dpp.h" 894562236bSHarry Wentland 904562236bSHarry Wentland struct resource_pool; 91608ac7bbSJerry Zuo struct dc_state; 924562236bSHarry Wentland struct resource_context; 93aa919167SBhawanpreet Lakha struct clk_bw_params; 944562236bSHarry Wentland 954562236bSHarry Wentland struct resource_funcs { 964562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 9766b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 98d4caa72eSAnthony Koo struct panel_cntl*(*panel_cntl_create)( 99d4caa72eSAnthony Koo const struct panel_cntl_init_data *panel_cntl_init_data); 1004562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 101e216431bSAurabindo Pillai struct dc_context *ctx, 1024562236bSHarry Wentland const struct encoder_init_data *init); 103e1f4328fSJimmy Kizito /* Create a minimal link encoder object with no dc_link object 104e1f4328fSJimmy Kizito * associated with it. */ 105e1f4328fSJimmy Kizito struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 106e1f4328fSJimmy Kizito 10745209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 108fb3466a4SBhawanpreet Lakha struct dc *dc, 109afcd526bSJoshua Aberback struct dc_state *context, 110afcd526bSJoshua Aberback bool fast_validate); 1118e02c26aSJoshua Aberback void (*calculate_wm_and_dlg)( 112b3ff538cSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 113b3ff538cSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 114b3ff538cSDmytro Laktyushkin int pipe_cnt, 115b3ff538cSDmytro Laktyushkin int vlevel); 116443dfba0SDmytro Laktyushkin void (*update_soc_for_wm_a)( 117443dfba0SDmytro Laktyushkin struct dc *dc, struct dc_state *context); 1181682bd1aSRodrigo Siqueira 1191682bd1aSRodrigo Siqueira /** 1201682bd1aSRodrigo Siqueira * @populate_dml_pipes - Populate pipe data struct 1211682bd1aSRodrigo Siqueira * 1221682bd1aSRodrigo Siqueira * Returns: 1231682bd1aSRodrigo Siqueira * Total of pipes available in the specific ASIC. 1241682bd1aSRodrigo Siqueira */ 125ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 126ed07237cSIlya Bakoulin struct dc *dc, 1272f488884SAlvin Lee struct dc_state *context, 128fa896813SIsabel Zhang display_e2e_pipe_params_st *pipes, 129fa896813SIsabel Zhang bool fast_validate); 130ed07237cSIlya Bakoulin 131f42ef862SJimmy Kizito /* 132f42ef862SJimmy Kizito * Algorithm for assigning available link encoders to links. 133f42ef862SJimmy Kizito * 134f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 135f42ef862SJimmy Kizito * struct resource_context. 136f42ef862SJimmy Kizito */ 137f42ef862SJimmy Kizito void (*link_encs_assign)( 138f42ef862SJimmy Kizito struct dc *dc, 139f42ef862SJimmy Kizito struct dc_state *state, 140f42ef862SJimmy Kizito struct dc_stream_state *streams[], 141f42ef862SJimmy Kizito uint8_t stream_count); 142f42ef862SJimmy Kizito /* 143f42ef862SJimmy Kizito * Unassign a link encoder from a stream. 144f42ef862SJimmy Kizito * 145f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 146f42ef862SJimmy Kizito * struct resource_context. 147f42ef862SJimmy Kizito */ 148f42ef862SJimmy Kizito void (*link_enc_unassign)( 149f42ef862SJimmy Kizito struct dc_state *state, 150f42ef862SJimmy Kizito struct dc_stream_state *stream); 151f42ef862SJimmy Kizito 1521dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1531dc90497SAndrey Grodzovsky struct dc *dc, 154608ac7bbSJerry Zuo struct dc_state *context); 1551dc90497SAndrey Grodzovsky 156652284d6SSamson Tam /* 157652284d6SSamson Tam * Acquires a free pipe for the head pipe. 158652284d6SSamson Tam * The head pipe is first pipe in the current context that matches the stream 159652284d6SSamson Tam * and does not have a top pipe or prev_odm_pipe. 160652284d6SSamson Tam */ 1614562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 162608ac7bbSJerry Zuo struct dc_state *context, 163a2b8659dSTony Cheng const struct resource_pool *pool, 1640971c40eSHarry Wentland struct dc_stream_state *stream); 1651dc90497SAndrey Grodzovsky 166652284d6SSamson Tam /* 167652284d6SSamson Tam * Acquires a free pipe for the head pipe with some additional checks for odm. 168652284d6SSamson Tam * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer 169652284d6SSamson Tam * where it is read from the context. So this allows us look for different 170652284d6SSamson Tam * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have 171652284d6SSamson Tam * a left and right pipe ). 172652284d6SSamson Tam * 173652284d6SSamson Tam * It also checks the old context to see if: 174652284d6SSamson Tam * 175652284d6SSamson Tam * 1. a pipe has already been allocated for the head pipe. If so, it will 176652284d6SSamson Tam * try to select that pipe as the idle pipe if it is available in the current 177652284d6SSamson Tam * context. 178652284d6SSamson Tam * 2. if the head_pipe is on the left, it will check if the right pipe has 179652284d6SSamson Tam * a pipe already allocated. If so, it will not use that pipe if it is 180652284d6SSamson Tam * selected as the idle pipe. 181652284d6SSamson Tam */ 182652284d6SSamson Tam struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)( 183652284d6SSamson Tam struct dc_state *context, 184652284d6SSamson Tam const struct resource_pool *pool, 185652284d6SSamson Tam struct dc_stream_state *stream, 186652284d6SSamson Tam struct pipe_ctx *head_pipe); 187652284d6SSamson Tam 1888e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1891dc90497SAndrey Grodzovsky 1901dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1911dc90497SAndrey Grodzovsky struct dc *dc, 192608ac7bbSJerry Zuo struct dc_state *new_ctx, 1931dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 194e56ae556SNikola Cornij 195e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 196e56ae556SNikola Cornij struct dc *dc, 197e56ae556SNikola Cornij struct dc_state *new_ctx, 198e56ae556SNikola Cornij struct dc_stream_state *stream); 1998d8c82b6SJoseph Gravenor enum dc_status (*patch_unknown_plane_state)( 20074eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 20174eac5f3SSu Sung Chung 20278cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 20378cc70b1SWesley Chalmers struct resource_context *res_ctx, 20478cc70b1SWesley Chalmers const struct resource_pool *pool, 20578cc70b1SWesley Chalmers struct dc_stream_state *stream); 206345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 207345429a6SHarry Wentland struct dc *dc, 208345429a6SHarry Wentland struct resource_context *res_ctx, 209345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 21078cc70b1SWesley Chalmers 211345429a6SHarry Wentland void (*set_mcif_arb_params)( 212345429a6SHarry Wentland struct dc *dc, 213345429a6SHarry Wentland struct dc_state *context, 214345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 215345429a6SHarry Wentland int pipe_cnt); 2161b2c7b2cSBhawanpreet Lakha void (*update_bw_bounding_box)( 2171b2c7b2cSBhawanpreet Lakha struct dc *dc, 2181b2c7b2cSBhawanpreet Lakha struct clk_bw_params *bw_params); 2195dba4991SBhawanpreet Lakha bool (*acquire_post_bldn_3dlut)( 2205dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 2215dba4991SBhawanpreet Lakha const struct resource_pool *pool, 2225dba4991SBhawanpreet Lakha int mpcc_id, 2235dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 2245dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 2255dba4991SBhawanpreet Lakha 2265dba4991SBhawanpreet Lakha bool (*release_post_bldn_3dlut)( 2275dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 2285dba4991SBhawanpreet Lakha const struct resource_pool *pool, 2295dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 2305dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 23159b8ca24SAlex Hung 232b4f71c8cSAurabindo Pillai enum dc_status (*add_dsc_to_stream_resource)( 233b4f71c8cSAurabindo Pillai struct dc *dc, struct dc_state *state, 234b4f71c8cSAurabindo Pillai struct dc_stream_state *stream); 235d3dfceb5SAurabindo Pillai 236d3dfceb5SAurabindo Pillai void (*add_phantom_pipes)( 237d3dfceb5SAurabindo Pillai struct dc *dc, 238d3dfceb5SAurabindo Pillai struct dc_state *context, 239d3dfceb5SAurabindo Pillai display_e2e_pipe_params_st *pipes, 240d3dfceb5SAurabindo Pillai unsigned int pipe_cnt, 241d3dfceb5SAurabindo Pillai unsigned int index); 24285f4bc0cSAlvin Lee 24385f4bc0cSAlvin Lee bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context); 2441178ac68SIan Chen void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 2454562236bSHarry Wentland }; 2464562236bSHarry Wentland 2474562236bSHarry Wentland struct audio_support{ 2484562236bSHarry Wentland bool dp_audio; 2494562236bSHarry Wentland bool hdmi_audio_on_dongle; 2504562236bSHarry Wentland bool hdmi_audio_native; 2514562236bSHarry Wentland }; 2524562236bSHarry Wentland 253f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 254f0e3db90SHarry Wentland 2554562236bSHarry Wentland struct resource_pool { 2564562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 2578feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 2584562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 2594562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 260d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 2614562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 2624562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 2634562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 264c9ef081dSYue Hin Lau struct hubbub *hubbub; 265cc408d72SDmytro Laktyushkin struct mpc *mpc; 2660f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 2671877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 268c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 269c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 270c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 2714562236bSHarry Wentland 272345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 273345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 274345429a6SHarry Wentland struct { 275345429a6SHarry Wentland unsigned int gsl_0:1; 276345429a6SHarry Wentland unsigned int gsl_1:1; 277345429a6SHarry Wentland unsigned int gsl_2:1; 278345429a6SHarry Wentland } gsl_groups; 279345429a6SHarry Wentland 28097bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 281345429a6SHarry Wentland 2824562236bSHarry Wentland unsigned int pipe_count; 2834562236bSHarry Wentland unsigned int underlay_pipe_index; 2844562236bSHarry Wentland unsigned int stream_enc_count; 285929c3aaaSEric Bernstein 286e1f4328fSJimmy Kizito /* An array for accessing the link encoder objects that have been created. 287e1f4328fSJimmy Kizito * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 288e1f4328fSJimmy Kizito */ 289e1f4328fSJimmy Kizito struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 290e1f4328fSJimmy Kizito /* Number of DIG link encoder objects created - i.e. number of valid 291e1f4328fSJimmy Kizito * entries in link_encoders array. 292e1f4328fSJimmy Kizito */ 293e1f4328fSJimmy Kizito unsigned int dig_link_enc_count; 294eabf2019SJimmy Kizito /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 295eabf2019SJimmy Kizito unsigned int usb4_dpia_count; 296e1f4328fSJimmy Kizito 29783228ebbSFangzhi Zuo unsigned int hpo_dp_stream_enc_count; 29883228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 2993bc8d921SFangzhi Zuo unsigned int hpo_dp_link_enc_count; 3003bc8d921SFangzhi Zuo struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 3015dba4991SBhawanpreet Lakha struct dc_3dlut *mpc_lut[MAX_PIPES]; 3025dba4991SBhawanpreet Lakha struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 30359b8ca24SAlex Hung 30433d7598dSJun Lei struct { 30533d7598dSJun Lei unsigned int xtalin_clock_inKhz; 30633d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 30733d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 30833d7598dSJun Lei } ref_clocks; 3093be1406aSYongqiang Sun unsigned int timing_generator_count; 310345429a6SHarry Wentland unsigned int mpcc_count; 3114562236bSHarry Wentland 312345429a6SHarry Wentland unsigned int writeback_pipe_count; 3134562236bSHarry Wentland /* 3144562236bSHarry Wentland * reserved clock source for DP 3154562236bSHarry Wentland */ 3164562236bSHarry Wentland struct clock_source *dp_clock_source; 3174562236bSHarry Wentland 3184562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 3194562236bSHarry Wentland unsigned int clk_src_count; 3204562236bSHarry Wentland 3217352193aSTai Man struct audio *audios[MAX_AUDIOS]; 3224562236bSHarry Wentland unsigned int audio_count; 3234562236bSHarry Wentland struct audio_support audio_support; 3244562236bSHarry Wentland 325ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 3264562236bSHarry Wentland struct irq_service *irqs; 3274562236bSHarry Wentland 3285e7773a2SAnthony Koo struct abm *abm; 3295e7773a2SAnthony Koo struct dmcu *dmcu; 3304c1a1335SWyatt Wood struct dmub_psr *psr; 3315e7773a2SAnthony Koo 332d99f1387SBhawanpreet Lakha struct abm *multiple_abms[MAX_PIPES]; 333d99f1387SBhawanpreet Lakha 3344562236bSHarry Wentland const struct resource_funcs *funcs; 3354562236bSHarry Wentland const struct resource_caps *res_cap; 336d9a07577SJun Lei 337d9a07577SJun Lei struct ddc_service *oem_device; 3384562236bSHarry Wentland }; 3394562236bSHarry Wentland 340f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 34169338c1fSDmytro Laktyushkin int dppclk_khz; 342799c5b9cSWesley Chalmers 343f553e681SDmytro Laktyushkin }; 344f553e681SDmytro Laktyushkin 34579b06f0cSHarry Wentland struct stream_resource { 346a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 34797bda032SHarry Wentland struct display_stream_compressor *dsc; 3486b670fa9SHarry Wentland struct timing_generator *tg; 3498e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 35083228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 351afaacef4SHarry Wentland struct audio *audio; 35210688217SHarry Wentland 35310688217SHarry Wentland struct pixel_clk_params pix_clk_params; 35496c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 3559aef1a31SSivapiriyanKumarasamy 3569aef1a31SSivapiriyanKumarasamy struct abm *abm; 357345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 358345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 359345429a6SHarry Wentland */ 360345429a6SHarry Wentland uint8_t gsl_group; 36179b06f0cSHarry Wentland }; 36279b06f0cSHarry Wentland 36379b06f0cSHarry Wentland struct plane_resource { 3646702a9acSHarry Wentland struct scaler_data scl_data; 3658feabd03SYue Hin Lau struct hubp *hubp; 36686a66c4eSHarry Wentland struct mem_input *mi; 36786a66c4eSHarry Wentland struct input_pixel_processor *ipp; 36886a66c4eSHarry Wentland struct transform *xfm; 369d94585a0SYue Hin Lau struct dpp *dpp; 370e07f541fSYongqiang Sun uint8_t mpcc_inst; 371f553e681SDmytro Laktyushkin 372f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 37379b06f0cSHarry Wentland }; 37479b06f0cSHarry Wentland 3754c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 3764c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 3774c3adc0bSWenjing Liu 378ef30f441SWenjing Liu /* all mappable hardware resources used to enable a link */ 379ef30f441SWenjing Liu struct link_resource { 380f3fac948SWenjing Liu struct hpo_dp_link_encoder *hpo_dp_link_enc; 381ef30f441SWenjing Liu }; 382ef30f441SWenjing Liu 383017860c9SWenjing Liu struct link_config { 384017860c9SWenjing Liu struct dc_link_settings dp_link_settings; 385017860c9SWenjing Liu }; 38624c18794SDmytro Laktyushkin union pipe_update_flags { 38724c18794SDmytro Laktyushkin struct { 38824c18794SDmytro Laktyushkin uint32_t enable : 1; 38924c18794SDmytro Laktyushkin uint32_t disable : 1; 39024c18794SDmytro Laktyushkin uint32_t odm : 1; 39124c18794SDmytro Laktyushkin uint32_t global_sync : 1; 39224c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 39324c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 39424c18794SDmytro Laktyushkin uint32_t mpcc : 1; 39524c18794SDmytro Laktyushkin uint32_t dppclk : 1; 39624c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 39724c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 39824c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 39924c18794SDmytro Laktyushkin uint32_t scaler : 1; 40024c18794SDmytro Laktyushkin uint32_t viewport : 1; 401498563cfSJinZe.Xu uint32_t plane_changed : 1; 402ba5a5371SNicholas Kazlauskas uint32_t det_size : 1; 40324c18794SDmytro Laktyushkin } bits; 40424c18794SDmytro Laktyushkin uint32_t raw; 40524c18794SDmytro Laktyushkin }; 40624c18794SDmytro Laktyushkin 4074562236bSHarry Wentland struct pipe_ctx { 4083be5262eSHarry Wentland struct dc_plane_state *plane_state; 4090971c40eSHarry Wentland struct dc_stream_state *stream; 4104562236bSHarry Wentland 41179b06f0cSHarry Wentland struct plane_resource plane_res; 412fdf17f10SRodrigo Siqueira 413fdf17f10SRodrigo Siqueira /** 414fdf17f10SRodrigo Siqueira * @stream_res: Reference to DCN resource components such OPP and DSC. 415fdf17f10SRodrigo Siqueira */ 41679b06f0cSHarry Wentland struct stream_resource stream_res; 417ef30f441SWenjing Liu struct link_resource link_res; 41879b06f0cSHarry Wentland 4194562236bSHarry Wentland struct clock_source *clock_source; 4204562236bSHarry Wentland 4214562236bSHarry Wentland struct pll_settings pll_settings; 4224562236bSHarry Wentland 423017860c9SWenjing Liu /* link config records software decision for what link config should be 424017860c9SWenjing Liu * enabled given current link capability and stream during hw resource 425017860c9SWenjing Liu * mapping. This is to decouple the dependency on link capability during 426017860c9SWenjing Liu * dc commit or update. 427017860c9SWenjing Liu */ 428017860c9SWenjing Liu struct link_config link_config; 429017860c9SWenjing Liu 4304562236bSHarry Wentland uint8_t pipe_idx; 431a896f870SMeenakshikumar Somasundaram uint8_t pipe_idx_syncd; 4324562236bSHarry Wentland 4334562236bSHarry Wentland struct pipe_ctx *top_pipe; 4344562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 435b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 436b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 437f0558542SDmytro Laktyushkin 438ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 439ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 440ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 441ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 4421f2fcc81SHarry Wentland struct _vcs_dpi_display_rq_params_st dml_rq_param; 4431f2fcc81SHarry Wentland struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 4441f2fcc81SHarry Wentland struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 445ba5a5371SNicholas Kazlauskas int det_buffer_size_kb; 446ba5a5371SNicholas Kazlauskas bool unbounded_req; 44759b8ca24SAlex Hung 44824c18794SDmytro Laktyushkin union pipe_update_flags update_flags; 449345429a6SHarry Wentland struct dwbc *dwbc; 450345429a6SHarry Wentland struct mcif_wb *mcif_wb; 4514562236bSHarry Wentland }; 4524562236bSHarry Wentland 4530d4b4253SJimmy Kizito /* Data used for dynamic link encoder assignment. 4540d4b4253SJimmy Kizito * Tracks current and future assignments; available link encoders; 4550d4b4253SJimmy Kizito * and mode of operation (whether to use current or future assignments). 4560d4b4253SJimmy Kizito */ 4570d4b4253SJimmy Kizito struct link_enc_cfg_context { 4580d4b4253SJimmy Kizito enum link_enc_cfg_mode mode; 4590d4b4253SJimmy Kizito struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 4600d4b4253SJimmy Kizito enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 4610d4b4253SJimmy Kizito struct link_enc_assignment transient_assignments[MAX_PIPES]; 4620d4b4253SJimmy Kizito }; 4630d4b4253SJimmy Kizito 4644562236bSHarry Wentland struct resource_context { 4654562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 4664562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 4674562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 4684562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 4694562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 470345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 4710d4b4253SJimmy Kizito struct link_enc_cfg_context link_enc_cfg_ctx; 47283228ebbSFangzhi Zuo bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 4736dd8931bSWenjing Liu unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 4746dd8931bSWenjing Liu int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 4755dba4991SBhawanpreet Lakha bool is_mpc_3dlut_acquired[MAX_PIPES]; 4764562236bSHarry Wentland }; 4774562236bSHarry Wentland 4789037d802SDmytro Laktyushkin struct dce_bw_output { 4799037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 4809037d802SDmytro Laktyushkin bool cpup_state_change_enable; 4819037d802SDmytro Laktyushkin bool stutter_mode_enable; 4829037d802SDmytro Laktyushkin bool nbp_state_change_enable; 4839037d802SDmytro Laktyushkin bool all_displays_in_sync; 4849037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 4859037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 486b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 4879037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 4889037d802SDmytro Laktyushkin int sclk_khz; 4899037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 4909037d802SDmytro Laktyushkin int yclk_khz; 4919037d802SDmytro Laktyushkin int dispclk_khz; 4929037d802SDmytro Laktyushkin int blackout_recovery_time_us; 4939037d802SDmytro Laktyushkin }; 4949037d802SDmytro Laktyushkin 495345429a6SHarry Wentland struct dcn_bw_writeback { 496345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 497345429a6SHarry Wentland }; 498345429a6SHarry Wentland 4999037d802SDmytro Laktyushkin struct dcn_bw_output { 500d578839cSDmytro Laktyushkin struct dc_clocks clk; 5019037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 502345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 503ba5a5371SNicholas Kazlauskas int compbuf_size_kb; 50420dad381SJun Lei unsigned int legacy_svp_drr_stream_index; 50520dad381SJun Lei bool legacy_svp_drr_stream_index_valid; 5069037d802SDmytro Laktyushkin }; 5079037d802SDmytro Laktyushkin 508813d20dcSAidan Wood union bw_output { 5099037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 5109037d802SDmytro Laktyushkin struct dce_bw_output dce; 5119037d802SDmytro Laktyushkin }; 5129037d802SDmytro Laktyushkin 513813d20dcSAidan Wood struct bw_context { 514813d20dcSAidan Wood union bw_output bw; 515813d20dcSAidan Wood struct display_mode_lib dml; 516813d20dcSAidan Wood }; 517*fa0fc4fbSRodrigo Siqueira 5182119aa17SDavid Francis /** 519*fa0fc4fbSRodrigo Siqueira * struct dc_state - The full description of a state requested by users 5202119aa17SDavid Francis */ 521608ac7bbSJerry Zuo struct dc_state { 522*fa0fc4fbSRodrigo Siqueira /** 523*fa0fc4fbSRodrigo Siqueira * @streams: Stream state properties 524*fa0fc4fbSRodrigo Siqueira */ 5250971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 526*fa0fc4fbSRodrigo Siqueira 527*fa0fc4fbSRodrigo Siqueira /** 528*fa0fc4fbSRodrigo Siqueira * @stream_status: Planes status on a given stream 529*fa0fc4fbSRodrigo Siqueira */ 530ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 531*fa0fc4fbSRodrigo Siqueira 532*fa0fc4fbSRodrigo Siqueira /** 533*fa0fc4fbSRodrigo Siqueira * @stream_count: Total of streams in use 534*fa0fc4fbSRodrigo Siqueira */ 535ab2541b6SAric Cyr uint8_t stream_count; 5360825d965SEric Yang uint8_t stream_mask; 5374562236bSHarry Wentland 538*fa0fc4fbSRodrigo Siqueira /** 539*fa0fc4fbSRodrigo Siqueira * @res_ctx: Persistent state of resources 540*fa0fc4fbSRodrigo Siqueira */ 5414562236bSHarry Wentland struct resource_context res_ctx; 5424562236bSHarry Wentland 543*fa0fc4fbSRodrigo Siqueira /** 544*fa0fc4fbSRodrigo Siqueira * @bw_ctx: The output from bandwidth and watermark calculations and the DML 545*fa0fc4fbSRodrigo Siqueira */ 546813d20dcSAidan Wood struct bw_context bw_ctx; 5479037d802SDmytro Laktyushkin 548*fa0fc4fbSRodrigo Siqueira /** 549*fa0fc4fbSRodrigo Siqueira * @pp_display_cfg: PowerPlay clocks and settings 550*fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 551*fa0fc4fbSRodrigo Siqueira */ 5524562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 553*fa0fc4fbSRodrigo Siqueira 554*fa0fc4fbSRodrigo Siqueira /** 555*fa0fc4fbSRodrigo Siqueira * @dcn_bw_vars: non-stack memory to support bandwidth calculations 556*fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 557*fa0fc4fbSRodrigo Siqueira */ 558ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 5598a76708eSAndrey Grodzovsky 5600de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 561ab8db3e1SAndrey Grodzovsky 5628ee5702aSDave Airlie struct kref refcount; 5636b85151fSMartin Leung 5646b85151fSMartin Leung struct { 5656b85151fSMartin Leung unsigned int stutter_period_us; 5666b85151fSMartin Leung } perf_params; 5674562236bSHarry Wentland }; 5684562236bSHarry Wentland 569e4b0eac3SJasdeep Dhillon struct dc_bounding_box_max_clk { 570e4b0eac3SJasdeep Dhillon int max_dcfclk_mhz; 571e4b0eac3SJasdeep Dhillon int max_dispclk_mhz; 572e4b0eac3SJasdeep Dhillon int max_dppclk_mhz; 573e4b0eac3SJasdeep Dhillon int max_phyclk_mhz; 574e4b0eac3SJasdeep Dhillon }; 575e4b0eac3SJasdeep Dhillon 5764562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 577