14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36391e20d8SDuke Du #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 37ff5ef992SAlex Deucher #include "mpc.h" 38391e20d8SDuke Du #endif 394562236bSHarry Wentland 404562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 414562236bSHarry Wentland 423be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 434562236bSHarry Wentland uint32_t controller_id); 444562236bSHarry Wentland 454562236bSHarry Wentland #include "grph_object_id.h" 464562236bSHarry Wentland #include "link_encoder.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "clock_source.h" 494562236bSHarry Wentland #include "audio.h" 50a185048cSTony Cheng #include "dm_pp_smu.h" 514562236bSHarry Wentland 524562236bSHarry Wentland 534562236bSHarry Wentland /************ link *****************/ 544562236bSHarry Wentland struct link_init_data { 55fb3466a4SBhawanpreet Lakha const struct dc *dc; 564562236bSHarry Wentland struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 574562236bSHarry Wentland uint32_t connector_index; /* this will be mapped to the HPD pins */ 584562236bSHarry Wentland uint32_t link_index; /* this is mapped to DAL display_index 594562236bSHarry Wentland TODO: remove it when DC is complete. */ 604562236bSHarry Wentland }; 614562236bSHarry Wentland 624176664bSCharlene Liu enum { 634176664bSCharlene Liu FREE_ACQUIRED_RESOURCE = 0, 644176664bSCharlene Liu KEEP_ACQUIRED_RESOURCE = 1, 654176664bSCharlene Liu }; 664176664bSCharlene Liu 67d0778ebfSHarry Wentland struct dc_link *link_create(const struct link_init_data *init_params); 68d0778ebfSHarry Wentland void link_destroy(struct dc_link **link); 694562236bSHarry Wentland 704562236bSHarry Wentland enum dc_status dc_link_validate_mode_timing( 710971c40eSHarry Wentland const struct dc_stream_state *stream, 72d0778ebfSHarry Wentland struct dc_link *link, 734562236bSHarry Wentland const struct dc_crtc_timing *timing); 744562236bSHarry Wentland 75d0778ebfSHarry Wentland void core_link_resume(struct dc_link *link); 764562236bSHarry Wentland 77ab8db3e1SAndrey Grodzovsky void core_link_enable_stream( 78ab8db3e1SAndrey Grodzovsky struct dc_state *state, 79ab8db3e1SAndrey Grodzovsky struct pipe_ctx *pipe_ctx); 804562236bSHarry Wentland 814176664bSCharlene Liu void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option); 824562236bSHarry Wentland 8315e17335SCharlene Liu void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 844562236bSHarry Wentland /********** DAL Core*********************/ 85e11b86adSDmytro Laktyushkin #include "display_clock.h" 864562236bSHarry Wentland #include "transform.h" 87d94585a0SYue Hin Lau #include "dpp.h" 884562236bSHarry Wentland 894562236bSHarry Wentland struct resource_pool; 90608ac7bbSJerry Zuo struct dc_state; 914562236bSHarry Wentland struct resource_context; 924562236bSHarry Wentland 934562236bSHarry Wentland struct resource_funcs { 944562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 954562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 964562236bSHarry Wentland const struct encoder_init_data *init); 974562236bSHarry Wentland 984562236bSHarry Wentland enum dc_status (*validate_guaranteed)( 99fb3466a4SBhawanpreet Lakha struct dc *dc, 1000971c40eSHarry Wentland struct dc_stream_state *stream, 101608ac7bbSJerry Zuo struct dc_state *context); 1024562236bSHarry Wentland 10345209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 104fb3466a4SBhawanpreet Lakha struct dc *dc, 105608ac7bbSJerry Zuo struct dc_state *context); 1064562236bSHarry Wentland 1071dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1081dc90497SAndrey Grodzovsky struct dc *dc, 109608ac7bbSJerry Zuo struct dc_state *context); 1101dc90497SAndrey Grodzovsky 1114562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 112608ac7bbSJerry Zuo struct dc_state *context, 113a2b8659dSTony Cheng const struct resource_pool *pool, 1140971c40eSHarry Wentland struct dc_stream_state *stream); 1151dc90497SAndrey Grodzovsky 1168e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1171dc90497SAndrey Grodzovsky 1181dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1191dc90497SAndrey Grodzovsky struct dc *dc, 120608ac7bbSJerry Zuo struct dc_state *new_ctx, 1211dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 122e56ae556SNikola Cornij 123e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 124e56ae556SNikola Cornij struct dc *dc, 125e56ae556SNikola Cornij struct dc_state *new_ctx, 126e56ae556SNikola Cornij struct dc_stream_state *stream); 1274562236bSHarry Wentland }; 1284562236bSHarry Wentland 1294562236bSHarry Wentland struct audio_support{ 1304562236bSHarry Wentland bool dp_audio; 1314562236bSHarry Wentland bool hdmi_audio_on_dongle; 1324562236bSHarry Wentland bool hdmi_audio_native; 1334562236bSHarry Wentland }; 1344562236bSHarry Wentland 135f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 136f0e3db90SHarry Wentland 1374562236bSHarry Wentland struct resource_pool { 1384562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 1398feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 1404562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 1414562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 142d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 1434562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 1444562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 1454562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 1465f06b3cfSTony Cheng 147c9ef081dSYue Hin Lau struct hubbub *hubbub; 148cc408d72SDmytro Laktyushkin struct mpc *mpc; 149a185048cSTony Cheng struct pp_smu_funcs_rv *pp_smu; 1505f06b3cfSTony Cheng struct pp_smu_display_requirement_rv pp_smu_req; 1514562236bSHarry Wentland 1524562236bSHarry Wentland unsigned int pipe_count; 1534562236bSHarry Wentland unsigned int underlay_pipe_index; 1544562236bSHarry Wentland unsigned int stream_enc_count; 1555ac3d3c9SCharlene Liu unsigned int ref_clock_inKhz; 1563be1406aSYongqiang Sun unsigned int timing_generator_count; 1574562236bSHarry Wentland 1584562236bSHarry Wentland /* 1594562236bSHarry Wentland * reserved clock source for DP 1604562236bSHarry Wentland */ 1614562236bSHarry Wentland struct clock_source *dp_clock_source; 1624562236bSHarry Wentland 1634562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 1644562236bSHarry Wentland unsigned int clk_src_count; 1654562236bSHarry Wentland 1664562236bSHarry Wentland struct audio *audios[MAX_PIPES]; 1674562236bSHarry Wentland unsigned int audio_count; 1684562236bSHarry Wentland struct audio_support audio_support; 1694562236bSHarry Wentland 1704562236bSHarry Wentland struct display_clock *display_clock; 1714562236bSHarry Wentland struct irq_service *irqs; 1724562236bSHarry Wentland 1735e7773a2SAnthony Koo struct abm *abm; 1745e7773a2SAnthony Koo struct dmcu *dmcu; 1755e7773a2SAnthony Koo 1764562236bSHarry Wentland const struct resource_funcs *funcs; 1774562236bSHarry Wentland const struct resource_caps *res_cap; 1784562236bSHarry Wentland }; 1794562236bSHarry Wentland 180f553e681SDmytro Laktyushkin struct dcn_fe_clocks { 181f553e681SDmytro Laktyushkin int dppclk_khz; 182f553e681SDmytro Laktyushkin }; 183f553e681SDmytro Laktyushkin 184f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 185f553e681SDmytro Laktyushkin struct dcn_fe_clocks calc; 186f553e681SDmytro Laktyushkin struct dcn_fe_clocks cur; 187f553e681SDmytro Laktyushkin }; 188f553e681SDmytro Laktyushkin 18979b06f0cSHarry Wentland struct stream_resource { 190a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 1916b670fa9SHarry Wentland struct timing_generator *tg; 1928e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 193afaacef4SHarry Wentland struct audio *audio; 19410688217SHarry Wentland 19510688217SHarry Wentland struct pixel_clk_params pix_clk_params; 19696c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 19779b06f0cSHarry Wentland }; 19879b06f0cSHarry Wentland 19979b06f0cSHarry Wentland struct plane_resource { 2006702a9acSHarry Wentland struct scaler_data scl_data; 2018feabd03SYue Hin Lau struct hubp *hubp; 20286a66c4eSHarry Wentland struct mem_input *mi; 20386a66c4eSHarry Wentland struct input_pixel_processor *ipp; 20486a66c4eSHarry Wentland struct transform *xfm; 205d94585a0SYue Hin Lau struct dpp *dpp; 206e07f541fSYongqiang Sun uint8_t mpcc_inst; 207f553e681SDmytro Laktyushkin 208f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 20979b06f0cSHarry Wentland }; 21079b06f0cSHarry Wentland 2114562236bSHarry Wentland struct pipe_ctx { 2123be5262eSHarry Wentland struct dc_plane_state *plane_state; 2130971c40eSHarry Wentland struct dc_stream_state *stream; 2144562236bSHarry Wentland 21579b06f0cSHarry Wentland struct plane_resource plane_res; 21679b06f0cSHarry Wentland struct stream_resource stream_res; 21779b06f0cSHarry Wentland 2184562236bSHarry Wentland struct clock_source *clock_source; 2194562236bSHarry Wentland 2204562236bSHarry Wentland struct pll_settings pll_settings; 2214562236bSHarry Wentland 2224562236bSHarry Wentland uint8_t pipe_idx; 2234562236bSHarry Wentland 2244562236bSHarry Wentland struct pipe_ctx *top_pipe; 2254562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 226f0558542SDmytro Laktyushkin 227ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 228ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 229ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 230ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 231ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 232ff5ef992SAlex Deucher #endif 2334562236bSHarry Wentland }; 2344562236bSHarry Wentland 2354562236bSHarry Wentland struct resource_context { 2364562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 2374562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 2384562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 2394562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 2404562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 2414562236bSHarry Wentland }; 2424562236bSHarry Wentland 2439037d802SDmytro Laktyushkin struct dce_bw_output { 2449037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 2459037d802SDmytro Laktyushkin bool cpup_state_change_enable; 2469037d802SDmytro Laktyushkin bool stutter_mode_enable; 2479037d802SDmytro Laktyushkin bool nbp_state_change_enable; 2489037d802SDmytro Laktyushkin bool all_displays_in_sync; 2499037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 2509037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 2519037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 2529037d802SDmytro Laktyushkin int sclk_khz; 2539037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 2549037d802SDmytro Laktyushkin int yclk_khz; 2559037d802SDmytro Laktyushkin int dispclk_khz; 2569037d802SDmytro Laktyushkin int blackout_recovery_time_us; 2579037d802SDmytro Laktyushkin }; 2589037d802SDmytro Laktyushkin 2599037d802SDmytro Laktyushkin struct dcn_bw_clocks { 2609037d802SDmytro Laktyushkin int dispclk_khz; 261f553e681SDmytro Laktyushkin int max_dppclk_khz; 2629037d802SDmytro Laktyushkin int dcfclk_khz; 263f553e681SDmytro Laktyushkin int socclk_khz; 2649037d802SDmytro Laktyushkin int dcfclk_deep_sleep_khz; 2659037d802SDmytro Laktyushkin int fclk_khz; 2669037d802SDmytro Laktyushkin int dram_ccm_us; 2679037d802SDmytro Laktyushkin int min_active_dram_ccm_us; 2689037d802SDmytro Laktyushkin }; 2699037d802SDmytro Laktyushkin 2709037d802SDmytro Laktyushkin struct dcn_bw_output { 2719037d802SDmytro Laktyushkin struct dcn_bw_clocks cur_clk; 2729037d802SDmytro Laktyushkin struct dcn_bw_clocks calc_clk; 2739037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 2749037d802SDmytro Laktyushkin }; 2759037d802SDmytro Laktyushkin 2769037d802SDmytro Laktyushkin union bw_context { 2779037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 2789037d802SDmytro Laktyushkin struct dce_bw_output dce; 2799037d802SDmytro Laktyushkin }; 2809037d802SDmytro Laktyushkin 281608ac7bbSJerry Zuo struct dc_state { 2820971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 283ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 284ab2541b6SAric Cyr uint8_t stream_count; 2854562236bSHarry Wentland 2864562236bSHarry Wentland struct resource_context res_ctx; 2874562236bSHarry Wentland 2884562236bSHarry Wentland /* The output from BW and WM calculations. */ 2899037d802SDmytro Laktyushkin union bw_context bw; 2909037d802SDmytro Laktyushkin 2915ea81b91SDmytro Laktyushkin /* Note: these are big structures, do *not* put on stack! */ 2924562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 293ff5ef992SAlex Deucher #ifdef CONFIG_DRM_AMD_DC_DCN1_0 294ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 295ff5ef992SAlex Deucher #endif 2968a76708eSAndrey Grodzovsky 297ab8db3e1SAndrey Grodzovsky struct display_clock *dis_clk; 298ab8db3e1SAndrey Grodzovsky 2998ee5702aSDave Airlie struct kref refcount; 3004562236bSHarry Wentland }; 3014562236bSHarry Wentland 3024562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 303