14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36ff5ef992SAlex Deucher #include "mpc.h" 37345429a6SHarry Wentland #include "dwb.h" 38345429a6SHarry Wentland #include "mcif_wb.h" 39d4caa72eSAnthony Koo #include "panel_cntl.h" 400baae624SAlvin Lee #include "dmub/inc/dmub_cmd.h" 414562236bSHarry Wentland 424562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 4320dad381SJun Lei #define MAX_SVP_PHANTOM_STREAMS 2 4420dad381SJun Lei #define MAX_SVP_PHANTOM_PLANES 2 454562236bSHarry Wentland 463be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 474562236bSHarry Wentland uint32_t controller_id); 484562236bSHarry Wentland 494562236bSHarry Wentland #include "grph_object_id.h" 504562236bSHarry Wentland #include "link_encoder.h" 514562236bSHarry Wentland #include "stream_encoder.h" 524562236bSHarry Wentland #include "clock_source.h" 534562236bSHarry Wentland #include "audio.h" 54a185048cSTony Cheng #include "dm_pp_smu.h" 55d462fcf5SBhawanpreet Lakha #include "dm_cp_psp.h" 56fd249266SWenjing Liu #include "link_hwss.h" 574562236bSHarry Wentland 584562236bSHarry Wentland /********** DAL Core*********************/ 594562236bSHarry Wentland #include "transform.h" 60d94585a0SYue Hin Lau #include "dpp.h" 614562236bSHarry Wentland 624562236bSHarry Wentland struct resource_pool; 63608ac7bbSJerry Zuo struct dc_state; 644562236bSHarry Wentland struct resource_context; 65aa919167SBhawanpreet Lakha struct clk_bw_params; 664562236bSHarry Wentland 674562236bSHarry Wentland struct resource_funcs { 684562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 6966b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 70d4caa72eSAnthony Koo struct panel_cntl*(*panel_cntl_create)( 71d4caa72eSAnthony Koo const struct panel_cntl_init_data *panel_cntl_init_data); 724562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 73e216431bSAurabindo Pillai struct dc_context *ctx, 744562236bSHarry Wentland const struct encoder_init_data *init); 75e1f4328fSJimmy Kizito /* Create a minimal link encoder object with no dc_link object 76e1f4328fSJimmy Kizito * associated with it. */ 77e1f4328fSJimmy Kizito struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 78e1f4328fSJimmy Kizito 7945209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 80fb3466a4SBhawanpreet Lakha struct dc *dc, 81afcd526bSJoshua Aberback struct dc_state *context, 82afcd526bSJoshua Aberback bool fast_validate); 838e02c26aSJoshua Aberback void (*calculate_wm_and_dlg)( 84b3ff538cSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 85b3ff538cSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 86b3ff538cSDmytro Laktyushkin int pipe_cnt, 87b3ff538cSDmytro Laktyushkin int vlevel); 88443dfba0SDmytro Laktyushkin void (*update_soc_for_wm_a)( 89443dfba0SDmytro Laktyushkin struct dc *dc, struct dc_state *context); 901682bd1aSRodrigo Siqueira 911682bd1aSRodrigo Siqueira /** 921682bd1aSRodrigo Siqueira * @populate_dml_pipes - Populate pipe data struct 931682bd1aSRodrigo Siqueira * 941682bd1aSRodrigo Siqueira * Returns: 951682bd1aSRodrigo Siqueira * Total of pipes available in the specific ASIC. 961682bd1aSRodrigo Siqueira */ 97ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 98ed07237cSIlya Bakoulin struct dc *dc, 992f488884SAlvin Lee struct dc_state *context, 100fa896813SIsabel Zhang display_e2e_pipe_params_st *pipes, 101fa896813SIsabel Zhang bool fast_validate); 102ed07237cSIlya Bakoulin 103f42ef862SJimmy Kizito /* 104f42ef862SJimmy Kizito * Algorithm for assigning available link encoders to links. 105f42ef862SJimmy Kizito * 106f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 107f42ef862SJimmy Kizito * struct resource_context. 108f42ef862SJimmy Kizito */ 109f42ef862SJimmy Kizito void (*link_encs_assign)( 110f42ef862SJimmy Kizito struct dc *dc, 111f42ef862SJimmy Kizito struct dc_state *state, 112f42ef862SJimmy Kizito struct dc_stream_state *streams[], 113f42ef862SJimmy Kizito uint8_t stream_count); 114f42ef862SJimmy Kizito /* 115f42ef862SJimmy Kizito * Unassign a link encoder from a stream. 116f42ef862SJimmy Kizito * 117f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 118f42ef862SJimmy Kizito * struct resource_context. 119f42ef862SJimmy Kizito */ 120f42ef862SJimmy Kizito void (*link_enc_unassign)( 121f42ef862SJimmy Kizito struct dc_state *state, 122f42ef862SJimmy Kizito struct dc_stream_state *stream); 123f42ef862SJimmy Kizito 1241dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1251dc90497SAndrey Grodzovsky struct dc *dc, 126608ac7bbSJerry Zuo struct dc_state *context); 1271dc90497SAndrey Grodzovsky 128652284d6SSamson Tam /* 129652284d6SSamson Tam * Acquires a free pipe for the head pipe. 130652284d6SSamson Tam * The head pipe is first pipe in the current context that matches the stream 131652284d6SSamson Tam * and does not have a top pipe or prev_odm_pipe. 132652284d6SSamson Tam */ 1334562236bSHarry Wentland struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 134608ac7bbSJerry Zuo struct dc_state *context, 135a2b8659dSTony Cheng const struct resource_pool *pool, 1360971c40eSHarry Wentland struct dc_stream_state *stream); 1371dc90497SAndrey Grodzovsky 138652284d6SSamson Tam /* 139652284d6SSamson Tam * Acquires a free pipe for the head pipe with some additional checks for odm. 140652284d6SSamson Tam * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer 141652284d6SSamson Tam * where it is read from the context. So this allows us look for different 142652284d6SSamson Tam * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have 143652284d6SSamson Tam * a left and right pipe ). 144652284d6SSamson Tam * 145652284d6SSamson Tam * It also checks the old context to see if: 146652284d6SSamson Tam * 147652284d6SSamson Tam * 1. a pipe has already been allocated for the head pipe. If so, it will 148652284d6SSamson Tam * try to select that pipe as the idle pipe if it is available in the current 149652284d6SSamson Tam * context. 150652284d6SSamson Tam * 2. if the head_pipe is on the left, it will check if the right pipe has 151652284d6SSamson Tam * a pipe already allocated. If so, it will not use that pipe if it is 152652284d6SSamson Tam * selected as the idle pipe. 153652284d6SSamson Tam */ 154652284d6SSamson Tam struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)( 155652284d6SSamson Tam struct dc_state *context, 156652284d6SSamson Tam const struct resource_pool *pool, 157652284d6SSamson Tam struct dc_stream_state *stream, 158652284d6SSamson Tam struct pipe_ctx *head_pipe); 159652284d6SSamson Tam 1608e7095b9SDmytro Laktyushkin enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 1611dc90497SAndrey Grodzovsky 1621dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1631dc90497SAndrey Grodzovsky struct dc *dc, 164608ac7bbSJerry Zuo struct dc_state *new_ctx, 1651dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 166e56ae556SNikola Cornij 167e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 168e56ae556SNikola Cornij struct dc *dc, 169e56ae556SNikola Cornij struct dc_state *new_ctx, 170e56ae556SNikola Cornij struct dc_stream_state *stream); 1718d8c82b6SJoseph Gravenor enum dc_status (*patch_unknown_plane_state)( 17274eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 17374eac5f3SSu Sung Chung 17478cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 17578cc70b1SWesley Chalmers struct resource_context *res_ctx, 17678cc70b1SWesley Chalmers const struct resource_pool *pool, 17778cc70b1SWesley Chalmers struct dc_stream_state *stream); 178345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 179345429a6SHarry Wentland struct dc *dc, 180345429a6SHarry Wentland struct resource_context *res_ctx, 181345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 18278cc70b1SWesley Chalmers 183345429a6SHarry Wentland void (*set_mcif_arb_params)( 184345429a6SHarry Wentland struct dc *dc, 185345429a6SHarry Wentland struct dc_state *context, 186345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 187345429a6SHarry Wentland int pipe_cnt); 1881b2c7b2cSBhawanpreet Lakha void (*update_bw_bounding_box)( 1891b2c7b2cSBhawanpreet Lakha struct dc *dc, 1901b2c7b2cSBhawanpreet Lakha struct clk_bw_params *bw_params); 1915dba4991SBhawanpreet Lakha bool (*acquire_post_bldn_3dlut)( 1925dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1935dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1945dba4991SBhawanpreet Lakha int mpcc_id, 1955dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1965dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1975dba4991SBhawanpreet Lakha 1985dba4991SBhawanpreet Lakha bool (*release_post_bldn_3dlut)( 1995dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 2005dba4991SBhawanpreet Lakha const struct resource_pool *pool, 2015dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 2025dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 20359b8ca24SAlex Hung 204b4f71c8cSAurabindo Pillai enum dc_status (*add_dsc_to_stream_resource)( 205b4f71c8cSAurabindo Pillai struct dc *dc, struct dc_state *state, 206b4f71c8cSAurabindo Pillai struct dc_stream_state *stream); 207d3dfceb5SAurabindo Pillai 208d3dfceb5SAurabindo Pillai void (*add_phantom_pipes)( 209d3dfceb5SAurabindo Pillai struct dc *dc, 210d3dfceb5SAurabindo Pillai struct dc_state *context, 211d3dfceb5SAurabindo Pillai display_e2e_pipe_params_st *pipes, 212d3dfceb5SAurabindo Pillai unsigned int pipe_cnt, 213d3dfceb5SAurabindo Pillai unsigned int index); 21485f4bc0cSAlvin Lee 215fd9978aaSAlvin Lee bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update); 2169b216b7eSAlvin Lee void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 2171178ac68SIan Chen void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 218aaae5211SAlvin Lee void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 219aaae5211SAlvin Lee void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 2204562236bSHarry Wentland }; 2214562236bSHarry Wentland 2224562236bSHarry Wentland struct audio_support{ 2234562236bSHarry Wentland bool dp_audio; 2244562236bSHarry Wentland bool hdmi_audio_on_dongle; 2254562236bSHarry Wentland bool hdmi_audio_native; 2264562236bSHarry Wentland }; 2274562236bSHarry Wentland 228f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 229f0e3db90SHarry Wentland 2304562236bSHarry Wentland struct resource_pool { 2314562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 2328feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 2334562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 2344562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 235d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 2364562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 2374562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 2384562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 239c9ef081dSYue Hin Lau struct hubbub *hubbub; 240cc408d72SDmytro Laktyushkin struct mpc *mpc; 2410f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 2421877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 243c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 244c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 245c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 2464562236bSHarry Wentland 247345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 248345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 249345429a6SHarry Wentland struct { 250345429a6SHarry Wentland unsigned int gsl_0:1; 251345429a6SHarry Wentland unsigned int gsl_1:1; 252345429a6SHarry Wentland unsigned int gsl_2:1; 253345429a6SHarry Wentland } gsl_groups; 254345429a6SHarry Wentland 25597bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 256345429a6SHarry Wentland 2574562236bSHarry Wentland unsigned int pipe_count; 2584562236bSHarry Wentland unsigned int underlay_pipe_index; 2594562236bSHarry Wentland unsigned int stream_enc_count; 260929c3aaaSEric Bernstein 261e1f4328fSJimmy Kizito /* An array for accessing the link encoder objects that have been created. 262e1f4328fSJimmy Kizito * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 263e1f4328fSJimmy Kizito */ 264e1f4328fSJimmy Kizito struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 265e1f4328fSJimmy Kizito /* Number of DIG link encoder objects created - i.e. number of valid 266e1f4328fSJimmy Kizito * entries in link_encoders array. 267e1f4328fSJimmy Kizito */ 268e1f4328fSJimmy Kizito unsigned int dig_link_enc_count; 269eabf2019SJimmy Kizito /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 270eabf2019SJimmy Kizito unsigned int usb4_dpia_count; 271e1f4328fSJimmy Kizito 27283228ebbSFangzhi Zuo unsigned int hpo_dp_stream_enc_count; 27383228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 2743bc8d921SFangzhi Zuo unsigned int hpo_dp_link_enc_count; 2753bc8d921SFangzhi Zuo struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 2765dba4991SBhawanpreet Lakha struct dc_3dlut *mpc_lut[MAX_PIPES]; 2775dba4991SBhawanpreet Lakha struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 27859b8ca24SAlex Hung 27933d7598dSJun Lei struct { 28033d7598dSJun Lei unsigned int xtalin_clock_inKhz; 28133d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 28233d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 28333d7598dSJun Lei } ref_clocks; 2843be1406aSYongqiang Sun unsigned int timing_generator_count; 285345429a6SHarry Wentland unsigned int mpcc_count; 2864562236bSHarry Wentland 287345429a6SHarry Wentland unsigned int writeback_pipe_count; 2884562236bSHarry Wentland /* 2894562236bSHarry Wentland * reserved clock source for DP 2904562236bSHarry Wentland */ 2914562236bSHarry Wentland struct clock_source *dp_clock_source; 2924562236bSHarry Wentland 2934562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 2944562236bSHarry Wentland unsigned int clk_src_count; 2954562236bSHarry Wentland 2967352193aSTai Man struct audio *audios[MAX_AUDIOS]; 2974562236bSHarry Wentland unsigned int audio_count; 2984562236bSHarry Wentland struct audio_support audio_support; 2994562236bSHarry Wentland 300ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 3014562236bSHarry Wentland struct irq_service *irqs; 3024562236bSHarry Wentland 3035e7773a2SAnthony Koo struct abm *abm; 3045e7773a2SAnthony Koo struct dmcu *dmcu; 3054c1a1335SWyatt Wood struct dmub_psr *psr; 3065e7773a2SAnthony Koo 307*e0138644SBhawanpreet Lakha struct dmub_replay *replay; 308*e0138644SBhawanpreet Lakha 309d99f1387SBhawanpreet Lakha struct abm *multiple_abms[MAX_PIPES]; 310d99f1387SBhawanpreet Lakha 3114562236bSHarry Wentland const struct resource_funcs *funcs; 3124562236bSHarry Wentland const struct resource_caps *res_cap; 313d9a07577SJun Lei 314d9a07577SJun Lei struct ddc_service *oem_device; 3154562236bSHarry Wentland }; 3164562236bSHarry Wentland 317f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 31869338c1fSDmytro Laktyushkin int dppclk_khz; 319799c5b9cSWesley Chalmers 320f553e681SDmytro Laktyushkin }; 321f553e681SDmytro Laktyushkin 32279b06f0cSHarry Wentland struct stream_resource { 323a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 32497bda032SHarry Wentland struct display_stream_compressor *dsc; 3256b670fa9SHarry Wentland struct timing_generator *tg; 3268e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 32783228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 328afaacef4SHarry Wentland struct audio *audio; 32910688217SHarry Wentland 33010688217SHarry Wentland struct pixel_clk_params pix_clk_params; 33196c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 3329aef1a31SSivapiriyanKumarasamy 3339aef1a31SSivapiriyanKumarasamy struct abm *abm; 334345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 335345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 336345429a6SHarry Wentland */ 337345429a6SHarry Wentland uint8_t gsl_group; 33879b06f0cSHarry Wentland }; 33979b06f0cSHarry Wentland 34079b06f0cSHarry Wentland struct plane_resource { 3416702a9acSHarry Wentland struct scaler_data scl_data; 3428feabd03SYue Hin Lau struct hubp *hubp; 34386a66c4eSHarry Wentland struct mem_input *mi; 34486a66c4eSHarry Wentland struct input_pixel_processor *ipp; 34586a66c4eSHarry Wentland struct transform *xfm; 346d94585a0SYue Hin Lau struct dpp *dpp; 347e07f541fSYongqiang Sun uint8_t mpcc_inst; 348f553e681SDmytro Laktyushkin 349f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 35079b06f0cSHarry Wentland }; 35179b06f0cSHarry Wentland 3524c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 3534c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 3544c3adc0bSWenjing Liu 355ef30f441SWenjing Liu /* all mappable hardware resources used to enable a link */ 356ef30f441SWenjing Liu struct link_resource { 357f3fac948SWenjing Liu struct hpo_dp_link_encoder *hpo_dp_link_enc; 358ef30f441SWenjing Liu }; 359ef30f441SWenjing Liu 360017860c9SWenjing Liu struct link_config { 361017860c9SWenjing Liu struct dc_link_settings dp_link_settings; 362017860c9SWenjing Liu }; 36324c18794SDmytro Laktyushkin union pipe_update_flags { 36424c18794SDmytro Laktyushkin struct { 36524c18794SDmytro Laktyushkin uint32_t enable : 1; 36624c18794SDmytro Laktyushkin uint32_t disable : 1; 36724c18794SDmytro Laktyushkin uint32_t odm : 1; 36824c18794SDmytro Laktyushkin uint32_t global_sync : 1; 36924c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 37024c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 37124c18794SDmytro Laktyushkin uint32_t mpcc : 1; 37224c18794SDmytro Laktyushkin uint32_t dppclk : 1; 37324c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 37424c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 37524c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 37624c18794SDmytro Laktyushkin uint32_t scaler : 1; 37724c18794SDmytro Laktyushkin uint32_t viewport : 1; 378498563cfSJinZe.Xu uint32_t plane_changed : 1; 379ba5a5371SNicholas Kazlauskas uint32_t det_size : 1; 380fe9fa385SAlvin Lee uint32_t unbounded_req : 1; 38124c18794SDmytro Laktyushkin } bits; 38224c18794SDmytro Laktyushkin uint32_t raw; 38324c18794SDmytro Laktyushkin }; 38424c18794SDmytro Laktyushkin 3854562236bSHarry Wentland struct pipe_ctx { 3863be5262eSHarry Wentland struct dc_plane_state *plane_state; 3870971c40eSHarry Wentland struct dc_stream_state *stream; 3884562236bSHarry Wentland 38979b06f0cSHarry Wentland struct plane_resource plane_res; 390fdf17f10SRodrigo Siqueira 391fdf17f10SRodrigo Siqueira /** 392fdf17f10SRodrigo Siqueira * @stream_res: Reference to DCN resource components such OPP and DSC. 393fdf17f10SRodrigo Siqueira */ 39479b06f0cSHarry Wentland struct stream_resource stream_res; 395ef30f441SWenjing Liu struct link_resource link_res; 39679b06f0cSHarry Wentland 3974562236bSHarry Wentland struct clock_source *clock_source; 3984562236bSHarry Wentland 3994562236bSHarry Wentland struct pll_settings pll_settings; 4004562236bSHarry Wentland 4016a0114e0SRodrigo Siqueira /** 4026a0114e0SRodrigo Siqueira * @link_config: 4036a0114e0SRodrigo Siqueira * 4046a0114e0SRodrigo Siqueira * link config records software decision for what link config should be 405017860c9SWenjing Liu * enabled given current link capability and stream during hw resource 406017860c9SWenjing Liu * mapping. This is to decouple the dependency on link capability during 407017860c9SWenjing Liu * dc commit or update. 408017860c9SWenjing Liu */ 409017860c9SWenjing Liu struct link_config link_config; 410017860c9SWenjing Liu 4114562236bSHarry Wentland uint8_t pipe_idx; 412a896f870SMeenakshikumar Somasundaram uint8_t pipe_idx_syncd; 4134562236bSHarry Wentland 4144562236bSHarry Wentland struct pipe_ctx *top_pipe; 4154562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 416b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 417b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 418f0558542SDmytro Laktyushkin 419ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 420ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 421ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 422ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 4231f2fcc81SHarry Wentland struct _vcs_dpi_display_rq_params_st dml_rq_param; 4241f2fcc81SHarry Wentland struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 4251f2fcc81SHarry Wentland struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 426ba5a5371SNicholas Kazlauskas int det_buffer_size_kb; 427ba5a5371SNicholas Kazlauskas bool unbounded_req; 428238debcaSDillon Varone unsigned int surface_size_in_mall_bytes; 42959b8ca24SAlex Hung 430345429a6SHarry Wentland struct dwbc *dwbc; 431345429a6SHarry Wentland struct mcif_wb *mcif_wb; 432238debcaSDillon Varone union pipe_update_flags update_flags; 433d205a800SLeo (Hanghong) Ma struct tg_color visual_confirm_color; 434d205a800SLeo (Hanghong) Ma bool has_vactive_margin; 4354562236bSHarry Wentland }; 4364562236bSHarry Wentland 4370d4b4253SJimmy Kizito /* Data used for dynamic link encoder assignment. 4380d4b4253SJimmy Kizito * Tracks current and future assignments; available link encoders; 4390d4b4253SJimmy Kizito * and mode of operation (whether to use current or future assignments). 4400d4b4253SJimmy Kizito */ 4410d4b4253SJimmy Kizito struct link_enc_cfg_context { 4420d4b4253SJimmy Kizito enum link_enc_cfg_mode mode; 4430d4b4253SJimmy Kizito struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 4440d4b4253SJimmy Kizito enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 4450d4b4253SJimmy Kizito struct link_enc_assignment transient_assignments[MAX_PIPES]; 4460d4b4253SJimmy Kizito }; 4470d4b4253SJimmy Kizito 4484562236bSHarry Wentland struct resource_context { 4494562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 4504562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 4514562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 4524562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 4534562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 454345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 4550d4b4253SJimmy Kizito struct link_enc_cfg_context link_enc_cfg_ctx; 45683228ebbSFangzhi Zuo bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 4576dd8931bSWenjing Liu unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 4586dd8931bSWenjing Liu int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 4595dba4991SBhawanpreet Lakha bool is_mpc_3dlut_acquired[MAX_PIPES]; 4604562236bSHarry Wentland }; 4614562236bSHarry Wentland 4629037d802SDmytro Laktyushkin struct dce_bw_output { 4639037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 4649037d802SDmytro Laktyushkin bool cpup_state_change_enable; 4659037d802SDmytro Laktyushkin bool stutter_mode_enable; 4669037d802SDmytro Laktyushkin bool nbp_state_change_enable; 4679037d802SDmytro Laktyushkin bool all_displays_in_sync; 4689037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 4699037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 470b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 4719037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 4729037d802SDmytro Laktyushkin int sclk_khz; 4739037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 4749037d802SDmytro Laktyushkin int yclk_khz; 4759037d802SDmytro Laktyushkin int dispclk_khz; 4769037d802SDmytro Laktyushkin int blackout_recovery_time_us; 4779037d802SDmytro Laktyushkin }; 4789037d802SDmytro Laktyushkin 479345429a6SHarry Wentland struct dcn_bw_writeback { 480345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 481345429a6SHarry Wentland }; 482345429a6SHarry Wentland 4839037d802SDmytro Laktyushkin struct dcn_bw_output { 484d578839cSDmytro Laktyushkin struct dc_clocks clk; 4859037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 486345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 487ba5a5371SNicholas Kazlauskas int compbuf_size_kb; 488238debcaSDillon Varone unsigned int mall_ss_size_bytes; 489238debcaSDillon Varone unsigned int mall_ss_psr_active_size_bytes; 490238debcaSDillon Varone unsigned int mall_subvp_size_bytes; 49120dad381SJun Lei unsigned int legacy_svp_drr_stream_index; 49220dad381SJun Lei bool legacy_svp_drr_stream_index_valid; 4939037d802SDmytro Laktyushkin }; 4949037d802SDmytro Laktyushkin 495813d20dcSAidan Wood union bw_output { 4969037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 4979037d802SDmytro Laktyushkin struct dce_bw_output dce; 4989037d802SDmytro Laktyushkin }; 4999037d802SDmytro Laktyushkin 500813d20dcSAidan Wood struct bw_context { 501813d20dcSAidan Wood union bw_output bw; 502813d20dcSAidan Wood struct display_mode_lib dml; 503813d20dcSAidan Wood }; 504fa0fc4fbSRodrigo Siqueira 5050baae624SAlvin Lee struct dc_dmub_cmd { 5060baae624SAlvin Lee union dmub_rb_cmd dmub_cmd; 5070baae624SAlvin Lee enum dm_dmub_wait_type wait_type; 5080baae624SAlvin Lee }; 5090baae624SAlvin Lee 5102119aa17SDavid Francis /** 511fa0fc4fbSRodrigo Siqueira * struct dc_state - The full description of a state requested by users 5122119aa17SDavid Francis */ 513608ac7bbSJerry Zuo struct dc_state { 514fa0fc4fbSRodrigo Siqueira /** 515fa0fc4fbSRodrigo Siqueira * @streams: Stream state properties 516fa0fc4fbSRodrigo Siqueira */ 5170971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 518fa0fc4fbSRodrigo Siqueira 519fa0fc4fbSRodrigo Siqueira /** 520fa0fc4fbSRodrigo Siqueira * @stream_status: Planes status on a given stream 521fa0fc4fbSRodrigo Siqueira */ 522ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 523fa0fc4fbSRodrigo Siqueira 524fa0fc4fbSRodrigo Siqueira /** 525fa0fc4fbSRodrigo Siqueira * @stream_count: Total of streams in use 526fa0fc4fbSRodrigo Siqueira */ 527ab2541b6SAric Cyr uint8_t stream_count; 5280825d965SEric Yang uint8_t stream_mask; 5294562236bSHarry Wentland 530fa0fc4fbSRodrigo Siqueira /** 531fa0fc4fbSRodrigo Siqueira * @res_ctx: Persistent state of resources 532fa0fc4fbSRodrigo Siqueira */ 5334562236bSHarry Wentland struct resource_context res_ctx; 5344562236bSHarry Wentland 535fa0fc4fbSRodrigo Siqueira /** 536fa0fc4fbSRodrigo Siqueira * @pp_display_cfg: PowerPlay clocks and settings 537fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 538fa0fc4fbSRodrigo Siqueira */ 5394562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 540fa0fc4fbSRodrigo Siqueira 541fa0fc4fbSRodrigo Siqueira /** 542fa0fc4fbSRodrigo Siqueira * @dcn_bw_vars: non-stack memory to support bandwidth calculations 543fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 544fa0fc4fbSRodrigo Siqueira */ 545ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 5468a76708eSAndrey Grodzovsky 5470de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 548ab8db3e1SAndrey Grodzovsky 5496a0114e0SRodrigo Siqueira /** 5509ed90489SAric Cyr * @bw_ctx: The output from bandwidth and watermark calculations and the DML 5519ed90489SAric Cyr * 5529ed90489SAric Cyr * Each context must have its own instance of VBA, and in order to 5539ed90489SAric Cyr * initialize and obtain IP and SOC, the base DML instance from DC is 5549ed90489SAric Cyr * initially copied into every context. 5559ed90489SAric Cyr */ 5569ed90489SAric Cyr struct bw_context bw_ctx; 5579ed90489SAric Cyr 5580baae624SAlvin Lee struct block_sequence block_sequence[50]; 5590baae624SAlvin Lee unsigned int block_sequence_steps; 5600baae624SAlvin Lee struct dc_dmub_cmd dc_dmub_cmd[10]; 5610baae624SAlvin Lee unsigned int dmub_cmd_count; 5620baae624SAlvin Lee 5639ed90489SAric Cyr /** 5646a0114e0SRodrigo Siqueira * @refcount: refcount reference 5656a0114e0SRodrigo Siqueira * 5666a0114e0SRodrigo Siqueira * Notice that dc_state is used around the code to capture the current 5676a0114e0SRodrigo Siqueira * context, so we need to pass it everywhere. That's why we want to use 5686a0114e0SRodrigo Siqueira * kref in this struct. 5696a0114e0SRodrigo Siqueira */ 5708ee5702aSDave Airlie struct kref refcount; 5716b85151fSMartin Leung 5726b85151fSMartin Leung struct { 5736b85151fSMartin Leung unsigned int stutter_period_us; 5746b85151fSMartin Leung } perf_params; 5754562236bSHarry Wentland }; 5764562236bSHarry Wentland 577*e0138644SBhawanpreet Lakha struct replay_context { 578*e0138644SBhawanpreet Lakha /* ddc line */ 579*e0138644SBhawanpreet Lakha enum channel_id aux_inst; 580*e0138644SBhawanpreet Lakha /* Transmitter id */ 581*e0138644SBhawanpreet Lakha enum transmitter digbe_inst; 582*e0138644SBhawanpreet Lakha /* Engine Id is used for Dig Be source select */ 583*e0138644SBhawanpreet Lakha enum engine_id digfe_inst; 584*e0138644SBhawanpreet Lakha /* Controller Id used for Dig Fe source select */ 585*e0138644SBhawanpreet Lakha enum controller_id controllerId; 586*e0138644SBhawanpreet Lakha unsigned int line_time_in_ns; 587*e0138644SBhawanpreet Lakha }; 588*e0138644SBhawanpreet Lakha 589*e0138644SBhawanpreet Lakha enum dc_replay_enable { 590*e0138644SBhawanpreet Lakha DC_REPLAY_DISABLE = 0, 591*e0138644SBhawanpreet Lakha DC_REPLAY_ENABLE = 1, 592*e0138644SBhawanpreet Lakha }; 593*e0138644SBhawanpreet Lakha 594e4b0eac3SJasdeep Dhillon struct dc_bounding_box_max_clk { 595e4b0eac3SJasdeep Dhillon int max_dcfclk_mhz; 596e4b0eac3SJasdeep Dhillon int max_dispclk_mhz; 597e4b0eac3SJasdeep Dhillon int max_dppclk_mhz; 598e4b0eac3SJasdeep Dhillon int max_phyclk_mhz; 599e4b0eac3SJasdeep Dhillon }; 600e4b0eac3SJasdeep Dhillon 6014562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 602